David Wu 2e4ce50d1a rockchip: clk: Add rv1108 SARADC clock support ... The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-10-01 00:33:29 +02:00
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clk
clock	rockchip: clk: Add rv1108 SARADC clock support	2017-10-01 00:33:29 +02:00
comphy
dma
gpio
input
interrupt-controller
interrupt-router
mailbox
media
memory	ARM: DTS: stm32: adapt stm32h7 dts files for U-boot	2017-09-22 07:40:03 -04:00
mfd	dm: reset: add stm32 reset driver	2017-09-22 07:40:01 -04:00
mrc
net
phy
pinctrl	ARM: DTS: stm32: add stm32h743i-disco files	2017-09-22 07:40:02 -04:00
pmic
power
power-domain
pwm
regulator
reset
sound
thermal
video