mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
7f9be61b22
This change force sets the default state for SFP TX pin. Change-Id: Iaaee73b8c4a6a4abc5fba9b1f88a2225cb1ed39d Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
183 lines
3.4 KiB
Text
183 lines
3.4 KiB
Text
/*
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "ipq5332-soc.dtsi"
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/ {
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machid = <0x1060003>;
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config_name = "config@db-mi02.1", "config-db-mi02.1";
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aliases {
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console = "/serial@78AF000";
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nand = "/nand-controller@79B0000";
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mmc = "/sdhci@7804000";
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usb0 = "/xhci@8a00000";
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pci1 = "/pci@18000000";
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i2c0 = "/i2c@78B6000";
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};
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serial@78AF000 {
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status = "ok";
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serial_gpio {
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blsp0_uart_rx {
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gpio = <18>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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blsp0_uart_tx {
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gpio = <19>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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};
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};
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i2c@78B6000 {
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i2c_gpio {
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gpio1 {
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gpio = <29>;
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func = <3>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_ENABLE>;
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};
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gpio2 {
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gpio = <30>;
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func = <3>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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oe = <GPIO_OE_ENABLE>;
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};
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};
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};
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nand: nand-controller@79B0000 {
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nand_gpio {
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qspi_dat3 {
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gpio = <8>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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};
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qspi_dat2 {
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gpio = <9>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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};
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qspi_dat1 {
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gpio = <10>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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};
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qspi_dat0 {
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gpio = <11>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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};
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qspi_cs_n {
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gpio = <12>;
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func = <2>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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qspi_clk {
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gpio = <13>;
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func = <2>;
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pull = <GPIO_PULL_DOWN>;
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drvstr = <GPIO_8MA>;
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};
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};
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};
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mmc: sdhci@7804000 {
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mmc_gpio {
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emmc_dat3 {
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gpio = <8>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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emmc_dat2 {
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gpio = <9>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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emmc_dat1 {
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gpio = <10>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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emmc_dat0 {
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gpio = <11>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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emmc_cmd{
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gpio = <12>;
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func = <1>;
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pull = <GPIO_PULL_UP>;
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drvstr = <GPIO_8MA>;
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};
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emmc_clk{
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gpio = <13>;
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func = <1>;
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pull = <GPIO_NO_PULL>;
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drvstr = <GPIO_8MA>;
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};
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};
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};
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pci1: pci@18000000 {
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status = "ok";
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perst_gpio = <47>;
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lane = <1>;
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pci_gpio {
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pci_rst {
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gpio = <47>;
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pull = <GPIO_PULL_UP>;
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oe = <GPIO_OE_ENABLE>;
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};
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};
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};
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ess-switch {
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switch_mac_mode0 = <PORT_WRAPPER_10GBASE_R>;
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switch_mac_mode1 = <PORT_WRAPPER_10GBASE_R>;
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sfp_gpio = <15 24>;
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sfp_gpio_cnt = <2>;
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port_phyinfo {
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port@0 {
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phy_type = <SFP_PHY_TYPE>;
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uniphy_id = <0>;
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uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
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};
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port@1 {
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phy_type = <SFP_PHY_TYPE>;
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uniphy_id = <1>;
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uniphy_mode = <PORT_WRAPPER_10GBASE_R>;
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};
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};
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};
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};
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