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Hao Zhang 101eec50f0 keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
..
asm keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 2014-07-25 16:26:09 -04:00