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075d0b81e8
Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> |
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| 74xx_7xx | ||
| arm720t | ||
| arm920t | ||
| arm925t | ||
| arm926ejs | ||
| arm946es | ||
| arm1136 | ||
| arm1176 | ||
| arm_intcm | ||
| at32ap | ||
| blackfin | ||
| i386 | ||
| ixp | ||
| leon2 | ||
| leon3 | ||
| lh7a40x | ||
| mcf52x2 | ||
| mcf523x | ||
| mcf532x | ||
| mcf547x_8x | ||
| mcf5227x | ||
| mcf5445x | ||
| microblaze | ||
| mips | ||
| mpc5xx | ||
| mpc5xxx | ||
| mpc8xx | ||
| mpc8xxx/ddr | ||
| mpc83xx | ||
| mpc85xx | ||
| mpc86xx | ||
| mpc512x | ||
| mpc824x | ||
| mpc8220 | ||
| mpc8260 | ||
| nios | ||
| nios2 | ||
| ppc4xx | ||
| pxa | ||
| s3c44b0 | ||
| sa1100 | ||
| sh2 | ||
| sh3 | ||
| sh4 | ||