Paul Burton 639200f6a0 MIPS: Ensure cache ops complete in mips_cache_reset ... Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>		2016-09-21 15:04:04 +02:00
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ashldi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
ashrdi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
bootm.c	libfdt: Introduce new ARCH_FIXUP_FDT option	2016-07-31 19:37:08 -06:00
cache.c	MIPS: L2 cache support	2016-09-21 15:04:04 +02:00
cache_init.S	MIPS: Ensure cache ops complete in mips_cache_reset	2016-09-21 15:04:04 +02:00
libgcc.h	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
lshrdi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
Makefile	MIPS: Support dynamic I/O port base address	2016-02-01 22:13:25 +01:00