From f62b258e045a6ba29cacaba7fe91f4831e225cd6 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Date: Mon, 12 Sep 2016 18:55:45 +0530
Subject: [PATCH] ipq8074: Adding qpic-nand gpio configuration to device tree

Change-Id: Iac2039fa6eac0143ae8b7f086e4ac1b91070899c
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
---
 arch/arm/dts/ipq807x-soc.dtsi | 102 ++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm/dts/ipq807x-soc.dtsi b/arch/arm/dts/ipq807x-soc.dtsi
index b3714047c6..dedd11d16c 100644
--- a/arch/arm/dts/ipq807x-soc.dtsi
+++ b/arch/arm/dts/ipq807x-soc.dtsi
@@ -37,6 +37,108 @@
 		compatible = "qcom,qpic-nand.1.5.20";
 		reg = <0x79B0000 0x10000>;
 
+		nand_gpio {
+			gpio1 {
+				gpio = <1>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio2 {
+				gpio = <3>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio3 {
+				gpio = <4>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio4 {
+				gpio = <5>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio5 {
+				gpio = <6>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio6 {
+				gpio = <7>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio7 {
+				gpio = <8>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio8 {
+				gpio = <10>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio9 {
+				gpio = <11>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio10 {
+				gpio = <12>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio11 {
+				gpio = <13>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio12 {
+				gpio = <14>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio13 {
+				gpio = <15>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+			gpio14 {
+				gpio = <17>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_DISABLE>;
+			};
+
+		};
+
 	};
 
 	xhci@8a00000 {