From d96ce7627722900a1688808582aaf2f4e509fab5 Mon Sep 17 00:00:00 2001 From: Rajkumar Ayyasamy Date: Tue, 12 Dec 2017 18:56:17 +0530 Subject: [PATCH] ipq40xx: move to spi dma driver from fifo driver Enabling spi dma driver for ipq40xx. This patch also enables rx and tx pipe configurable from dts. Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b Signed-off-by: Rajkumar Ayyasamy --- arch/arm/dts/ipq40xx-soc.dtsi | 4 ++++ arch/arm/dts/ipq807x-soc.dtsi | 2 ++ drivers/spi/Makefile | 2 +- drivers/spi/qca_qup_spi_bam.c | 43 ++++++++++++++++++++++++++++------- drivers/spi/qca_qup_spi_bam.h | 1 + include/configs/ipq40xx.h | 1 + 6 files changed, 44 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/ipq40xx-soc.dtsi b/arch/arm/dts/ipq40xx-soc.dtsi index adaabc4d00..d4b8d0098b 100644 --- a/arch/arm/dts/ipq40xx-soc.dtsi +++ b/arch/arm/dts/ipq40xx-soc.dtsi @@ -42,6 +42,10 @@ spi { status = "disabled"; + wr_pipe_0 = <4>; + rd_pipe_0 = <5>; + wr_pipe_1 = <6>; + rd_pipe_1 = <7>; }; nand@79B0000 { diff --git a/arch/arm/dts/ipq807x-soc.dtsi b/arch/arm/dts/ipq807x-soc.dtsi index 8d641cdf27..98b9f7928a 100644 --- a/arch/arm/dts/ipq807x-soc.dtsi +++ b/arch/arm/dts/ipq807x-soc.dtsi @@ -74,6 +74,8 @@ status = "ok"; compatible = "qcom,spi-qup-v2.7.0"; + wr_pipe_0 = <12>; + rd_pipe_0 = <13>; spi_gpio { gpio1 { gpio = <38>; diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index abc0ab15af..fa4355b43a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o ifdef CONFIG_QCA_SPI -obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi.o +obj-$(CONFIG_ARCH_IPQ40xx) += qca_qup_spi_bam.o obj-$(CONFIG_ARCH_IPQ807x) += qca_qup_spi_bam.o obj-$(CONFIG_ARCH_IPQ806x) += ipq_spi.o endif diff --git a/drivers/spi/qca_qup_spi_bam.c b/drivers/spi/qca_qup_spi_bam.c index 3d695d8ef9..b5668d39e1 100644 --- a/drivers/spi/qca_qup_spi_bam.c +++ b/drivers/spi/qca_qup_spi_bam.c @@ -36,6 +36,12 @@ #include #include "qca_qup_spi_bam.h" +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int read_pipe[NO_OF_QUPS]; +static unsigned int write_pipe[NO_OF_QUPS]; +static unsigned char qup_pipe_initialized = 0; + static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay) { @@ -161,37 +167,58 @@ void spi_init() /* do nothing */ } +static void qup_pipe_init() +{ + char rd_pipe_name[10], wr_pipe_name[10]; + int node,i; + + qup_pipe_initialized = 1; + node = fdt_path_offset(gd->fdt_blob, "/spi"); + if (node >= 0) { + for(i = 0; i < NO_OF_QUPS; i++) { + + snprintf(rd_pipe_name, sizeof(rd_pipe_name), + "rd_pipe_%01d", i); + + snprintf(wr_pipe_name, sizeof(wr_pipe_name), + "wr_pipe_%01d", i); + + read_pipe[i] = fdtdec_get_uint(gd->fdt_blob, + node, rd_pipe_name, 0); + write_pipe[i] = fdtdec_get_uint(gd->fdt_blob, + node, wr_pipe_name, 0); + } + } +} + int qup_bam_init(struct ipq_spi_slave *ds) { - unsigned int read_pipe = QUP0_DATA_PRODUCER_PIPE; - unsigned int write_pipe = QUP0_DATA_CONSUMER_PIPE; uint8_t read_pipe_grp = QUP0_DATA_PRODUCER_PIPE_GRP; uint8_t write_pipe_grp = QUP0_DATA_CONSUMER_PIPE_GRP; int bam_ret; + if (!qup_pipe_initialized) + qup_pipe_init(); + /* Pipe numbers based on the QUP index */ if (ds->slave.bus == BLSP0_SPI) { - read_pipe = QUP0_DATA_PRODUCER_PIPE; - write_pipe = QUP0_DATA_CONSUMER_PIPE; read_pipe_grp = QUP0_DATA_PRODUCER_PIPE_GRP; write_pipe_grp = QUP0_DATA_CONSUMER_PIPE_GRP; } else if (ds->slave.bus == BLSP1_SPI) { - read_pipe = QUP1_DATA_PRODUCER_PIPE; - write_pipe = QUP1_DATA_CONSUMER_PIPE; read_pipe_grp = QUP1_DATA_PRODUCER_PIPE_GRP; write_pipe_grp = QUP1_DATA_CONSUMER_PIPE_GRP; } bam.base = BLSP0_BAM_BASE; /* Set Read Pipe Params */ - bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num = read_pipe; + bam.pipe[DATA_PRODUCER_PIPE_INDEX].pipe_num = read_pipe[ds->slave.bus]; bam.pipe[DATA_PRODUCER_PIPE_INDEX].trans_type = BAM2SYS; bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.size = QUP_BAM_DATA_FIFO_SIZE; bam.pipe[DATA_PRODUCER_PIPE_INDEX].fifo.head = qup_spi_data_desc_fifo; bam.pipe[DATA_PRODUCER_PIPE_INDEX].lock_grp = read_pipe_grp; /* Set Write pipe params. */ - bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = write_pipe; + bam.pipe[DATA_CONSUMER_PIPE_INDEX].pipe_num = write_pipe[ds->slave.bus]; bam.pipe[DATA_CONSUMER_PIPE_INDEX].trans_type = SYS2BAM; bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.size = QUP_BAM_DATA_FIFO_SIZE; bam.pipe[DATA_CONSUMER_PIPE_INDEX].fifo.head = qup_spi_data_desc_fifo; diff --git a/drivers/spi/qca_qup_spi_bam.h b/drivers/spi/qca_qup_spi_bam.h index 41e74f613d..93077f700a 100644 --- a/drivers/spi/qca_qup_spi_bam.h +++ b/drivers/spi/qca_qup_spi_bam.h @@ -282,6 +282,7 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) #define QUP1_DATA_PRODUCER_PIPE_GRP 0 #define QUP1_DATA_CONSUMER_PIPE_GRP 0 +#define NO_OF_QUPS 2 /* QUP EE */ #define QUP_SPI_EE 0 diff --git a/include/configs/ipq40xx.h b/include/configs/ipq40xx.h index 2bc1de7079..65b4fb9079 100644 --- a/include/configs/ipq40xx.h +++ b/include/configs/ipq40xx.h @@ -153,6 +153,7 @@ typedef struct { #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#define CONFIG_QUP_SPI_USE_DMA 1 /* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */