From f2741fbe5aeb42694a9c4ea01bfa460018dd1f8f Mon Sep 17 00:00:00 2001 From: sameeruddin shaik Date: Mon, 29 Oct 2018 16:52:58 +0530 Subject: [PATCH] ipq806x: Disable relocation in uboot-2016 This change will resolve the "L2 Master port decode error" print in the Kernel log. Change-Id: I12fd39a85093cc1d7fab336898e039a61eeb5565 Signed-off-by: sameeruddin shaik --- arch/arm/include/asm/system.h | 6 ++++++ arch/arm/lib/cache-cp15.c | 5 +++-- arch/arm/lib/crt0.S | 4 ++-- common/board_f.c | 2 +- include/configs/ipq40xx.h | 1 + include/configs/ipq806x.h | 9 ++++++--- include/configs/ipq807x.h | 1 + 7 files changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 71b31085b4..cc79699275 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -240,6 +240,8 @@ enum dcache_option { DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), + SHARED_DEVICE = TTB_SECT_B_MASK | TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | + TTB_SECT_XN_MASK | TTB_SECT, }; #else /* options available for data cache on each page */ @@ -248,6 +250,10 @@ enum dcache_option { DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, DCACHE_WRITEALLOC = 0x16, + /* Regions other than DDR has to be marked as "shared device" + * They have B bit set, C bit unset, S(hared) bit set, XN bit set + */ + SHARED_DEVICE = 0x10016, }; #endif diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0f7f8e26ec..629be6e9cb 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -62,7 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ6018) +#if defined(CONFIG_IPQ_NO_RELOC) #define UBOOT_CACHE_SETUP 0x100e #define GEN_CACHE_SETUP 0x101e @@ -90,9 +90,10 @@ void mmu_setup(void) u32 reg; arm_init_before_mmu(); + memset(gd->arch.tlb_addr, 0, gd->arch.tlb_size); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) - set_section_dcache(i, DCACHE_WRITEALLOC); + set_section_dcache(i, SHARED_DEVICE); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { dram_bank_mmu_setup(i); diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index f069495922..e8afb7331f 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -86,7 +86,7 @@ ENTRY(_main) bl board_init_f_mem mov sp, r0 -#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ6018) +#if defined(CONFIG_IPQ_NO_RELOC) || defined(CONFIG_ARCH_IPQ6018) ldr r0, =__bss_start /* this is auto-relocated! */ #ifdef CONFIG_USE_ARCH_MEMSET @@ -156,7 +156,7 @@ here: cmp r0, #0 movne sp, r0 # endif -#if !defined(CONFIG_ARCH_IPQ807x) && !defined(CONFIG_ARCH_IPQ40xx) && !defined(CONFIG_ARCH_IPQ6018) +#if !defined(CONFIG_IPQ_NO_RELOC) && !defined(CONFIG_ARCH_IPQ6018) ldr r0, =__bss_start /* this is auto-relocated! */ #ifdef CONFIG_USE_ARCH_MEMSET diff --git a/common/board_f.c b/common/board_f.c index e48b92bcab..9c2e1aaf7b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1062,7 +1062,7 @@ void board_init_f(ulong boot_flags) gd->flags = boot_flags; gd->have_console = 0; -#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ6018) +#if defined(CONFIG_IPQ_NO_RELOC) gd->flags |= GD_FLG_SKIP_RELOC; #endif diff --git a/include/configs/ipq40xx.h b/include/configs/ipq40xx.h index a9b8dddf34..96a021f6e9 100644 --- a/include/configs/ipq40xx.h +++ b/include/configs/ipq40xx.h @@ -25,6 +25,7 @@ #endif #define CONFIG_IPQ40XX +#define CONFIG_IPQ_NO_RELOC #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/include/configs/ipq806x.h b/include/configs/ipq806x.h index 9fa35b1ef5..3e359438a0 100644 --- a/include/configs/ipq806x.h +++ b/include/configs/ipq806x.h @@ -34,6 +34,7 @@ #endif /* !DO_DEPS_ONLY */ #define CONFIG_IPQ806X +#define CONFIG_IPQ_NO_RELOC #define CONFIG_SMP_CMD_SUPPORT #ifdef CONFIG_SMP_CMD_SUPPORT #define NR_CPUS 2 @@ -43,7 +44,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_IPQ806X_ENV #define CONFIG_SYS_BOOTM_LEN (64 << 20) -#define CONFIG_IPQ_FDT_HIGH 0x48000000 +#define CONFIG_IPQ_FDT_HIGH 0xffffffff #define CONFIG_BOOTARGS "console=ttyMSM0,115200n8" #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_VSNPRINTF @@ -132,7 +133,7 @@ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x41200000 +#define CONFIG_SYS_TEXT_BASE 0x42000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 #define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20)) @@ -244,7 +245,9 @@ typedef struct { #define IPQ_TEMP_DUMP_ADDR (IPQ_MEM_RESERVE_BASE(nsstcmdump)) #define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) -#define IPQ_TFTP_MAX_ADDR (gd->start_addr_sp - (4 << 20)) +#define IPQ_TFTP_MAX_ADDR (gd->bd->bi_dram[0].start + \ + gd->bd->bi_dram[0].size) + #define CONFIG_QCA_SMEM_BASE CONFIG_SYS_SDRAM_BASE + 0x1000000 #endif /* __ASSEMBLY__ */ diff --git a/include/configs/ipq807x.h b/include/configs/ipq807x.h index 5f47bc1667..604475f732 100644 --- a/include/configs/ipq807x.h +++ b/include/configs/ipq807x.h @@ -29,6 +29,7 @@ */ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_IPQ_NO_RELOC #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_CACHELINE_SIZE 64