From efb97f9df08098652aaf5f41b01f0fdd82cfc085 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Thu, 7 May 2020 20:08:06 +0530 Subject: [PATCH] ipq5018: Uart clock update This changes update uart clock setting for 1.8Mhz Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: I406a0e3c86481d0fce9ac9aff489212ee5f709d9 --- arch/arm/dts/ipq5018-soc.dtsi | 4 +- board/qca/arm/ipq5018/ipq5018.c | 77 ++++++++++++++------------------- board/qca/arm/ipq5018/ipq5018.h | 11 ++--- 3 files changed, 42 insertions(+), 50 deletions(-) diff --git a/arch/arm/dts/ipq5018-soc.dtsi b/arch/arm/dts/ipq5018-soc.dtsi index e2ee00a00e..e139a29964 100644 --- a/arch/arm/dts/ipq5018-soc.dtsi +++ b/arch/arm/dts/ipq5018-soc.dtsi @@ -19,7 +19,9 @@ serial@78AF000 { compatible = "qca,ipq-uartdm"; reg = <0x78af000 0x200>; - id = <2>; + m_value = <0x24>; + n_value = <0xC31A>; + d_value = <0xC2F6>; bit_rate = <0xff>; status = "disabled"; }; diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index e5fc3c5cc5..85aa63d6f5 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -120,26 +120,6 @@ void uart1_set_rate_mnd(unsigned int m, writel(NOT_2D(two_d), GCC_BLSP1_UART1_APPS_D); } -int uart1_trigger_update(void) -{ - unsigned long cmd_rcgr; - int timeout = 0; - - cmd_rcgr = readl(GCC_BLSP1_UART1_APPS_CMD_RCGR); - cmd_rcgr |= UART1_CMD_RCGR_UPDATE; - writel(cmd_rcgr, GCC_BLSP1_UART1_APPS_CMD_RCGR); - - while (readl(GCC_BLSP1_UART1_APPS_CMD_RCGR) & UART1_CMD_RCGR_UPDATE) { - if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) { - printf("Timeout waiting for UART1 clock update\n"); - return -ETIMEDOUT; - udelay(1); - } - } - cmd_rcgr = readl(GCC_BLSP1_UART1_APPS_CMD_RCGR); - return 0; -} - void reset_board(void) { run_command("reset", 0); @@ -154,39 +134,48 @@ void uart1_toggle_clock(void) writel(cbcr_val, GCC_BLSP1_UART1_APPS_CBCR); } -void uart1_clock_config(unsigned int m, - unsigned int n, unsigned int two_d) +int uart1_trigger_update(void) { - uart1_configure_mux(); - uart1_set_rate_mnd(m, n, two_d); - uart1_trigger_update(); + unsigned long cmd_rcgr; + int timeout = 0; + + cmd_rcgr = readl(GCC_BLSP1_UART1_APPS_CMD_RCGR); + cmd_rcgr |= UART1_CMD_RCGR_UPDATE | UART1_CMD_RCGR_ROOT_EN; + writel(cmd_rcgr, GCC_BLSP1_UART1_APPS_CMD_RCGR); + + while (readl(GCC_BLSP1_UART1_APPS_CMD_RCGR) & UART1_CMD_RCGR_UPDATE) { + if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) { + printf("Timeout waiting for UART1 clock update\n"); + return -ETIMEDOUT; + udelay(1); + } + } uart1_toggle_clock(); + return 0; +} + +int uart1_clock_config(struct ipq_serial_platdata *plat) +{ + + uart1_configure_mux(); + uart1_set_rate_mnd(plat->m_value, + plat->n_value, + plat->d_value); + return uart1_trigger_update(); } void qca_serial_init(struct ipq_serial_platdata *plat) { - int node, uart1_node; + int ret; - writel(1, GCC_BLSP1_UART1_APPS_CBCR); - node = fdt_path_offset(gd->fdt_blob, "/serial@78AF000/serial_gpio"); - if (node < 0) { - printf("Could not find serial_gpio node\n"); + if (plat->gpio_node < 0) { + printf("serial_init: unable to find gpio node \n"); return; } - - if (plat->port_id == 1) { - uart1_node = fdt_path_offset(gd->fdt_blob, "uart1"); - if (uart1_node < 0) { - printf("Could not find uart1 node\n"); - return; - } - node = fdt_subnode_offset(gd->fdt_blob, - uart1_node, "serial_gpio"); - uart1_clock_config(plat->m_value, plat->n_value, plat->d_value); - writel(1, GCC_BLSP1_UART1_APPS_CBCR); - } - - qca_gpio_init(node); + qca_gpio_init(plat->gpio_node); + ret = uart1_clock_config(plat); + if (ret) + printf("UART clock config failed %d \n", ret); } /* diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index a617dfa551..dc2cdc122a 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -74,11 +74,12 @@ #define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8 #define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0 -#define UART1_RCGR_SRC_SEL 0x1 -#define UART1_RCGR_SRC_DIV 0x0 -#define UART1_RCGR_MODE 0x2 -#define UART1_CMD_RCGR_UPDATE 0x1 -#define UART1_CBCR_CLK_ENABLE 0x1 +#define UART1_RCGR_SRC_SEL 0x1 +#define UART1_RCGR_SRC_DIV 0x0 +#define UART1_RCGR_MODE 0x2 +#define UART1_CMD_RCGR_UPDATE 0x1 +#define UART1_CMD_RCGR_ROOT_EN 0x2 +#define UART1_CBCR_CLK_ENABLE 0x1 /* USB Registers */ #define GCC_SYS_NOC_USB0_AXI_CBCR 0x1826040