mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2025-12-10 07:44:53 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

ipq807x: Add PCIE support for IPQ807x

Browse source 
Change-Id: Iba6db5caf405b4fe4f1668dc6462504e41d5d219
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan 2016-09-22 14:32:02 +05:30 • committed by Gerrit - the friendly Code Review server
parent dbc99acc0c
commit ef5b429ab2
6 changed files with 107 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

36
arch/arm/dts/ipq807x-hk01.dts
View file

@ -13,6 +13,7 @@
/dts-v1/;
#include "ipq807x-hk01.dtsi"
#include <dt-bindings/qcom/gpio-ipq807x.h>
/ {
model ="QCA, IPQ807x-HK01";
compatible = "qca,ipq807x", "qca,ipq807x-hk01";
@ -24,6 +25,41 @@
xhci0 = "/xhci@8a00000";
xhci1 = "/xhci@8c00000";
i2c0 = "/i2c@78b6000";
pci0 = "/pci@20000000";
pci1 = "/pci@10000000";
};
pci@20000000 {
pci_gpio {
gpio1 {
gpio = <58>;
func = <0>;
out = <GPIO_OUT_HIGH>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
};
};
pci@10000000 {
pci_gpio {
gpio1 {
gpio = <61>;
func = <0>;
out = <GPIO_OUT_HIGH>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_ENABLE>;
vm = <GPIO_VM_ENABLE>;
od_en = <GPIO_OD_DISABLE>;
pu_res = <GPIO_PULL_RES2>;
};
};
};
};

30
arch/arm/dts/ipq807x-hk01.dtsi
View file

@ -59,4 +59,34 @@
#size-cells = <0>;
reg = <0x78b6000 0x600>;
};
pci@20000000 {
compatible = "qcom,ipq807x-pcie";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x20000000 0xf1d
0x80000 0x2000
0x20000f20 0xa8
0x20300000 0xd00000
0x20100000 0x100000
0x01875004 0x40>;
reg-names = "pci_dbi", "parf", "elbi", "axi_bars",
"axi_conf", "pci_rst";
perst_gpio = <58>;
};
pci@10000000 {
compatible = "qcom,ipq807x-pcie";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10000000 0xf1d
0x88000 0x2000
0x10000f20 0xa8
0x10300000 0xd00000
0x10100000 0x100000
0x1876004 0x40>;
reg-names = "pci_dbi", "parf", "elbi", "axi_bars",
"axi_conf", "pci_rst";
perst_gpio = <61>;
};
};

19
board/qca/ipq807x/ipq807x.c
View file

@ -17,6 +17,7 @@
#include <environment.h>
#include <asm/arch-qcom-common/qca_common.h>
#include <asm/arch-qcom-common/qpic_nand.h>
#include <asm/arch-qcom-common/gpio.h>
#include <asm/arch-qcom-common/uart.h>
#include <fdtdec.h>
@ -138,3 +139,21 @@ void board_nand_init(void)
qpic_nand_init(&config);
}
void board_pci_init(int id)
{
int node, gpio_node;
char name[16];
sprintf(name, "pci%d", id);
node = fdt_path_offset(gd->fdt_blob, name);
if (node < 0) {
printf("Could not find PCI in device tree\n");
return;
}
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
if (gpio_node >= 0)
qca_gpio_init(gpio_node);
return ;
}

1
board/qca/ipq807x/ipq807x.h
View file

@ -55,5 +55,6 @@ extern const char *del_node[];
extern const add_node_t add_node[];
void reset_crashdump(void);
void board_pci_init(int id);
#endif /* _IPQ807X_H_ */

7
include/configs/ipq807x.h
View file

@ -215,6 +215,13 @@ extern loff_t board_env_offset;
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#define CONFIG_PCI_IPQ
#define PCI_MAX_DEVICES 2
#ifdef CONFIG_PCI_IPQ
#define CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
* Cache flush and invalidation based on L1 cache, so the cache line
* size is configured to 64 */

14
include/dt-bindings/qcom/gpio-ipq807x.h
View file

@ -59,4 +59,18 @@
#define GPIO_OE_DISABLE 0
#define GPIO_OE_ENABLE 1
/* GPIO VM */
#define GPIO_VM_ENABLE 1
#define GPIO_VM_DISABLE 0
/* GPIO OD */
#define GPIO_OD_ENABLE 1
#define GPIO_OD_DISABLE 0
/* GPIO PULLUP RES */
#define GPIO_PULL_RES0 0
#define GPIO_PULL_RES1 1
#define GPIO_PULL_RES2 2
#define GPIO_PULL_RES3 3
#endif