From f0af526b777b1412f281b0bbee708361b0c6c5ce Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Fri, 18 Sep 2020 21:52:10 +0530 Subject: [PATCH 01/37] driver: nand: qpic_nand: Add support for winbond device Signed-off-by: Md Sadre Alam Change-Id: I19c0d6b285d4b054d9700f58a88395cd0ffe3896 --- .../include/asm/arch-qca-common/qpic_nand.h | 1 + drivers/mtd/nand/qpic_nand.c | 52 ++++++++++++++++--- 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-qca-common/qpic_nand.h b/arch/arm/include/asm/arch-qca-common/qpic_nand.h index 72e97d433b..5a5c7b2d7b 100644 --- a/arch/arm/include/asm/arch-qca-common/qpic_nand.h +++ b/arch/arm/include/asm/arch-qca-common/qpic_nand.h @@ -281,6 +281,7 @@ */ #define FLASH_SPI_NAND_FR_ADDR 0xB0 #define FLASH_SPI_NAND_FR_ECC_ENABLE (1 << 4) +#define FLASH_SPI_NAND_FR_BUFF_ENABLE (1 << 3) #define FLASH_SPI_NAND_FR_QUAD_ENABLE 0x1 /* According to GigaDevice data sheet Status Register(0xC0) is: * _________________________________________________ diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 677a267d82..6adbd7e658 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -114,9 +114,26 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = false, .name = "MT29F1G01ABBFDWB-IT", }, + { + .id = { 0xef, 0xbc }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 1024, + .spare_size = 64, + .density = 0x08000000, + .otp_region = 0x5000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "W25N01JW", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c +#define WINBOND_DEVICE_ID 0x0021bcef #define CMD3_MASK 0xfff0ffff /* * An array holding the fixed pattern to compare with @@ -1257,14 +1274,14 @@ int qpic_spi_nand_config(struct mtd_info *mtd) qspi_debug("%s : Quad bit not enabled.\n",__func__); qspi_debug("%s : Issuning set feature command to enable it.\n", __func__); - /* Enable quad bit */ status = qpic_serial_set_feature(mtd, FLASH_SPI_NAND_FR_ADDR, FLASH_SPI_NAND_FR_QUAD_ENABLE); if (status < 0) { - printf("%s : Error in enabling Quad bit.\n",__func__); - return status; + printf("%s : Error in enabling Quad bit.\n",__func__); + return status; } + /* Read status again to know wether Quad bit enabled or not */ status = qpic_serial_get_feature(mtd, FLASH_SPI_NAND_FR_ADDR); if (status < 0) { @@ -1276,16 +1293,39 @@ int qpic_spi_nand_config(struct mtd_info *mtd) qspi_debug("%s:Quad mode not enabled,so use x1 Mode.\n", __func__); dev->quad_mode = false; - return 0; } else { qspi_debug("%s: Quad mode enabled. using X4 mode\n",__func__); - return 0; } } else { qspi_debug("%s: Quad mode enabled on Opwer on.\n",__func__); - return 0; } } + + if (dev->id == WINBOND_DEVICE_ID) { + status = qpic_serial_get_feature(mtd, FLASH_SPI_NAND_FR_ADDR); + if (status < 0) { + printf("%s : Error in getting feature.\n",__func__); + return status; + } + + if (!((status >> 8) & FLASH_SPI_NAND_FR_BUFF_ENABLE)) { + qspi_debug("%s :continous buffer mode disabled\n", + __func__); + qspi_debug("%s : Issuing set feature command to enable it\n", + __func__); + status = qpic_serial_set_feature(mtd, FLASH_SPI_NAND_FR_ADDR, + (FLASH_SPI_NAND_FR_BUFF_ENABLE | (status >> 8))); + if (status < 0) { + printf("%s : Error in disabling continous buffer bit.\n", + __func__); + return status; + } + } else { + qspi_debug("%s : continous buffer mode enabled on power on\n", + __func__); + } + } + return 0; } #endif From a08592083b2b39659bb33273893a693f03ca3961 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Thu, 24 Dec 2020 16:27:31 +0530 Subject: [PATCH 02/37] ipq50xx: net: Update UNIPHY_MISC register address This changes enable proper uniphy soft reset for mode setting. Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: Iebafa56ec4aecee98ba2f124d6140ee15083d317 --- drivers/net/ipq5018/ipq5018_uniphy.c | 11 ++++++++++- drivers/net/ipq5018/ipq5018_uniphy.h | 3 ++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipq5018/ipq5018_uniphy.c b/drivers/net/ipq5018/ipq5018_uniphy.c index d3edde505d..7daeec098e 100644 --- a/drivers/net/ipq5018/ipq5018_uniphy.c +++ b/drivers/net/ipq5018/ipq5018_uniphy.c @@ -22,6 +22,8 @@ #include "ipq5018_uniphy.h" #include "ipq_phy.h" +static uint32_t cur_mode; + static int ppe_uniphy_calibration(void) { int retries = 100, calibration_done = 0; @@ -59,6 +61,7 @@ static void ppe_gcc_uniphy_soft_reset(void) static void ppe_uniphy_sgmii_mode_set(uint32_t mode) { + uint32_t phy_mode = 0x70; writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE + UNIPHY_MISC2_REG_OFFSET); @@ -93,14 +96,20 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t mode) case PORT_WRAPPER_SGMII_PLUS: writel((UNIPHY_SG_PLUS_MODE | UNIPHY_PSGMII_MAC_MODE), PPE_UNIPHY_BASE + PPE_UNIPHY_MODE_CONTROL); + phy_mode = 0x30; break; default: printf("SGMII Config. wrongly"); break; } + if ((cur_mode == PORT_WRAPPER_SGMII_PLUS) || + (mode == PORT_WRAPPER_SGMII_PLUS)){ + cur_mode = mode; + ppe_gcc_uniphy_soft_reset(); + } - ppe_gcc_uniphy_soft_reset(); + writel(phy_mode, PPE_UNIPHY_BASE + PPE_UNIPHY_ALLREG_DEC_MISC2); writel(0x1, GCC_UNIPHY_RX_CBCR); udelay(500); diff --git a/drivers/net/ipq5018/ipq5018_uniphy.h b/drivers/net/ipq5018/ipq5018_uniphy.h index 3b606636b0..da08281c29 100644 --- a/drivers/net/ipq5018/ipq5018_uniphy.h +++ b/drivers/net/ipq5018/ipq5018_uniphy.h @@ -23,7 +23,7 @@ #define GCC_GMAC1_RX_CBCR 0x01868248 #define GCC_GMAC1_TX_CBCR 0x0186824C -#define GCC_UNIPHY0_MISC 0x01856004 +#define GCC_UNIPHY0_MISC 0x01856104 #define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0 #define UNIPHY_CALIBRATION_DONE 0x1 @@ -33,6 +33,7 @@ #define PPE_UNIPHY_BASE 0x00098000 #define PPE_UNIPHY_MODE_CONTROL 0x46C +#define PPE_UNIPHY_ALLREG_DEC_MISC2 0x218 #define UNIPHY_XPCS_MODE (1 << 12) #define UNIPHY_SG_PLUS_MODE (1 << 11) #define UNIPHY_SG_MODE (1 << 10) From ddd63fb99d19f52fa5478886358814673b935223 Mon Sep 17 00:00:00 2001 From: Pavithra Palanisamy Date: Tue, 29 Dec 2020 13:59:18 +0530 Subject: [PATCH 03/37] pack: Update section name for WIFIFW This change is to update the section name for wififw in single-image with the QCN IDs when multiple wififw images get packed. Signed-off-by: Pavithra Palanisamy Change-Id: I56ab611a127b9958c38737684d856c51fabf7cd2 --- tools/pack.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tools/pack.py b/tools/pack.py index ceed58342c..96cb715b6f 100644 --- a/tools/pack.py +++ b/tools/pack.py @@ -758,8 +758,8 @@ class Pack(object): machid_list.append(machid) script.start_if_or("machid", machid_list) - script.start_activity("Flashing wifi_fw volume:") - script.imxtract("wifi_fw_" + wifi_fw_type + "-" + sha1(fw_filename)) + script.start_activity("Flashing " + fw_filename[:-13] + ":") + script.imxtract(fw_filename[:-13] + "-" + sha1(fw_filename)) script.append('flash wifi_fw', fatal=False) script.finish_activity() @@ -837,14 +837,14 @@ class Pack(object): return 1 script.start_if_or("machid", machid_list) - script.start_activity("Flashing %s_%s:" % ( section_conf, wifi_fw_type )) + script.start_activity("Flashing %s:" % ( filename[:-13] )) if img_size > 0: filename_pad = filename + ".padded" if ((self.flinfo.type == 'nand' or self.flinfo.type == 'emmc') and (size != img_size)): - script.imxtract(section_conf + "_" + wifi_fw_type + "-" + sha1(filename_pad)) + script.imxtract(filename[:-13] + "-" + sha1(filename_pad)) else: - script.imxtract(section_conf + "_" + wifi_fw_type + "-" + sha1(filename)) + script.imxtract(filename[:-13] + "-" + sha1(filename)) part_size = Pack.norplusnand_rootfs_img_size if part_info == None: @@ -1551,7 +1551,7 @@ class Pack(object): elif section_conf == "wififw" and self.flash_type in ["nand", "nand-4k", "nand-audio", "nand-audio-4k", "norplusnand", "norplusnand-4k"]: section_conf = "wififw_ubi" elif section_conf == "wififw" and wifi_fw_type: - section_conf = section_conf + "_" + wifi_fw_type + section_conf = filename[:-13] if soc_version: section_conf = section_conf + "_v" + str(soc_version) @@ -1564,7 +1564,7 @@ class Pack(object): def __gen_script_append_images_wififw_ubi_volume(self, fw_filename, wifi_fw_type, images): - image_info = ImageInfo("wifi_fw_" + wifi_fw_type + "-" + sha1(fw_filename), + image_info = ImageInfo(fw_filename[:-13] + "-" + sha1(fw_filename), fw_filename, "firmware") if fw_filename.lower() != "none": if image_info not in images: From c8abb253308fe9b5129b154114e06c287a6bc564 Mon Sep 17 00:00:00 2001 From: Pavithra Palanisamy Date: Wed, 16 Dec 2020 20:09:59 +0530 Subject: [PATCH 04/37] pack: Modify QCN9100 to QCN6122 for Spruce Signed-off-by: Pavithra Palanisamy Change-Id: Id39e432528603778d125ba69638b26bb7e74f41e --- tools/pack.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/tools/pack.py b/tools/pack.py index 96cb715b6f..00c179845d 100644 --- a/tools/pack.py +++ b/tools/pack.py @@ -89,7 +89,7 @@ memory_size = "default" lk = "false" skip_4k_nand = "false" atf = "false" -qcn9100 = "false" +qcn6122 = "false" tiny_16m = "false" # Note: ipq806x didn't expose any relevant version */ @@ -1247,7 +1247,7 @@ class Pack(object): try: diff_soc_ver_files = section.attrib['diff_soc_ver_files'] except KeyError, e: - if (qcn9100 == "true" or tiny_16m == "true") and 'wififw_type_min' in section.attrib: + if (qcn6122 == "true" or tiny_16m == "true") and 'wififw_type_min' in section.attrib: wifi_fw_type_min = section.attrib['wififw_type_min'] wifi_fw_type_max = section.attrib['wififw_type_max'] else: @@ -1313,7 +1313,7 @@ class Pack(object): if flinfo.type != "emmc": img = section.find('img_name') - if img != None and 'wififw_type' in img.attrib and (qcn9100 == "true" or tiny_16m == "true"): + if img != None and 'wififw_type' in img.attrib and (qcn6122 == "true" or tiny_16m == "true"): imgs = section.findall('img_name') try: for img in imgs: @@ -1410,7 +1410,7 @@ class Pack(object): if ret == 0: return 0 - if self.flash_type in [ "nand", "nand-4k", "norplusnand", "norplusnand-4k" ] and partition == "rootfs" and qcn9100 == "true": + if self.flash_type in [ "nand", "nand-4k", "norplusnand", "norplusnand-4k" ] and partition == "rootfs" and qcn6122 == "true": fw_imgs = section.findall('img_name') for fw_img in fw_imgs: @@ -1689,7 +1689,7 @@ class Pack(object): diff_soc_ver_files = section.attrib['diff_soc_ver_files'] partition = section.attrib['label'] except KeyError, e: - if (qcn9100 == "true" or tiny_16m == "true") and 'wififw_type_min' in section.attrib: + if (qcn6122 == "true" or tiny_16m == "true") and 'wififw_type_min' in section.attrib: wifi_fw_type_min = section.attrib['wififw_type_min'] wifi_fw_type_max = section.attrib['wififw_type_max'] partition = section.attrib['label'] @@ -1755,7 +1755,7 @@ class Pack(object): img = section.find('img_name') - if img != None and 'wififw_type' in img.attrib and (qcn9100 == "true" or tiny_16m == "true"): + if img != None and 'wififw_type' in img.attrib and (qcn6122 == "true" or tiny_16m == "true"): imgs = section.findall('img_name') try: for img in imgs: @@ -1860,7 +1860,7 @@ class Pack(object): if filename != "": self.__gen_script_append_images(filename, soc_version, wifi_fw_type, images, flinfo, root, section_conf, partition) - if self.flash_type in [ "nand", "nand-4k", "norplusnand", "norplusnand-4k" ] and section_conf == "rootfs" and qcn9100 == "true": + if self.flash_type in [ "nand", "nand-4k", "norplusnand", "norplusnand-4k" ] and section_conf == "rootfs" and qcn6122 == "true": fw_imgs = section.findall('img_name') try: @@ -2210,7 +2210,7 @@ class ArgParser(object): global lk global atf global skip_4k_nand - global qcn9100 + global qcn6122 """Start the parsing process, and populate members with parsed value. @@ -2220,7 +2220,7 @@ class ArgParser(object): cdir = os.path.abspath(os.path.dirname("")) if len(sys.argv) > 1: try: - opts, args = getopt(sys.argv[1:], "", ["arch=", "fltype=", "srcPath=", "inImage=", "outImage=", "image_type=", "memory=", "lk", "skip_4k_nand", "atf", "qcn9100"]) + opts, args = getopt(sys.argv[1:], "", ["arch=", "fltype=", "srcPath=", "inImage=", "outImage=", "image_type=", "memory=", "lk", "skip_4k_nand", "atf", "qcn6122"]) except GetoptError, e: raise UsageError(e.msg) @@ -2255,8 +2255,8 @@ class ArgParser(object): elif option =="--skip_4k_nand": skip_4k_nand = "true" - elif option == "--qcn9100": - qcn9100 = "true" + elif option == "--qcn6122": + qcn6122 = "true" #Verify Arguments passed by user From ac3c252cf1385c493fb00afd8ba3f9f43c5bbce2 Mon Sep 17 00:00:00 2001 From: Selvam Sathappan Periakaruppan Date: Wed, 30 Dec 2020 16:09:56 +0530 Subject: [PATCH 05/37] qca: Move the function set_platform_specific_default_env This patch moves the set_platform_specific_default_env function outside of CONFIG_QCA_MMC as this function is not dependent on that config. This will cause unexpected behaviour if suppose MMC config is disabled. Signed-off-by: Selvam Sathappan Periakaruppan Change-Id: I9bfc35afb054103bfb60b837cff04eed1d94decd --- board/qca/arm/common/env.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/qca/arm/common/env.c b/board/qca/arm/common/env.c index 4f6b7e6bd7..5fab9a55f2 100644 --- a/board/qca/arm/common/env.c +++ b/board/qca/arm/common/env.c @@ -128,6 +128,7 @@ int board_mmc_env_init(qca_mmc mmc_host) } return ret; } +#endif void set_platform_specific_default_env(void) { @@ -152,4 +153,3 @@ void set_platform_specific_default_env(void) setenv_ulong("soc_version_minor", (unsigned long)soc_ver_minor); } } -#endif From e0b48e556a0284e2f48ad0635d2b629eb135fba1 Mon Sep 17 00:00:00 2001 From: Rajkumar Ayyasamy Date: Fri, 18 Dec 2020 20:25:45 +0530 Subject: [PATCH 06/37] ipq5018: increase bt wait timeout Signed-off-by: Rajkumar Ayyasamy Change-Id: I0255e7814d13b6cbe46ba6b167a9930e9c6f61e5 --- board/qca/arm/ipq5018/ipq5018.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index 5f7ba7227f..b6e5c0f86e 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -640,7 +640,7 @@ typedef enum { BT_WAIT_FOR_STOP = 2, } bt_wait; -#define BT_TIMEOUT_US 50000 +#define BT_TIMEOUT_US 500000 int bt_init(void); #endif From 489d892a2fdf51814329542277e5c022fa7a00ee Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Wed, 7 Oct 2020 14:29:47 +0530 Subject: [PATCH 07/37] configs: ipq5018:Enable PRIVATE LIBGCC Signed-off-by: Karthick Shanmugham Change-Id: I2bab00e94787331e3f0060cf0d3641ee01e110c1 --- configs/ipq5018_defconfig | 2 +- configs/ipq5018_tiny_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/ipq5018_defconfig b/configs/ipq5018_defconfig index 3b794cf72b..b10406f814 100644 --- a/configs/ipq5018_defconfig +++ b/configs/ipq5018_defconfig @@ -307,7 +307,7 @@ CONFIG_USB_XHCI_IPQ=y # # CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set CONFIG_HAVE_PRIVATE_LIBGCC=y -# CONFIG_USE_PRIVATE_LIBGCC is not set +CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_HZ=1000 # CONFIG_SYS_VSNPRINTF is not set CONFIG_REGEX=y diff --git a/configs/ipq5018_tiny_defconfig b/configs/ipq5018_tiny_defconfig index e9907530a8..40cf113167 100644 --- a/configs/ipq5018_tiny_defconfig +++ b/configs/ipq5018_tiny_defconfig @@ -306,7 +306,7 @@ CONFIG_QCA8033_PHY=y # # CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set CONFIG_HAVE_PRIVATE_LIBGCC=y -# CONFIG_USE_PRIVATE_LIBGCC is not set +CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_HZ=1000 # CONFIG_SYS_VSNPRINTF is not set CONFIG_REGEX=y From b6d6a4aa725064af0ac9a89a0f30ee444825d1eb Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Wed, 7 Oct 2020 12:56:47 +0530 Subject: [PATCH 08/37] ipq5018: block_drvr const declared only on HAVE_BLOCK_DEVICE 1. Modified to the declare block_drvr struct and const variable only on HAVE_BLOCK_DEVICE config enabled. 2. Removed unused const training_block_128 Signed-off-by: Karthick Shanmugham Change-Id: Icfe05aec82a124429443aadf735767366b168d6b --- disk/part.c | 6 +++--- drivers/mtd/nand/qpic_nand.c | 11 ----------- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/disk/part.c b/disk/part.c index 909712e501..7fe2e7db5a 100644 --- a/disk/part.c +++ b/disk/part.c @@ -20,6 +20,9 @@ #define PRINTF(fmt,args...) #endif +DECLARE_GLOBAL_DATA_PTR; + +#ifdef HAVE_BLOCK_DEVICE struct block_drvr { char *name; block_dev_desc_t* (*get_dev)(int dev); @@ -55,9 +58,6 @@ static const struct block_drvr block_drvr[] = { { }, }; -DECLARE_GLOBAL_DATA_PTR; - -#ifdef HAVE_BLOCK_DEVICE static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) { const struct block_drvr *drvr = block_drvr; diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 91fc2f06b6..ed5c23e837 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -128,17 +128,6 @@ static const unsigned int training_block_64[] = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, }; - -static const unsigned int training_block_128[] = { - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, - 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, -}; #define TRAINING_PART_OFFSET 0x3c00000 #define MAXIMUM_ALLOCATED_TRAINING_BLOCK 4 #define TOTAL_NUM_PHASE 7 From 7767cd056ebbf798fb2509a70b03afc8c0a22d86 Mon Sep 17 00:00:00 2001 From: Sivaprakash Murugesan Date: Tue, 18 Aug 2020 09:01:05 +0530 Subject: [PATCH 09/37] net: Use packed structures for networking With latest GCC 4 byte aligned instructions are getting generated for 2 byte aligned data. This is due to the option '-fstore-merging' enabled by default for '-O2' This is causing data abort if data cache is disabled. Signed-off-by: Sivaprakash Murugesan Change-Id: Idaac94fcc8e5c61f0ea720ed0c10e908d3688c61 --- include/net.h | 14 +++++++------- net/bootp.h | 2 +- net/dns.h | 2 +- net/nfs.h | 2 +- net/sntp.h | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/net.h b/include/net.h index f7039e3acc..b1a9bc22c3 100644 --- a/include/net.h +++ b/include/net.h @@ -278,7 +278,7 @@ struct ethernet_hdr { u8 et_dest[6]; /* Destination node */ u8 et_src[6]; /* Source node */ u16 et_protlen; /* Protocol or length */ -}; +} __attribute__((packed)); /* Ethernet header size */ #define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr)) @@ -296,7 +296,7 @@ struct e802_hdr { u8 et_snap2; u8 et_snap3; u16 et_prot; /* 802 protocol */ -}; +} __attribute__((packed)); /* 802 + SNAP + ethernet header size */ #define E802_HDR_SIZE (sizeof(struct e802_hdr)) @@ -310,7 +310,7 @@ struct vlan_ethernet_hdr { u16 vet_vlan_type; /* PROT_VLAN */ u16 vet_tag; /* TAG of VLAN */ u16 vet_type; /* protocol type */ -}; +} __attribute__((packed)); /* VLAN Ethernet header size */ #define VLAN_ETHER_HDR_SIZE (sizeof(struct vlan_ethernet_hdr)) @@ -337,7 +337,7 @@ struct ip_hdr { u16 ip_sum; /* checksum */ struct in_addr ip_src; /* Source IP address */ struct in_addr ip_dst; /* Destination IP address */ -}; +} __attribute__((packed)); #define IP_OFFS 0x1fff /* ip offset *= 8 */ #define IP_FLAGS 0xe000 /* first 3 bits */ @@ -365,7 +365,7 @@ struct ip_udp_hdr { u16 udp_dst; /* UDP destination port */ u16 udp_len; /* Length of UDP packet */ u16 udp_xsum; /* Checksum */ -}; +} __attribute__((packed)); #define IP_UDP_HDR_SIZE (sizeof(struct ip_udp_hdr)) #define UDP_HDR_SIZE (IP_UDP_HDR_SIZE - IP_HDR_SIZE) @@ -404,7 +404,7 @@ struct arp_hdr { u8 ar_tha[]; /* Target hardware address */ u8 ar_tpa[]; /* Target protocol address */ #endif /* 0 */ -}; +} __attribute__((packed)); #define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */ @@ -439,7 +439,7 @@ struct icmp_hdr { } frag; u8 data[0]; } un; -}; +} __attribute__((packed)); #define ICMP_HDR_SIZE (sizeof(struct icmp_hdr)) #define IP_ICMP_HDR_SIZE (IP_HDR_SIZE + ICMP_HDR_SIZE) diff --git a/net/bootp.h b/net/bootp.h index fcb0a64e61..567340ec5d 100644 --- a/net/bootp.h +++ b/net/bootp.h @@ -49,7 +49,7 @@ struct bootp_hdr { char bp_sname[64]; /* Server host name */ char bp_file[128]; /* Boot file name */ char bp_vend[OPT_FIELD_SIZE]; /* Vendor information */ -}; +} __attribute__((packed)); #define BOOTP_HDR_SIZE sizeof(struct bootp_hdr) diff --git a/net/dns.h b/net/dns.h index c4e96afa06..c55a5c1b04 100644 --- a/net/dns.h +++ b/net/dns.h @@ -29,7 +29,7 @@ struct header { uint16_t nauth; /* Authority PRs */ uint16_t nother; /* Other PRs */ unsigned char data[1]; /* Data, variable length */ -}; +} __attribute__((packed)); void dns_start(void); /* Begin DNS */ diff --git a/net/nfs.h b/net/nfs.h index d69b422f52..09b387e4c9 100644 --- a/net/nfs.h +++ b/net/nfs.h @@ -68,7 +68,7 @@ struct rpc_t { uint32_t data[19]; } reply; } u; -}; +} __attribute__((packed)); void nfs_start(void); /* Begin NFS */ diff --git a/net/sntp.h b/net/sntp.h index 6a9c6bb82f..c38bceed3f 100644 --- a/net/sntp.h +++ b/net/sntp.h @@ -51,7 +51,7 @@ struct sntp_pkt_t { unsigned long long originate_timestamp; unsigned long long receive_timestamp; unsigned long long transmit_timestamp; -}; +} __attribute__((packed)); void sntp_start(void); /* Begin SNTP */ From 53e68f335e05260651aa4315ca17385087d98c02 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 11 Jan 2021 16:26:33 +0530 Subject: [PATCH 10/37] ipq5018: Enable usb power gpio output Gpio out need to be enabled for re-spin boards. Signed-off-by: Manikanta Mylavarapu Change-Id: I711ed313170fb6268d1d5b9d70f2966bae481241 --- arch/arm/dts/ipq5018-mp03.1.dts | 1 + arch/arm/dts/ipq5018-mp03.3.dts | 1 + arch/arm/dts/ipq5018-mp03.5-c1.dts | 1 + arch/arm/dts/ipq5018-mp03.6-c1.dts | 1 + board/qca/arm/ipq5018/ipq5018.c | 9 +++++++-- 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/ipq5018-mp03.1.dts b/arch/arm/dts/ipq5018-mp03.1.dts index b729946822..fe9d12e33b 100644 --- a/arch/arm/dts/ipq5018-mp03.1.dts +++ b/arch/arm/dts/ipq5018-mp03.1.dts @@ -113,6 +113,7 @@ usb0: xhci@8a00000 { ssphy = <1>; + usb_pwr_gpio = <24>; usb_gpio { pwr_gpio { gpio = <24>; diff --git a/arch/arm/dts/ipq5018-mp03.3.dts b/arch/arm/dts/ipq5018-mp03.3.dts index 4eebff1458..5badea7cdb 100644 --- a/arch/arm/dts/ipq5018-mp03.3.dts +++ b/arch/arm/dts/ipq5018-mp03.3.dts @@ -127,6 +127,7 @@ }; usb0: xhci@8a00000 { + usb_pwr_gpio = <24>; usb_gpio { pwr_gpio { gpio = <24>; diff --git a/arch/arm/dts/ipq5018-mp03.5-c1.dts b/arch/arm/dts/ipq5018-mp03.5-c1.dts index 2405f95c1f..45ee452d1a 100644 --- a/arch/arm/dts/ipq5018-mp03.5-c1.dts +++ b/arch/arm/dts/ipq5018-mp03.5-c1.dts @@ -127,6 +127,7 @@ }; usb0: xhci@8a00000 { + usb_pwr_gpio = <24>; usb_gpio { pwr_gpio { gpio = <24>; diff --git a/arch/arm/dts/ipq5018-mp03.6-c1.dts b/arch/arm/dts/ipq5018-mp03.6-c1.dts index 80222b8b5e..ad7aba6e92 100644 --- a/arch/arm/dts/ipq5018-mp03.6-c1.dts +++ b/arch/arm/dts/ipq5018-mp03.6-c1.dts @@ -127,6 +127,7 @@ }; usb0: xhci@8a00000 { + usb_pwr_gpio = <24>; usb_gpio { pwr_gpio { gpio = <24>; diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index 4d661d19da..db16be1e50 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -1343,7 +1343,9 @@ void board_usb_deinit(int id) gpio_node, "gpio", 0); unsigned int *gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + int usb_pwr_gpio = fdtdec_get_int(gd->fdt_blob, nodeoff, "usb_pwr_gpio", 0); writel(0xC1, gpio_base); + gpio_set_value(usb_pwr_gpio, GPIO_OUT_LOW); } } @@ -1497,7 +1499,7 @@ static void usb_init_phy(int index, int ssphy) int ipq_board_usb_init(void) { - int i, nodeoff, ssphy, gpio_node; + int i, nodeoff, ssphy, gpio_node, usb_pwr_gpio; char node_name[8]; if(readl(EUD_EUD_EN2)) { @@ -1528,8 +1530,11 @@ int ipq_board_usb_init(void) /* USB power GPIO for drive 5V */ gpio_node = fdt_subnode_offset(gd->fdt_blob, nodeoff, "usb_gpio"); - if (gpio_node >= 0) + if (gpio_node >= 0) { qca_gpio_init(gpio_node); + usb_pwr_gpio = fdtdec_get_int(gd->fdt_blob, nodeoff, "usb_pwr_gpio", 0); + gpio_set_value(usb_pwr_gpio, GPIO_OUT_HIGH); + } } return 0; From 680ffebba6ef78ee8bfcaa43bbc1e663e4fcee3e Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Tue, 12 Jan 2021 12:26:21 +0530 Subject: [PATCH 11/37] arm: dts: ipq5018: Update blsp base address for i2c. This change will update blsp base address for i2c in MP03.3rdp. Updated address from 78b6000 to 78b7000. Signed-off-by: Md Sadre Alam Change-Id: Idd37550ac4cf012db0dfea16539d5c0948b13f40 --- arch/arm/dts/ipq5018-mp03.3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/ipq5018-mp03.3.dts b/arch/arm/dts/ipq5018-mp03.3.dts index 4eebff1458..d36f1a354a 100644 --- a/arch/arm/dts/ipq5018-mp03.3.dts +++ b/arch/arm/dts/ipq5018-mp03.3.dts @@ -22,7 +22,7 @@ aliases { console = "/serial@78AF000"; mmc = "/sdhci@7804000"; - i2c0 = "/i2c@78b6000"; + i2c0 = "/i2c@78b7000"; gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; pci0 = "/pci@80000000"; From 460937810933707e9ddcbcb6ea2b061787fa85c3 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Mon, 14 Dec 2020 22:23:44 +0530 Subject: [PATCH 12/37] driver: mtd: qpic_nand: Add support for F50D1G41LB spi-nand Signed-off-by: Md Sadre Alam Change-Id: Ib042ec361ed4a16b93594a37c8daca6c26840ce7 --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index df0fb8eb56..7cfb4e29bd 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -130,6 +130,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "W25N01JW", }, + { + .id = { 0xc8, 0x11 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 1024, + .spare_size = 64, + .density = 0x08000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = false, + .name = "F50D1G41LB(2M)", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 02c55e3fb05dfc022e86275738673a6debe40b4d Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Thu, 14 Jan 2021 00:31:06 +0530 Subject: [PATCH 13/37] driver: nand: qpic_nand: Add support for giga device spi nand This change will add support for giga device GD5F1GQ5REYIG spi nand support. Signed-off-by: Md Sadre Alam Change-Id: I57211ce34543de81216d86653a45519b97cf2fb0 --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 7cfb4e29bd..6d4d9c76de 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -146,6 +146,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = false, .name = "F50D1G41LB(2M)", }, + { + .id = { 0xc8, 0x41 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 2048, + .spare_size = 128, + .density = 0x08000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 8, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "GD5F1GQ5REYIG", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 17fd8d354d29a7e07382690c44ba2c5b1dbcaec8 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Tue, 19 Jan 2021 13:50:03 +0530 Subject: [PATCH 14/37] driver: mtd: nand: qcom_nand: Add support for gigadevice nand GD5F1GQ5REYIH Signed-off-by: Md Sadre Alam Change-Id: I84e9d15792a86185e444936a8fe0e5ebd061be8a --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 6d4d9c76de..bfebdf2bc8 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -162,6 +162,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "GD5F1GQ5REYIG", }, + { + .id = { 0xc8, 0x21 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 1024, + .spare_size = 64, + .density = 0x08000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "GD5F1GQ5REYIH", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 64af2446f8dd934bb1f5f5e4403011f6b5fdba18 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Fri, 22 Jan 2021 19:54:45 +0530 Subject: [PATCH 15/37] driver: nand: qpic_nand: Add support for Winbond spi nand This change will add support for winbond "W25N02JWZEIF" spi nand device. Signed-off-by: Md Sadre Alam Change-Id: I1dd258c3f0f3174d09e74fb7ffd0c26a43e6c24b --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index bfebdf2bc8..13c2528049 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -178,6 +178,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "GD5F1GQ5REYIH", }, + { + .id = { 0xef, 0xbf }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 2048, + .spare_size = 64, + .density = 0x10000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "W25N02JWZEIF", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From b05847a5de54002c8da2ae0eb69dd62b24a0c1ca Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Wed, 27 Jan 2021 17:14:07 +0530 Subject: [PATCH 16/37] drivers: nand: qpic_nand: Add support for Macronix spi nand. This change will add support for Macronix "MX35UF1GE4AC" spi nand Signed-off-by: Md Sadre Alam Change-Id: I66e82e22217d655b44e30baa64f3aefd5a5f2aaa --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 13c2528049..a03fbeb15a 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -194,6 +194,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "W25N02JWZEIF", }, + { + .id = { 0xc2, 0x92 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 1024, + .spare_size = 64, + .density = 0x08000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "MX35UF1GE4AC", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 695eea1bf0143ba508824aa9e0e7af95e73cd31a Mon Sep 17 00:00:00 2001 From: Amandeep Singh Date: Thu, 4 Feb 2021 10:41:39 +0530 Subject: [PATCH 17/37] ipq5018: Add BT state information in dts Add BT state information to patch dts when the BT is started at bootloader. Signed-off-by: Amandeep Singh Change-Id: Ib88150bb6c8469ec6d63578ce5c4ab21511aff60 --- board/qca/arm/common/fdt_fixup.c | 11 +++++++++++ board/qca/arm/ipq5018/bt.h | 1 + board/qca/arm/ipq5018/ipq5018.c | 10 ++++++++++ 3 files changed, 22 insertions(+) diff --git a/board/qca/arm/common/fdt_fixup.c b/board/qca/arm/common/fdt_fixup.c index 9c43f0acfc..4704b43690 100644 --- a/board/qca/arm/common/fdt_fixup.c +++ b/board/qca/arm/common/fdt_fixup.c @@ -866,6 +866,13 @@ __weak void fdt_fixup_art_format(void *blob) return; } +#ifdef CONFIG_IPQ_BT_SUPPORT +__weak void fdt_fixup_bt_running(void *blob) +{ + return; +} +#endif + __weak void fdt_fixup_bt_debug(void *blob) { return; @@ -1052,6 +1059,10 @@ int ft_board_setup(void *blob, bd_t *bd) if (s) { fdt_fixup_bt_debug(blob); } + +#ifdef CONFIG_IPQ_BT_SUPPORT + fdt_fixup_bt_running(blob); +#endif /* || This features fixup compressed_art in || dts if its 16M profile build. diff --git a/board/qca/arm/ipq5018/bt.h b/board/qca/arm/ipq5018/bt.h index 92af9e27e6..bb54444742 100644 --- a/board/qca/arm/ipq5018/bt.h +++ b/board/qca/arm/ipq5018/bt.h @@ -205,4 +205,5 @@ struct ipc_intent { extern int bt_ipc_sendmsg(struct bt_descriptor *btDesc, unsigned char *buf, int len ); extern void bt_ipc_init(struct bt_descriptor *btDesc); extern void bt_ipc_worker(struct bt_descriptor *btDesc); +extern int bt_running; #endif /* _BT_H */ diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index db16be1e50..01b4d44498 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -484,6 +484,8 @@ void fdt_fixup_auto_restart(void *blob) } #ifdef CONFIG_IPQ_BT_SUPPORT +int bt_running; + unsigned char hci_reset[] = {0x01, 0x03, 0x0c, 0x00}; @@ -659,8 +661,16 @@ int bt_init(void) send_bt_hci_cmds(btDesc); + bt_running = 1; return 0; } + +void fdt_fixup_bt_running(void *blob) +{ + if (bt_running) { + parse_fdt_fixup("/soc/bt@7000000%qcom,bt-running%1", blob); + } +} #endif void reset_crashdump(void) From 73966739fb0d4977b02d653e1f8520e3d36ae628 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Tue, 2 Feb 2021 18:11:31 +0530 Subject: [PATCH 18/37] common: sf_command: Add ram region validation Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: I36a48bae392388cfd565c6a351f01247959bb613 --- common/cmd_sf.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 69345dbf07..14fae9cc35 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -19,6 +19,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static struct spi_flash *flash; /* @@ -265,6 +267,7 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) int ret = 1; int dev = 0; loff_t offset, len, maxsize; + unsigned long sram_end = CONFIG_SYS_SDRAM_BASE + gd->ram_size; if (argc < 3) return -1; @@ -283,6 +286,16 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) argv[0], flash->size); return 1; } + /* Validate DDR region address */ + if ((addr < CONFIG_SYS_SDRAM_BASE) || (addr > (sram_end - 1))) { + puts("Invalid RAM address \n"); + return 1; + } + + if ((addr + len) > sram_end) { + puts("No space available\n"); + return 1; + } buf = map_physmem(addr, len, MAP_WRBACK); if (!buf) { From 44cd9ed1c4226447914e74f71d144e940e42d9ee Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 16 Feb 2021 11:01:28 +0530 Subject: [PATCH 19/37] configs: ipq6018: enable LZMA decompressor Now, the linux-5.4 image is LZMA compressed enable the LZMA decompressor support. Signed-off-by: Kathiravan T Change-Id: Ibfc0d1fb6ffc463182f944bea0aa1d76af7d57b5 --- configs/ipq6018_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ipq6018_defconfig b/configs/ipq6018_defconfig index 2581be6aae..8b83a56810 100644 --- a/configs/ipq6018_defconfig +++ b/configs/ipq6018_defconfig @@ -313,5 +313,6 @@ CONFIG_REGEX=y # Compression Support # # CONFIG_LZ4 is not set +CONFIG_LZMA=y # CONFIG_ERRNO_STR is not set # CONFIG_UNIT_TEST is not set From ebcbd6d5f6b2665c3ce0dfa6738e398fa5f9674a Mon Sep 17 00:00:00 2001 From: Gitanjali Krishna Date: Sat, 20 Feb 2021 14:08:54 -0800 Subject: [PATCH 20/37] ipq5018: disable pci0 for ipq5018-mp03.6-c1 dts Signed-off-by: Gitanjali Krishna Change-Id: Ia9982a03265eb0b6e0e633590c6b82134afc537a --- arch/arm/dts/ipq5018-mp03.6-c1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/ipq5018-mp03.6-c1.dts b/arch/arm/dts/ipq5018-mp03.6-c1.dts index ad7aba6e92..03456de139 100644 --- a/arch/arm/dts/ipq5018-mp03.6-c1.dts +++ b/arch/arm/dts/ipq5018-mp03.6-c1.dts @@ -25,7 +25,6 @@ i2c0 = "/i2c@78b6000"; gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; - pci0 = "/pci@80000000"; pci1 = "/pci@a0000000"; nand = "/nand-controller@79B0000"; }; From 688ca8069d92b64d1b4f14311c84cf09985066a0 Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Mon, 8 Feb 2021 16:59:34 +0530 Subject: [PATCH 21/37] ipq6018: Modified the ppe ports to support 2.5G link in PHY3 Signed-off-by: Karthick Shanmugham Change-Id: Iab6a8f81213cdd1013d22597e623cda5be5cd041 --- drivers/net/ipq6018/ipq6018_ppe.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ipq6018/ipq6018_ppe.h b/drivers/net/ipq6018/ipq6018_ppe.h index b7a28770fc..cd8130e39c 100644 --- a/drivers/net/ipq6018/ipq6018_ppe.h +++ b/drivers/net/ipq6018/ipq6018_ppe.h @@ -200,9 +200,9 @@ union ipo_action_u { #define IPQ6018_PPE_PORT_QCOM1 0x1 #define IPQ6018_PPE_PORT_QCOM2 0x2 #define IPQ6018_PPE_PORT_QCOM3 0x3 -#define IPQ6018_PPE_PORT_QCOM4 0x4 -#define IPQ6018_PPE_PORT_XGMAC1 0x5 -#define IPQ6018_PPE_PORT_XGMAC2 0x6 +#define IPQ6018_PPE_PORT_QCOM4 0x6 +#define IPQ6018_PPE_PORT_XGMAC1 0x4 +#define IPQ6018_PPE_PORT_XGMAC2 0x5 #define IPQ6018_PPE_PORT_CRYPTO1 0x7 #define IPQ6018_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000 #define IPQ6018_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000 From 5ddba484f3eaac6fe8f3a1d70243e5c4abc97a18 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Thu, 18 Mar 2021 08:17:08 +0530 Subject: [PATCH 22/37] pack: Remove flash wifi_fw command 'flash wifi_fw' command writes into flash based on 'rootfs' partition offset. After sysupgrade, flashing single image at u-boot write wifi firmware into failsafe partitions because post sysupgarde primary and failsafe partitions are swapped vice-versa. Single image always boots with primary partitions, and the wifi firmware flashed into failsafe partition won't be loaded subsequently q6 will crash. This patch resolves issue by using "ubi" command's instead of "flash wifi_fw" command. Signed-off-by: Manikanta Mylavarapu Change-Id: I9a89872ade5cbd753272e11fd15e7b8f06d4f92c --- tools/pack.py | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tools/pack.py b/tools/pack.py index 00c179845d..b5fbce05ce 100644 --- a/tools/pack.py +++ b/tools/pack.py @@ -760,7 +760,23 @@ class Pack(object): script.start_if_or("machid", machid_list) script.start_activity("Flashing " + fw_filename[:-13] + ":") script.imxtract(fw_filename[:-13] + "-" + sha1(fw_filename)) - script.append('flash wifi_fw', fatal=False) + + rootfs_info = self.__get_part_info("rootfs") + rootfs_offset = rootfs_info.offset + rootfs_len = rootfs_info.length + + wifi_fw_cmd = "setenv mtdids nand0=nand0\n" + wifi_fw_cmd += "setenv mtdparts mtdparts=nand0:0x%x@0x%x(rootfs)\n" % (rootfs_len,rootfs_offset) + wifi_fw_cmd += "ubi part rootfs\n" + img_size = self.__get_img_size(fw_filename) + wifi_fw_cmd += "ubi write $fileaddr wifi_fw %x" % img_size + script.append(wifi_fw_cmd, fatal=False) + + #Enable the below lines for debugging purpose + """ + script.append("mtdparts", fatal=False) + script.append("ubi info layout", fatal=False) + """ script.finish_activity() script.end_if() @@ -1903,7 +1919,7 @@ class Pack(object): its_fp.write(its_data) its_fp.close() - + try: cmd = [SRC_DIR + "/mkimage", "-f", self.its_fname, self.img_fname] ret = subprocess.call(cmd) From bce99ec378b0477023f003e17fd49f65df9a5271 Mon Sep 17 00:00:00 2001 From: Karthick Shanmugham Date: Thu, 18 Mar 2021 12:44:07 +0530 Subject: [PATCH 23/37] ipq: cmd: Disabled the cache commands Disabled the cache commands config CONFIG_CMD_CACHE. This changes removes the icache and dcache commands. Signed-off-by: Karthick Shanmugham Change-Id: I0cfd4df12e452a15861f0df7f4512234113d315a --- include/configs/ipq40xx.h | 1 - include/configs/ipq5018.h | 1 - include/configs/ipq6018.h | 1 - include/configs/ipq806x.h | 1 - include/configs/ipq807x.h | 1 - 5 files changed, 5 deletions(-) diff --git a/include/configs/ipq40xx.h b/include/configs/ipq40xx.h index 3613edfc5b..8882ddf369 100644 --- a/include/configs/ipq40xx.h +++ b/include/configs/ipq40xx.h @@ -182,7 +182,6 @@ typedef struct { * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE #define CONFIG_QCA_BAM 1 /* diff --git a/include/configs/ipq5018.h b/include/configs/ipq5018.h index bece713695..8dc6aeca4f 100644 --- a/include/configs/ipq5018.h +++ b/include/configs/ipq5018.h @@ -329,7 +329,6 @@ extern loff_t board_env_size; #else #define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_CACHE /* Multicore CPU support */ #define CONFIG_SMP_CMD_SUPPORT diff --git a/include/configs/ipq6018.h b/include/configs/ipq6018.h index 835bf85f50..c074e65b23 100644 --- a/include/configs/ipq6018.h +++ b/include/configs/ipq6018.h @@ -348,7 +348,6 @@ extern loff_t board_env_size; * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE /*#define CONFIG_SYS_DCACHE_OFF*/ /* Enabling this flag will report any L2 errors. diff --git a/include/configs/ipq806x.h b/include/configs/ipq806x.h index bce2752193..0b25c2322b 100644 --- a/include/configs/ipq806x.h +++ b/include/configs/ipq806x.h @@ -347,7 +347,6 @@ typedef struct { * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE /*#define CONFIG_SYS_DCACHE_OFF*/ /* Enabling this flag will report any L2 errors. diff --git a/include/configs/ipq807x.h b/include/configs/ipq807x.h index 71869e95b8..97fe5f92d3 100644 --- a/include/configs/ipq807x.h +++ b/include/configs/ipq807x.h @@ -334,7 +334,6 @@ extern loff_t board_env_size; * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE /* Enabling this flag will report any L2 errors. * By default we are disabling it */ From 15aa7bfe5a659e91bd07ffedd0d3fcb67e4c96fa Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Mon, 22 Mar 2021 12:17:38 +0530 Subject: [PATCH 24/37] bootqca: correct misprint log Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: I87b4f3b2aa4af9af41486e8056bd759a1722ba7c --- board/qca/arm/common/cmd_bootqca.c | 2 +- drivers/mtd/nand/qpic_nand.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/qca/arm/common/cmd_bootqca.c b/board/qca/arm/common/cmd_bootqca.c index dae1a1187a..1342f421f1 100644 --- a/board/qca/arm/common/cmd_bootqca.c +++ b/board/qca/arm/common/cmd_bootqca.c @@ -253,7 +253,7 @@ int config_select(unsigned int addr, char *rcmd, int rcmd_size) } - printf("Config not availabale\n"); + printf("Config not available\n"); return -1; } diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index a03fbeb15a..ba0b88458d 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -878,7 +878,7 @@ static void qpic_serial_update_dev_params(struct mtd_info *mtd) mtd->ecc_strength = 8; else mtd->ecc_strength = 4; - printf("Serial NAND device Manufature:%s\n",serial_params->name); + printf("Serial NAND device Manufacturer:%s\n",serial_params->name); printf("Device Size:%d MiB, Page size:%d, Spare Size:%d, ECC:%d-bit\n", (int)(dev->density >> 20), dev->page_size, mtd->oobsize, mtd->ecc_strength); } From 68054def6c692628cf308d8d798e8193e395aba9 Mon Sep 17 00:00:00 2001 From: c_nguruj Date: Tue, 23 Mar 2021 16:22:05 +0530 Subject: [PATCH 25/37] test change to validate profiles in coretech_fig manifest Change-Id: I6d9b5baa30a3bc057958974d18a4d3db724f86d8 Signed-off-by: c_nguruj --- net/dns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/dns.c b/net/dns.c index 7017bac75a..5b9b22d9bd 100644 --- a/net/dns.c +++ b/net/dns.c @@ -8,7 +8,7 @@ * in the DNS response as net_server_ip. This can then be used for any other * network related activities. * - * The packet handling is partly based on TADNS, original copyrights + * The packet handling is partly based on TADNS, original copyrights * follow below. * */ From b524f067dc3eac250c3878b50a1b555fd030986e Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Mon, 29 Mar 2021 17:02:09 +0530 Subject: [PATCH 26/37] arm: dts: add mp03.3-c3 support Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: Id430feb89b3b3cff3b59e5a191c0b342fc59bf65 --- arch/arm/dts/Makefile | 1 + arch/arm/dts/ipq5018-mp03.3-c3.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm/dts/ipq5018-mp03.3-c3.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5d500ddcf..7088b0c6c2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -68,6 +68,7 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-emulation.dtb \ ipq5018-mp03.1-c3.dtb \ ipq5018-mp03.3.dtb \ ipq5018-mp03.3-c2.dtb \ + ipq5018-mp03.3-c3.dtb \ ipq5018-mp03.4-c1.dtb \ ipq5018-mp03.4-c2.dtb \ ipq5018-mp03.6-c1.dtb \ diff --git a/arch/arm/dts/ipq5018-mp03.3-c3.dts b/arch/arm/dts/ipq5018-mp03.3-c3.dts new file mode 100644 index 0000000000..a38d72ec92 --- /dev/null +++ b/arch/arm/dts/ipq5018-mp03.3-c3.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipq5018-mp03.3.dts" +/ { + model ="QCA, IPQ5018-MP03.3-C3"; + compatible = "qca,ipq5018", "qca,ipq5018-mp03.3-c3"; + machid = <0x8040202>; + config_name = "config@mp03.3-c3"; +}; From 5343739b4070bcec2fecd72f758c16adc31a3083 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Tue, 30 Mar 2021 11:45:03 +0530 Subject: [PATCH 27/37] arm: dts: remove pci-x2 and usb from mp03.3-c3 Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: I5d8169368f9dfed4110a2dceecab56606712aa4b --- arch/arm/dts/ipq5018-mp03.3-c3.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/ipq5018-mp03.3-c3.dts b/arch/arm/dts/ipq5018-mp03.3-c3.dts index a38d72ec92..b360a20272 100644 --- a/arch/arm/dts/ipq5018-mp03.3-c3.dts +++ b/arch/arm/dts/ipq5018-mp03.3-c3.dts @@ -16,4 +16,7 @@ compatible = "qca,ipq5018", "qca,ipq5018-mp03.3-c3"; machid = <0x8040202>; config_name = "config@mp03.3-c3"; + + /delete-node/ pci@a0000000; + /delete-node/ xhci@8a00000; }; From eeee0973a17766ea53c3124c9c4e6e0a38b09c2f Mon Sep 17 00:00:00 2001 From: Prasanna Kumar Thoorvas Samyrao Muralidharan Date: Tue, 13 Apr 2021 15:17:13 +0530 Subject: [PATCH 28/37] ipq5018: mp03.5-c1: Fix i2c device address in dts Change-Id: I98484c481db55c78aef89a27bb529f1bd39ca08b Signed-off-by: Prasanna Kumar Thoorvas Samyrao Muralidharan --- arch/arm/dts/ipq5018-mp03.5-c1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/ipq5018-mp03.5-c1.dts b/arch/arm/dts/ipq5018-mp03.5-c1.dts index 45ee452d1a..d6ea0e0649 100644 --- a/arch/arm/dts/ipq5018-mp03.5-c1.dts +++ b/arch/arm/dts/ipq5018-mp03.5-c1.dts @@ -22,7 +22,7 @@ aliases { console = "/serial@78AF000"; mmc = "/sdhci@7804000"; - i2c0 = "/i2c@78b6000"; + i2c0 = "/i2c@78b7000"; gmac_gpio = "/gmac_gpio"; usb0 = "/xhci@8a00000"; pci0 = "/pci@80000000"; From 3f60ccc070ac2ab215dc68a34d52dc44d3065dfa Mon Sep 17 00:00:00 2001 From: sjagadam Date: Tue, 23 Feb 2021 15:11:35 +0530 Subject: [PATCH 29/37] driver: nand: qpic_nand: Add support for ESMT SPI nand device F50D2G41KA-83YIG2V Signed-off-by: sjagadam Change-Id: Ib95578b56f1f8c062b0b16ffe4e936434297fc3d --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index ba0b88458d..d9c1d0275d 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -210,6 +210,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "MX35UF1GE4AC", }, + { + .id = { 0xc8, 0x51 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 2048, + .spare_size = 128, + .density = 0x10000000, + .otp_region = 0xF000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 8, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "F50D2G41KA-83YIG2V", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 235f540e47bdc98d4ecc638547e063879f743773 Mon Sep 17 00:00:00 2001 From: sjagadam Date: Sat, 1 May 2021 10:26:41 +0530 Subject: [PATCH 30/37] driver: nand: qpic_nand: Add support for Dosillicon SPI nand device DS35M1GA Change-Id: I2eee62bcdec0189cb5985d03e394acf8a5970b3d Author: sjagadam --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index d9c1d0275d..040829a1f1 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -226,6 +226,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "F50D2G41KA-83YIG2V", }, + { + .id = { 0xe5, 0x21 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 1024, + .spare_size = 64, + .density = 0x08000000, + .otp_region = 0xF000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "DS35M1GA", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From c0751657f2022b7afd2ba1c7e88aeab09b6a9865 Mon Sep 17 00:00:00 2001 From: sjagadam Date: Sat, 24 Apr 2021 21:44:13 +0530 Subject: [PATCH 31/37] driver: nand: qpic_nand: Add support for Gigadevice 2Gb SPI nand device GD5F2GQ5REYIG Signed-off-by: sjagadam Change-Id: I9a1fa6b7a9990ad5bf372ea330d4bf3782bfce72 Signed-off-by: sjagadam --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index 040829a1f1..a51321dbdd 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -242,6 +242,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "DS35M1GA", }, + { + .id = { 0xc8, 0x42 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 2048, + .spare_size = 128, + .density = 0x10000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 8, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "GD5F2GQ5REYIG", + }, }; struct qpic_serial_nand_params *serial_params; #define MICRON_DEVICE_ID 0x152c152c From 10a29f259a964ccbee1efda488e7a0ea9e2220d0 Mon Sep 17 00:00:00 2001 From: sjagadam Date: Tue, 20 Apr 2021 18:09:41 +0530 Subject: [PATCH 32/37] driver: nand: qpic_nand: Add support for Gigadevice SPI nand device GD5F4GQ6REYIHR Change-Id: I38050d1a23462fa4101cd658a612e646d6a4993d Signed-off-by: sjagadam --- drivers/mtd/nand/qpic_nand.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c index ba0b88458d..0a87028d4b 100644 --- a/drivers/mtd/nand/qpic_nand.c +++ b/drivers/mtd/nand/qpic_nand.c @@ -98,6 +98,22 @@ static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = { .check_quad_config = true, .name = "GD5F2GQ5REYIH", }, + { + .id = { 0xc8, 0x25 }, + .page_size = 2048, + .erase_blk_size = 0x00020000, + .pgs_per_blk = 64, + .no_of_blocks = 4096, + .spare_size = 64, + .density = 0x20000000, + .otp_region = 0x2000, + .no_of_addr_cycle = 0x3, + .num_bits_ecc_correctability = 4, + .timing_mode_support = 0, + .quad_mode = true, + .check_quad_config = true, + .name = "GD5F4GQ6REYIHR", + }, { .id = { 0x2c, 0x15 }, .page_size = 2048, From cae6d364003feecef715ea09e411e31e3dce8698 Mon Sep 17 00:00:00 2001 From: Prasanna Kumar Thoorvas Samyrao Muralidharan Date: Thu, 13 May 2021 11:41:04 +0530 Subject: [PATCH 33/37] arm: dts: Add support for MP03.3-C4 and MP03.3-C5 Change-Id: If84d926d07081b1d62775a88cc904158f90be797 Signed-off-by: Prasanna Kumar Thoorvas Samyrao Muralidharan --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/ipq5018-mp03.3-c4.dts | 19 +++++++++++++++++++ arch/arm/dts/ipq5018-mp03.3-c5.dts | 19 +++++++++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 arch/arm/dts/ipq5018-mp03.3-c4.dts create mode 100644 arch/arm/dts/ipq5018-mp03.3-c5.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7088b0c6c2..376d990117 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -69,6 +69,8 @@ dtb-$(CONFIG_ARCH_IPQ5018) += ipq5018-emulation.dtb \ ipq5018-mp03.3.dtb \ ipq5018-mp03.3-c2.dtb \ ipq5018-mp03.3-c3.dtb \ + ipq5018-mp03.3-c4.dtb \ + ipq5018-mp03.3-c5.dtb \ ipq5018-mp03.4-c1.dtb \ ipq5018-mp03.4-c2.dtb \ ipq5018-mp03.6-c1.dtb \ diff --git a/arch/arm/dts/ipq5018-mp03.3-c4.dts b/arch/arm/dts/ipq5018-mp03.3-c4.dts new file mode 100644 index 0000000000..0b4d311fc0 --- /dev/null +++ b/arch/arm/dts/ipq5018-mp03.3-c4.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipq5018-mp03.3.dts" +/ { + model ="QCA, IPQ5018-MP03.3-C4"; + compatible = "qca,ipq5018", "qca,ipq5018-mp03.3-c4"; + machid = <0x8040302>; + config_name = "config@mp03.3-c4"; +}; diff --git a/arch/arm/dts/ipq5018-mp03.3-c5.dts b/arch/arm/dts/ipq5018-mp03.3-c5.dts new file mode 100644 index 0000000000..97b55dae4b --- /dev/null +++ b/arch/arm/dts/ipq5018-mp03.3-c5.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipq5018-mp03.3.dts" +/ { + model ="QCA, IPQ5018-MP03.3-C5"; + compatible = "qca,ipq5018", "qca,ipq5018-mp03.3-c5"; + machid = <0x8040402>; + config_name = "config@mp03.3-c5"; +}; From 293234fda082da2eb3d3635e59e1374123484e52 Mon Sep 17 00:00:00 2001 From: Mohamed Husain Date: Thu, 20 May 2021 13:42:02 +0530 Subject: [PATCH 34/37] ipq6018: Add support for AP-CP01-C5 Signed-off-by: Mohamed Husain Change-Id: I097abd309ee3010eef302aababb74b9668d46a0a --- arch/arm/include/asm/mach-types.h | 1 + board/qca/arm/ipq6018/ipq6018.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index c92b76b1ab..a4eea15aca 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1144,6 +1144,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_IPQ6018_AP_CP01_C2 0x8030001 #define MACH_TYPE_IPQ6018_AP_CP01_C3 0x8030002 #define MACH_TYPE_IPQ6018_AP_CP01_C4 0x8030003 +#define MACH_TYPE_IPQ6018_AP_CP01_C5 0x8030004 #define MACH_TYPE_IPQ5018_AP_MP02_1 0x8040000 #define MACH_TYPE_IPQ5018_DB_MP02_1 0X1040003 #define MACH_TYPE_IPQ807x_AP_HK01_C1 0x8010000 diff --git a/board/qca/arm/ipq6018/ipq6018.c b/board/qca/arm/ipq6018/ipq6018.c index dfe61f9827..eeeffd7dc6 100644 --- a/board/qca/arm/ipq6018/ipq6018.c +++ b/board/qca/arm/ipq6018/ipq6018.c @@ -1322,6 +1322,7 @@ unsigned int get_dts_machid(unsigned int machid) { case MACH_TYPE_IPQ6018_AP_CP01_C2: case MACH_TYPE_IPQ6018_AP_CP01_C3: + case MACH_TYPE_IPQ6018_AP_CP01_C5: return MACH_TYPE_IPQ6018_AP_CP01_C1; case MACH_TYPE_IPQ6018_AP_CP01_C4: return MACH_TYPE_IPQ6018_AP_CP01_C1; @@ -1346,6 +1347,9 @@ void ipq_uboot_fdt_fixup(void) case MACH_TYPE_IPQ6018_AP_CP01_C4: config = "config@cp01-c4"; break; + case MACH_TYPE_IPQ6018_AP_CP01_C5: + config = "config@cp01-c5"; + break; } if (config != NULL) From 0e82aab85691f2d8b134cf356d2060b2bb1a80d9 Mon Sep 17 00:00:00 2001 From: "Singh, Amandeep" Date: Wed, 21 Apr 2021 02:39:09 +0530 Subject: [PATCH 35/37] dts: sirocco: Add base dts file Change-Id: I4d9e6c83cfe40518f236d324f25240d87382f652 Signed-off-by: Singh, Amandeep --- arch/arm/dts/sirocco-p0.dts | 115 ++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 arch/arm/dts/sirocco-p0.dts diff --git a/arch/arm/dts/sirocco-p0.dts b/arch/arm/dts/sirocco-p0.dts new file mode 100644 index 0000000000..6396454d59 --- /dev/null +++ b/arch/arm/dts/sirocco-p0.dts @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "ipq5018-soc.dtsi" +/ { + model ="QCA, SIROCCO-P0"; + compatible = "qca,ipq5018", "qca,sirocco-p0"; + machid = <0x1040006>; + config_name = "config@sirocco-p0"; + + aliases { + console = "/serial@78AF000"; + mmc = "/sdhci@7804000"; + }; + + console: serial@78AF000 { + status = "ok"; + serial_gpio { + blsp0_uart_rx { + gpio = <28>; + func = <3>; + pull = ; + oe = ; + drvstr = ; + od_en = ; + }; + blsp0_uart_tx { + gpio = <29>; + func = <3>; + pull = ; + oe = ; + drvstr = ; + od_en = ; + }; + blsp1_uart_rx { + gpio = <20>; + func = <0>; + pull = ; + oe = ; + drvstr = ; + od_en = ; + }; + blsp1_uart_tx { + gpio = <21>; + func = <0>; + pull = ; + oe = ; + drvstr = ; + od_en = ; + }; + + }; + }; + + mmc: sdhci@7804000 { + compatible = "qcom,sdhci-msm"; + status = "okay"; + mmc_gpio { + emmc_dat3 { + gpio = <4>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + emmc_dat2 { + gpio = <5>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + emmc_dat1 { + gpio = <6>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + emmc_dat0 { + gpio = <7>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + emmc_cmd{ + gpio = <8>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + emmc_clk{ + gpio = <9>; + func = <1>; + pull = ; + od_en = ; + drvstr = ; + }; + }; + }; + +}; From b3de3b7abfde4e21ba6b4e0e01c0dc6355706e96 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Fri, 21 May 2021 15:43:05 +0530 Subject: [PATCH 36/37] ipq50xx: update gephy debug register RW Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: Id179a343a93b465941630ba6613930c29d5ffcdd --- .../include/asm/arch-ipq5018/ipq5018_gmac.h | 4 ++- drivers/net/ipq5018/ipq5018_gmac.c | 29 ++++++++++++------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-ipq5018/ipq5018_gmac.h b/arch/arm/include/asm/arch-ipq5018/ipq5018_gmac.h index f93bca4a5f..4d71b39959 100644 --- a/arch/arm/include/asm/arch-ipq5018/ipq5018_gmac.h +++ b/arch/arm/include/asm/arch-ipq5018/ipq5018_gmac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,6 +27,8 @@ #define MPGE_PHY_MMD1_DAC_MASK 0xff00 #define PHY_DAC(val) (val<<8) #define MPGE_PHY_DEBUG_EDAC 0x4380 +#define QCA808X_DEBUG_PORT_ADDRESS 29 +#define QCA808X_DEBUG_PORT_DATA 30 #define LINK_UP 0x400 #define LINK(_data) (_data & LINK_UP)? "Up" : "Down" diff --git a/drivers/net/ipq5018/ipq5018_gmac.c b/drivers/net/ipq5018/ipq5018_gmac.c index 76f552daa1..6e8d163950 100644 --- a/drivers/net/ipq5018/ipq5018_gmac.c +++ b/drivers/net/ipq5018/ipq5018_gmac.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. +* Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -685,18 +685,27 @@ static void gephy_mdac_edac_config(ipq_gmac_board_cfg_t *gmac_cfg) (phy_data | phy_dac) ); mdelay(1); - /*set edac value*/ + /* + || set edac value debug register write follows indirect + || adressing so first write address in port address and + || write value in data register + */ + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_ADDRESS, + MPGE_PHY_DEBUG_EDAC); phy_data = ipq5018_mdio_read( gmac_cfg->phy_addr, - MPGE_PHY_DEBUG_EDAC, - NULL - ); + QCA808X_DEBUG_PORT_DATA, + NULL); + phy_data &= ~(MPGE_PHY_MMD1_DAC_MASK); - ipq5018_mdio_write( - gmac_cfg->phy_addr, - MPGE_PHY_DEBUG_EDAC, - (phy_data | phy_dac) - ); + + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_ADDRESS, + MPGE_PHY_DEBUG_EDAC); + ipq5018_mdio_write(gmac_cfg->phy_addr, + QCA808X_DEBUG_PORT_DATA, + (phy_data | phy_dac)); mdelay(1); } From c01f9cccc49bd9b55679035ad708f1391364997c Mon Sep 17 00:00:00 2001 From: Prasanna Kumar Thoorvas Samyrao Muralidharan Date: Wed, 9 Jun 2021 17:43:20 +0530 Subject: [PATCH 37/37] arm: ipq5018: Add clock line for NAND in DB.MP03.3 Change-Id: Iec5dcf6f14ab9a1542e18e9a028290b91f3f809d Signed-off-by: Prasanna Kumar Thoorvas Samyrao Muralidharan --- arch/arm/dts/ipq5018-db-mp03.3.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/ipq5018-db-mp03.3.dts b/arch/arm/dts/ipq5018-db-mp03.3.dts index 443ebff29f..ff537d59da 100644 --- a/arch/arm/dts/ipq5018-db-mp03.3.dts +++ b/arch/arm/dts/ipq5018-db-mp03.3.dts @@ -55,6 +55,12 @@ nand: nand-controller@79B0000 { status = "okay"; nand_gpio { + qspi_clk { + gpio = <9>; + func = <2>; + od_en = ; + drvstr = ; + }; qspi_dat3 { gpio = <4>; func = <2>;