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dm: i2c: Convert to driver model

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Change-Id: Ie0ac70054991783bd4f8b89af2151177a2bba0f8
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
This commit is contained in:
Ajay Kishore 2016-07-28 13:39:27 +05:30
parent d8cf279460
commit e7485c18fd
7 changed files with 85 additions and 24 deletions
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1
arch/arm/dts/ipq40xx-dk01.dts
View file

@ -24,6 +24,7 @@
console = "/serial@78af000";
xhci0 = "/xhci@8a00000";
xhci1 = "/xhci@6000000";
i2c0 = "/i2c@78b7000";
};
};

7
arch/arm/dts/ipq40xx-dk01.dtsi
View file

@ -44,5 +44,12 @@
reg = <0x6000000 0xcd00>;
rst_ctrl = <0x181E01C 0x4>;
};
i2c0: i2c@78b7000 {
compatible = "qcom,qup-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x78b7000 0x600>;
};
};

2
arch/arm/dts/ipq807x-hk01.dts
View file

@ -23,7 +23,7 @@
console = "/serial@78af000";
xhci0 = "/xhci@8a00000";
xhci1 = "/xhci@8c00000";
i2c0 = "/i2c@78b6000";
};
};

8
arch/arm/dts/ipq807x-hk01.dtsi
View file

@ -51,5 +51,11 @@
#size-cells = <1>;
reg = <0x8c00000 0xcd00>;
};
};
i2c0: i2c@78b6000 {
compatible = "qcom,qup-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x78b6000 0x600>;
};
};

88
drivers/i2c/qup_i2c.c
View file

@ -16,11 +16,22 @@
#include "qup_i2c.h"
#include <asm/io.h>
#include <asm/errno.h>
#include <fdtdec.h>
#include <dm/device.h>
#include <dm/root.h>
#include <mapmem.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
static int i2c_base_addr;
static int i2c_hw_initialized;
static int i2c_board_initialized;
struct i2c_qup_bus {
int *i2c_base_addr;
};
/*
* Reset entire QUP and all mini cores
*/
@ -91,11 +102,9 @@ void config_i2c_mode(void)
writel(cfg, i2c_base_addr + QUP_IO_MODES_OFFSET);
}
void i2c_qca_board_init(void)
void i2c_qca_board_init(struct i2c_qup_bus *i2c_bus)
{
i2c_base_addr = gboard_param->i2c_cfg->i2c_base;
qca_configure_gpio(gboard_param->i2c_cfg->i2c_gpio, NO_OF_I2C_GPIOS);
/*Need to configure GPIO*/
/* Configure the I2C clock */
i2c_clock_config();
@ -302,7 +311,7 @@ uint32_t i2c_write_read_tag(uchar chip, uint addr, int alen, int data_len)
return 0;
}
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_read_data(struct i2c_qup_bus *i2c_bus, uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int ret = 0;
int nack = 0;
@ -312,12 +321,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
int idx = 0;
int cfg;
i2c_base_addr = gboard_param->i2c_cfg->i2c_base;
config_i2c_state(QUP_STATE_RESET);
if (!i2c_board_initialized) {
i2c_qca_board_init();
i2c_qca_board_init(i2c_bus);
}
if (!i2c_hw_initialized) {
@ -457,7 +464,7 @@ uint32_t i2c_frame_wr_tag(uchar chip, uint8_t data_len, int alen)
return tag;
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
int i2c_write_data(struct i2c_qup_bus *i2c_bus, uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int ret = 0;
int nack = 0;
@ -470,13 +477,11 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
uint32_t *fifo;
uint32_t cfg;
i2c_base_addr = gboard_param->i2c_cfg->i2c_base;
/* Set to Reset State */
ret = config_i2c_state(QUP_STATE_RESET);
if (!i2c_board_initialized) {
i2c_qca_board_init();
i2c_qca_board_init(i2c_bus);
}
if (!i2c_hw_initialized) {
@ -585,19 +590,58 @@ out:
return ret;
}
/*
* Probe the given I2C chip address.
* Returns 0 if a chip responded.
*/
int i2c_probe(uchar chip)
static int qup_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
int nmsgs)
{
uchar buf;
struct i2c_qup_bus *i2c_bus = dev_get_priv(bus);
int ret;
/*send the third parameter alen as per the i2c slave*/
return i2c_read(chip, 0x0, 0x0, &buf, 0x1);
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
if (msg->flags & I2C_M_RD) {
ret = i2c_read_data(i2c_bus, msg->addr, 0, 0, msg->buf,
msg->len);
} else {
ret = i2c_write_data(i2c_bus, msg->addr, 0, 0, msg->buf,
msg->len);
}
if (ret) {
printf("i2c_write: error sending\n");
return -EREMOTEIO;
}
}
return 0;
}
void i2c_init(int speed, int slaveaddr)
/* Probe to see if a chip is present. */
static int qup_i2c_probe_chip(struct udevice *bus, uint chip_addr,
uint chip_flags)
{
debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
uchar buf[1];
struct i2c_qup_bus *i2c_bus = dev_get_priv(bus);
buf[0] = 0;
i2c_bus->i2c_base_addr = (int *)dev_get_addr(bus);
i2c_base_addr = (int)i2c_bus->i2c_base_addr;
return i2c_read_data(i2c_bus, chip_addr , 0x0, 0x0, buf, 0x1);
}
static const struct dm_i2c_ops qup_i2c_ops = {
.xfer = qup_i2c_xfer,
.probe_chip = qup_i2c_probe_chip,
};
static const struct udevice_id qpic_ver_ids[] = {
{ .compatible = "qcom,qup-i2c"},
{ },
};
U_BOOT_DRIVER(i2c_qup) = {
.name = "i2c_qup",
.id = UCLASS_I2C,
.of_match = qpic_ver_ids,
.priv_auto_alloc_size = sizeof(struct i2c_qup_bus),
.ops = &qup_i2c_ops,
};

1
include/fdtdec.h
View file

@ -172,6 +172,7 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_QCOM_QPIC_NAND_V1_5_20, /* Qualcomm QPIC NAND controller */
COMPAT_QCOM_QPIC_NAND_V1_4_20, /* Qualcomm QPIC NAND controller */
COMPAT_QCOM_QUP_I2C, /* Qualcomm QUP I2C controller */
COMPAT_COUNT,
};

2
lib/fdtdec.c
View file

@ -77,6 +77,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(COMPAT_QCOM_QPIC_NAND_V1_5_20, "qcom,qpic-nand.1.5.20"),
COMPAT(COMPAT_QCOM_QPIC_NAND_V1_4_20, "qcom,qpic-nand.1.4.20"),
COMPAT(COMPAT_QCOM_QPIC_NAND_V1_4_20, "qcom,qpic-nand.1.4.20"),
COMPAT(QCOM_QUP_I2C, "qcom,qup-ip2c"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)