ipq9574: Inialialize ethernet ports during boot up

This patch sets the function select as mdc_mdio and also
adds AQUANTIA, QCA80xx PHY ASSERT and DE-ASSERT support.

Change-Id: Ib606b51342df4e80d705271cc661f6fbe1664ed0
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org

arch/arm/include/asm/arch-qca-common/qca_common.h

@@ -104,8 +104,12 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla
 
 int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
 void set_ethmac_addr(void);
+
+#ifndef CONFIG_IPQ9574_RUMI
 void aquantia_phy_reset_init_done(void);
 void aquantia_phy_reset_init(void);
+#endif
+
 int bring_sec_core_up(unsigned int cpuid, unsigned int entry, unsigned int arg);
 int is_secondary_core_off(unsigned int cpuid);
 int smem_read_cpu_count(void);

board/qca/arm/common/board_init.c

@@ -221,7 +221,9 @@ int board_init(void)
 		}
 	}
 
+#ifndef CONFIG_IPQ9574_RUMI
 	aquantia_phy_reset_init();
+#endif
 	disable_audio_clks();
 	ipq_uboot_fdt_fixup();
 	/*

board/qca/arm/common/cmd_bootqca.c

@@ -848,7 +848,9 @@ static int do_bootipq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 	ret = qca_scm_call(SCM_SVC_FUSE, QFPROM_IS_AUTHENTICATE_CMD, &buf, sizeof(char));
 
+#ifndef CONFIG_IPQ9574_RUMI
 	aquantia_phy_reset_init_done();
+#endif
 	/*
 	|| if atf is enable in env ,do_boot_signedimg is skip.
 	|| Note: This features currently support in ipq50XX.

board/qca/arm/ipq9574/ipq9574.c

@@ -680,11 +680,206 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla
 }
 #endif
 
+#ifndef CONFIG_IPQ9574_RUMI
+int get_aquantia_gpio(int aquantia_gpio[2])
+{
+	int aquantia_gpio_cnt = -1, node;
+	int res = -1;
+
+	node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
+	if (node >= 0) {
+		aquantia_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_gpio_cnt", -1);
+		if (aquantia_gpio_cnt >= 1) {
+			res = fdtdec_get_int_array(gd->fdt_blob, node, "aquantia_gpio",
+						  (u32 *)aquantia_gpio, aquantia_gpio_cnt);
+			if (res >= 0)
+				return aquantia_gpio_cnt;
+		}
+	}
+
+	return res;
+}
+
+int get_napa_gpio(int napa_gpio[2])
+{
+	int napa_gpio_cnt = -1, node;
+	int res = -1;
+
+	node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
+	if (node >= 0) {
+		napa_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "napa_gpio_cnt", -1);
+		if (napa_gpio_cnt >= 1) {
+			res = fdtdec_get_int_array(gd->fdt_blob, node, "napa_gpio",
+						  (u32 *)napa_gpio, napa_gpio_cnt);
+			if (res >= 0)
+				return napa_gpio_cnt;
+		}
+	}
+
+	return res;
+}
+
+int get_malibu_gpio(int malibu_gpio[2])
+{
+	int malibu_gpio_cnt = -1, node;
+	int res = -1;
+
+	node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
+	if (node >= 0) {
+		malibu_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "malibu_gpio_cnt", -1);
+		if (malibu_gpio_cnt >= 1) {
+			res = fdtdec_get_int_array(gd->fdt_blob, node, "malibu_gpio",
+						  (u32 *)malibu_gpio, malibu_gpio_cnt);
+			if (res >= 0)
+				return malibu_gpio_cnt;
+		}
+	}
+
+	return res;
+}
+
+void aquantia_phy_reset_init(void)
+{
+	int aquantia_gpio[2] = {0}, aquantia_gpio_cnt, i;
+	unsigned int *aquantia_gpio_base;
+
+	aquantia_gpio_cnt = get_aquantia_gpio(aquantia_gpio);
+	if (aquantia_gpio_cnt >= 1) {
+		for (i = 0; i < aquantia_gpio_cnt; i++) {
+			if (aquantia_gpio[i] >= 0) {
+				aquantia_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(aquantia_gpio[i]);
+				writel(0x203, aquantia_gpio_base);
+				gpio_direction_output(aquantia_gpio[i], 0x0);
+			}
+		}
+	}
+}
+
+void napa_phy_reset_init(void)
+{
+	int napa_gpio[2] = {0}, napa_gpio_cnt, i;
+	unsigned int *napa_gpio_base;
+
+	napa_gpio_cnt = get_napa_gpio(napa_gpio);
+	if (napa_gpio_cnt >= 1) {
+		for (i = 0; i < napa_gpio_cnt; i++) {
+			if (napa_gpio[i] >= 0) {
+				napa_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(napa_gpio[i]);
+				writel(0x203, napa_gpio_base);
+				gpio_direction_output(napa_gpio[i], 0x0);
+			}
+		}
+	}
+}
+
+void malibu_phy_reset_init(void)
+{
+	int malibu_gpio[2] = {0}, malibu_gpio_cnt, i;
+	unsigned int *malibu_gpio_base;
+
+	malibu_gpio_cnt = get_malibu_gpio(malibu_gpio);
+	if (malibu_gpio_cnt >= 1) {
+		for (i = 0; i < malibu_gpio_cnt; i++) {
+			if (malibu_gpio[i] >=0) {
+				malibu_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(malibu_gpio[i]);
+				writel(0x203, malibu_gpio_base);
+				gpio_direction_output(malibu_gpio[i], 0x0);
+			}
+		}
+	}
+}
+
+void aquantia_phy_reset_init_done(void)
+{
+	int aquantia_gpio[2] = {0}, aquantia_gpio_cnt, i;
+
+	aquantia_gpio_cnt = get_aquantia_gpio(aquantia_gpio);
+	if (aquantia_gpio_cnt >= 1) {
+		for (i = 0; i < aquantia_gpio_cnt; i++)
+			gpio_set_value(aquantia_gpio[i], 0x1);
+	}
+}
+
+void napa_phy_reset_init_done(void)
+{
+	int napa_gpio[2] = {0}, napa_gpio_cnt, i;
+
+	napa_gpio_cnt = get_napa_gpio(napa_gpio);
+	if (napa_gpio_cnt >= 1) {
+		for (i = 0; i < napa_gpio_cnt; i++)
+			gpio_set_value(napa_gpio[i], 0x1);
+	}
+}
+
+void malibu_phy_reset_init_done(void)
+{
+	int malibu_gpio[2] = {0}, malibu_gpio_cnt, i;
+
+	malibu_gpio_cnt = get_malibu_gpio(malibu_gpio);
+	if (malibu_gpio_cnt >= 1) {
+		for (i = 0; i < malibu_gpio_cnt; i++)
+			gpio_set_value(malibu_gpio[i], 0x1);
+	}
+}
+
+int get_mdc_mdio_gpio(int mdc_mdio_gpio[2])
+{
+	int mdc_mdio_gpio_cnt = 2, node;
+	int res = -1;
+	node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
+	if (node >= 0) {
+		res = fdtdec_get_int_array(gd->fdt_blob, node, "mdc_mdio_gpio",
+					   (u32 *)mdc_mdio_gpio, mdc_mdio_gpio_cnt);
+		if (res >= 0)
+			return mdc_mdio_gpio_cnt;
+	}
+
+	return res;
+}
+
+void set_function_select_as_mdc_mdio(void)
+{
+	int mdc_mdio_gpio[2] = {0}, mdc_mdio_gpio_cnt, i;
+	unsigned int *mdc_mdio_gpio_base;
+
+	mdc_mdio_gpio_cnt = get_mdc_mdio_gpio(mdc_mdio_gpio);
+	if (mdc_mdio_gpio_cnt >= 1) {
+		for (i = 0; i < mdc_mdio_gpio_cnt; i++) {
+			if (mdc_mdio_gpio[i] >=0) {
+				mdc_mdio_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(mdc_mdio_gpio[i]);
+				writel(0xC7, mdc_mdio_gpio_base);
+			}
+		}
+	}
+}
+
+void eth_clock_enable(void)
+{
+	/* PPE CLK INIT and NSS PPE ASSERT/DE-ASSERT must be added */
+
+	/* set function select as mdio */
+	set_function_select_as_mdc_mdio();
+
+	/* bring phy out of reset */
+	malibu_phy_reset_init();
+	aquantia_phy_reset_init();
+	napa_phy_reset_init();
+	mdelay(500);
+	malibu_phy_reset_init_done();
+	aquantia_phy_reset_init_done();
+	napa_phy_reset_init_done();
+	mdelay(500);
+}
+#endif
+
 int board_eth_init(bd_t *bis)
 {
 	int ret=0;
 
-	/* eth_clock_enable must be added */
+#ifndef CONFIG_IPQ9574_RUMI
+	eth_clock_enable();
+#endif
+
 	ret = ipq9574_edma_init(NULL);
 
 	if (ret != 0)

board/qca/arm/ipq9574/ipq9574.h

@@ -299,9 +299,6 @@ struct smem_ram_ptn {
 	unsigned reserved2, reserved3, reserved4, reserved5;
 } __attribute__ ((__packed__));
 
-__weak void aquantia_phy_reset_init_done(void) {}
-__weak void aquantia_phy_reset_init(void) {}
-
 struct smem_ram_ptable {
 #define _SMEM_RAM_PTABLE_MAGIC_1	0x9DA5E0A8
 #define _SMEM_RAM_PTABLE_MAGIC_2	0xAF9EC4E2