mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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ipq807x: Added the support for aquantia firmware download
Change-Id: Iebef6426e6ffdef7e3c5fb8c6a04c2c6f494a664 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This commit is contained in:
Sham Muthayyan
Gerrit - the friendly Code Review server
parent
7d086407d3
commit
e216c7f3ab
4 changed files with 272 additions and 1 deletions
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@ -20,6 +20,7 @@
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#include <miiphy.h>
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#include "ipq_phy.h"
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#include "ipq807x_aquantia_phy.h"
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#include <crc.h>
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extern int ipq_mdio_write(int mii_id,
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int regnum, u16 value);
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@ -106,6 +107,27 @@ u32 aq_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed)
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return 0;
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}
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void aquantia_phy_restart_autoneg(u32 phy_id)
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{
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u16 phy_data;
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_PHY_XS_REGISTERS,
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AQUANTIA_PHY_XS_USX_TRANSMIT));
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if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE))
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aq_phy_reg_write(0x0, phy_id,AQUANTIA_REG_ADDRESS(
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AQUANTIA_MMD_PHY_XS_REGISTERS,
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AQUANTIA_PHY_XS_USX_TRANSMIT),
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phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE);
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phy_data = aq_phy_reg_read(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG,
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AQUANTIA_AUTONEG_STANDARD_CONTROL1));
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phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_AUTONEG,
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AQUANTIA_AUTONEG_STANDARD_CONTROL1),
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phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION);
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}
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int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id)
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{
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u16 phy_data;
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@ -142,7 +164,236 @@ int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id)
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phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK;
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aq_phy_reg_write(0x0, phy_id, AQUANTIA_REG_ADDRESS(AQUANTIA_MMD_GLOABLE_REGISTERS,
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AQUANTIA_GLOBAL_INTR_VENDOR_MASK), phy_data);
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return 0;
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}
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#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300
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static int do_load_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i;
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uint32_t load_addr;
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uint32_t file_size;
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unsigned int phy_addr;
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uint8_t *buf;
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uint16_t file_crc;
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uint16_t computed_crc;
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uint32_t reg1, reg2;
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uint16_t recorded_ggp8_val;
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uint16_t daisy_chain_dis;
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uint32_t primary_header_ptr = 0x00000000;
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uint32_t primary_iram_ptr = 0x00000000;
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uint32_t primary_dram_ptr = 0x00000000;
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uint32_t primary_iram_sz = 0x00000000;
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uint32_t primary_dram_sz = 0x00000000;
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uint32_t phy_img_hdr_off;
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uint32_t byte_sz;
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uint32_t dword_sz;
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uint32_t byte_ptr;
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uint16_t msw;
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uint16_t lsw;
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uint8_t msb1;
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uint8_t msb2;
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uint8_t lsb1;
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uint8_t lsb2;
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uint16_t mailbox_crc;
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if (argc < 4)
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return CMD_RET_USAGE;
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phy_addr = simple_strtoul(argv[1], NULL, 16);
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load_addr = simple_strtoul(argv[2], NULL, 16);
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file_size = simple_strtoul(argv[3], NULL, 16);
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if (phy_addr != AQU_PHY_ADDR) {
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printf("Phy address is not correct: use 0x7\n");
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return 0;
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}
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300), 0xdead);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301), 0xbeaf);
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reg1 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x300));
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reg2 = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x301));
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if(reg1 != 0xdead && reg2 != 0xbeaf) {
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printf("Scratchpad Read/Write test fail\n");
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return 0;
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}
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buf = (uint8_t *)load_addr;
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file_crc = buf[file_size - 2] << 8 | buf[file_size - 1];
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computed_crc = cyg_crc16(buf, file_size - 2);
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if (file_crc != computed_crc) {
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printf("CRC check failed on image file\n");
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return 0;
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} else {
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printf ("CRC check good on image file (0x%04X)\n",computed_crc);
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}
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daisy_chain_dis = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452));
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if (!(daisy_chain_dis & 0x1))
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc452), 0x1);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc471), 0x40);
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recorded_ggp8_val = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447));
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if ((recorded_ggp8_val & 0x1f) != phy_addr)
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc447), phy_addr);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x4000);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41);
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primary_header_ptr = (((buf[0x9] & 0x0F) << 8) | buf[0x8]) << 12;
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phy_img_hdr_off = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD;
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primary_iram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 2] << 16) |
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(buf[primary_header_ptr + phy_img_hdr_off + 0x4 + 1] << 8) |
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buf[primary_header_ptr + phy_img_hdr_off + 0x4];
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primary_iram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 2] << 16) |
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(buf[primary_header_ptr + phy_img_hdr_off + 0x7 + 1] << 8) |
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buf[primary_header_ptr + phy_img_hdr_off + 0x7];
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primary_dram_ptr = (buf[primary_header_ptr + phy_img_hdr_off + 0xA + 2] << 16) |
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(buf[primary_header_ptr + phy_img_hdr_off + 0xA + 1] << 8) |
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buf[primary_header_ptr + phy_img_hdr_off + 0xA];
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primary_dram_sz = (buf[primary_header_ptr + phy_img_hdr_off + 0xD + 2] << 16) |
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(buf[primary_header_ptr + phy_img_hdr_off + 0xD + 1] << 8) |
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buf[primary_header_ptr + phy_img_hdr_off + 0xD];
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primary_iram_ptr += primary_header_ptr;
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primary_dram_ptr += primary_header_ptr;
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printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n");
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printf ("Primary Iram Address: 0x%x\n", primary_iram_ptr);
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printf ("Primary Iram Size: 0x%x\n", primary_iram_sz);
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printf ("Primary Dram Address: 0x%x\n", primary_dram_ptr);
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printf ("Primary Dram Size: 0x%x\n", primary_dram_sz);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x1000);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0x0);
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computed_crc = 0;
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printf("Loading IRAM\n");
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x4000);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0);
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byte_sz = primary_iram_sz;
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dword_sz = byte_sz >> 2;
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byte_ptr = primary_iram_ptr;
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for (i = 0; i < dword_sz; i++) {
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000);
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msb1 = msw >> 8;
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msb2 = msw & 0xFF;
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lsb1 = lsw >> 8;
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lsb2 = lsw & 0xFF;
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computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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if (i && ((i % 512) == 0))
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printf(" Byte: %X:\n", i << 2);
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}
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switch (byte_sz & 0x3) {
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case 0x1:
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lsw = buf[byte_ptr++];
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msw = 0x0000;
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break;
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case 0x2:
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = 0x0000;
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break;
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case 0x3:
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = buf[byte_ptr++];
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break;
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}
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if (byte_sz & 0x3) {
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000);
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msb1 = msw >> 8;
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msb2 = msw & 0xFF;
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lsb1 = lsw >> 8;
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lsb2 = lsw & 0xFF;
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computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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}
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printf("Loading DRAM\n");
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x202), 0x3ffe);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x203), 0x0);
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byte_sz = primary_dram_sz;
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dword_sz = byte_sz >> 2;
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byte_ptr = primary_dram_ptr;
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for (i = 0; i < dword_sz; i++) {
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000);
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msb1 = msw >> 8;
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msb2 = msw & 0xFF;
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lsb1 = lsw >> 8;
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lsb2 = lsw & 0xFF;
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computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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if (i && ((i % 512) == 0))
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printf(" Byte: %X:\n", i << 2);
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}
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switch (byte_sz & 0x3) {
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case 0x1:
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lsw = buf[byte_ptr++];
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msw = 0x0000;
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break;
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case 0x2:
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = 0x0000;
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break;
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case 0x3:
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lsw = (buf[byte_ptr + 1] << 8) | buf[byte_ptr];
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byte_ptr += 2;
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msw = buf[byte_ptr++];
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break;
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}
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if (byte_sz & 0x3) {
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x204), msw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x205), lsw);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x200), 0xc000);
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msb1 = msw >> 8;
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msb2 = msw & 0xFF;
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lsb1 = lsw >> 8;
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lsb2 = lsw & 0xFF;
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computed_crc = cyg_crc16_computed(&msb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&msb2, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb1, 0x1, computed_crc);
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computed_crc = cyg_crc16_computed(&lsb2, 0x1, computed_crc);
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}
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc441), 0x2010);
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mailbox_crc = aq_phy_reg_read(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x201));
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if (mailbox_crc != computed_crc)
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printf("Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", mailbox_crc, computed_crc);
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else
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printf("Image load good - mailbox CRC-16 matches (0x%X)\n", mailbox_crc);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0x0), 0x0);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x41);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x8041);
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mdelay(100);
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aq_phy_reg_write(0x0, phy_addr, AQUANTIA_REG_ADDRESS(0x1e, 0xc001), 0x40);
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mdelay(100);
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aquantia_phy_restart_autoneg(phy_addr);
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return 0;
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}
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U_BOOT_CMD(
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aq_load_fw, 5, 1, do_load_fw,
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"LOAD aq-fw-binary",
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""
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);
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@ -31,6 +31,10 @@
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#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01
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#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001
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#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0
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#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000
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#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200
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#define AQ_PHY_AUTO_STATUS_REG 0x70001
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#define PORT_LINK_DOWN 0
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#define PORT_LINK_UP 1
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@ -66,4 +66,6 @@ cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
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extern uint16_t cyg_crc16(unsigned char *s, int len);
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extern uint16_t cyg_crc16_computed(unsigned char *buf, int len, uint16_t computed_crc);
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#endif /* _SERVICES_CRC_CRC_H_ */
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14
lib/crc16.c
14
lib/crc16.c
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@ -73,3 +73,17 @@ cyg_crc16(unsigned char *buf, int len)
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}
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return cksum;
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}
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uint16_t
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cyg_crc16_computed(unsigned char *buf, int len, uint16_t computed_crc)
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{
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int i;
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uint16_t cksum;
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cksum = computed_crc;
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for (i = 0; i < len; i++) {
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cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
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}
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return cksum;
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}
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