mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
Merge "ipq6018: Enable USB support"
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commit
df527e6248
6 changed files with 500 additions and 9 deletions
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@ -23,6 +23,8 @@
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console = "/serial@78af000";
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mmc = "/sdhci@7804000";
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i2c0 = "/i2c@78b6000";
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usb0 = "/xhci@8a00000";
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usb1 = "/xhci@7000000";
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};
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serial@78af000 {
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compatible = "qca,ipq-uartdm";
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@ -49,7 +51,6 @@
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compatible = "qcom,sdhci-msm";
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};
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i2c0: i2c@78b6000 {
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compatible = "qcom,qup-i2c";
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#address-cells = <1>;
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@ -75,4 +76,13 @@
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};
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};
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};
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xhci@8a00000 {
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qcom,emulation = <1>;
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};
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xhci@7000000 {
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qcom,emulation = <1>;
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};
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};
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@ -52,5 +52,19 @@
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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xhci@8a00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8a00000 0xcd00>;
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};
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xhci@7000000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x7000000 0xcd00>;
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};
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};
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@ -23,6 +23,7 @@
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#include <ipq6018.h>
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#include <mmc.h>
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#include <sdhci.h>
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sdhci_host mmc_host;
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@ -232,10 +233,337 @@ void board_nand_init(void)
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}
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#endif
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}
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void set_flash_secondary_type(qca_smem_flash_info_t *smem)
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{
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return;
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};
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#ifdef CONFIG_USB_XHCI_IPQ
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void board_usb_deinit(int id)
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{
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void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
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void __iomem *usb_phy_bcr, *usb_gen_cfg, *usb_guctl, *phy_base;
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if (id == 0) {
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boot_clk_ctl = GCC_USB_0_BOOT_CLOCK_CTL;
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usb_bcr = GCC_USB0_BCR;
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qusb2_phy_bcr = GCC_QUSB2_0_PHY_BCR;
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usb_phy_bcr = GCC_USB0_PHY_BCR;
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usb_gen_cfg = USB30_1_GENERAL_CFG;
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usb_guctl = USB30_1_GUCTL;
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phy_base = USB30_PHY_1_QUSB2PHY_BASE;
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}
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else if (id == 1) {
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boot_clk_ctl = GCC_USB_1_BOOT_CLOCK_CTL;
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usb_bcr = GCC_USB1_BCR;
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qusb2_phy_bcr = GCC_QUSB2_1_PHY_BCR;
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phy_base = USB30_PHY_2_QUSB2PHY_BASE;
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}
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else {
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return;
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}
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//Enable USB2 PHY Power down
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setbits_le32(phy_base+0xB4, 0x1);
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if (id == 0) {
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB0_MASTER_CBCR);
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writel(0, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(0, GCC_SNOC_BUS_TIMEOUT1_AHB_CBCR);
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writel(0, GCC_USB0_SLEEP_CBCR);
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writel(0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0, GCC_USB0_AUX_CBCR);
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}
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else if (id == 1) {
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writel(0x8000, GCC_USB1_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB1_MASTER_CBCR);
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writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(0, GCC_USB1_SLEEP_CBCR);
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writel(0, GCC_USB1_MOCK_UTMI_CBCR);
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}
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//GCC_QUSB2_0_PHY_BCR
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setbits_le32(qusb2_phy_bcr, 0x1);
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mdelay(10);
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clrbits_le32(qusb2_phy_bcr, 0x1);
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//GCC_USB0_PHY_BCR
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setbits_le32(usb_phy_bcr, 0x1);
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mdelay(10);
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clrbits_le32(usb_phy_bcr, 0x1);
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//GCC Reset USB0 BCR
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setbits_le32(usb_bcr, 0x1);
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mdelay(10);
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clrbits_le32(usb_bcr, 0x1);
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}
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static void usb_clock_init(int id)
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{
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if (id == 0) {
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writel(0x222000, GCC_USB0_GDSCR);
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writel(0, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(0, GCC_SNOC_BUS_TIMEOUT1_AHB_CBCR);
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writel(0x10b, GCC_USB0_MASTER_CFG_RCGR);
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writel(0x1, GCC_USB0_MASTER_CMD_RCGR);
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writel(1, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(0xcff1, GCC_USB0_MASTER_CBCR);
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writel(1, GCC_SNOC_BUS_TIMEOUT1_AHB_CBCR);
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writel(1, GCC_USB0_SLEEP_CBCR);
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writel(0x210b, GCC_USB0_MOCK_UTMI_CFG_RCGR);
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writel(0x1, GCC_USB0_MOCK_UTMI_M);
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writel(0xf7, GCC_USB0_MOCK_UTMI_N);
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writel(0xf6, GCC_USB0_MOCK_UTMI_D);
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writel(0x3, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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writel(1, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0x8001, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(1, GCC_USB0_AUX_CBCR);
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writel(1, GCC_USB0_PIPE_CBCR);
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}
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else if (id == 1) {
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writel(0x222000, GCC_USB1_GDSCR);
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writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(0xcff1, GCC_USB1_MASTER_CBCR);
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writel(1, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(1, GCC_USB1_SLEEP_CBCR);
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writel(0x210b, GCC_USB1_MOCK_UTMI_CFG_RCGR);
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writel(0x1, GCC_USB1_MOCK_UTMI_M);
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writel(0xf7, GCC_USB1_MOCK_UTMI_N);
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writel(0xf6, GCC_USB1_MOCK_UTMI_D);
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writel(0x3, GCC_USB1_MOCK_UTMI_CMD_RCGR);
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writel(1, GCC_USB1_MOCK_UTMI_CBCR);
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writel(0x8001, GCC_USB1_PHY_CFG_AHB_CBCR);
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}
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}
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static void usb_init_ssphy(int index)
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{
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void __iomem *phybase;
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if (index == 0) {
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phybase = USB30_PHY_1_USB3PHY_AHB2PHY_BASE;
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}
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else if (index == 1) {
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phybase = USB30_PHY_2_USB2PHY_AHB2PHY_BASE;
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} else
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return;
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out_8(phybase + USB3_PHY_POWER_DOWN_CONTROL,0x1);
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out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x1a);
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out_8(phybase + QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08);
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out_8(phybase + QSERDES_COM_CLK_SELECT,0x30);
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out_8(phybase + QSERDES_COM_BG_TRIM,0x0f);
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out_8(phybase + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b);
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out_8(phybase + QSERDES_COM_SVS_MODE_CLK_SEL,0x01);
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out_8(phybase + QSERDES_COM_HSCLK_SEL,0x00);
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out_8(phybase + QSERDES_COM_CMN_CONFIG,0x06);
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out_8(phybase + QSERDES_COM_PLL_IVCO,0x0f);
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out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x06);
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out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x82);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0x55);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0x55);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x03);
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out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x0b);
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out_8(phybase + QSERDES_COM_PLL_RCTRL_MODE0,0x16);
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out_8(phybase + QSERDES_COM_PLL_CCTRL_MODE0,0x28);
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out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0x80);
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out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0x15);
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out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x34);
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out_8(phybase + QSERDES_COM_LOCK_CMP3_MODE0,0x00);
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out_8(phybase + QSERDES_COM_CORE_CLK_EN,0x00);
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out_8(phybase + QSERDES_COM_LOCK_CMP_CFG,0x00);
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out_8(phybase + QSERDES_COM_VCO_TUNE_MAP,0x00);
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out_8(phybase + QSERDES_COM_BG_TIMER,0x0a);
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out_8(phybase + QSERDES_COM_SSC_EN_CENTER,0x01);
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out_8(phybase + QSERDES_COM_SSC_PER1,0x31);
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out_8(phybase + QSERDES_COM_SSC_PER2,0x01);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER1,0x00);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER2,0x00);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0xde);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x07);
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out_8(phybase + QSERDES_RX_UCDR_SO_GAIN,0x06);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8);
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out_8(phybase + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL,0x77);
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out_8(phybase + QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2,0x80);
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out_8(phybase + QSERDES_RX_SIGDET_CNTRL,0x03);
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out_8(phybase + QSERDES_RX_SIGDET_DEGLITCH_CNTRL,0x16);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0c);
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out_8(phybase + QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D,0x45);
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out_8(phybase + QSERDES_TX_RCV_DETECT_LVL_2,0x12);
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out_8(phybase + QSERDES_TX_LANE_MODE,0x06);
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out_8(phybase + PCS_TXDEEMPH_M6DB_V0,0x15);
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out_8(phybase + PCS_TXDEEMPH_M3P5DB_V0,0x0e);
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out_8(phybase + PCS_FLL_CNTRL2,0x83);
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out_8(phybase + PCS_FLL_CNTRL1,0x02);
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out_8(phybase + PCS_FLL_CNT_VAL_L,0x09);
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out_8(phybase + PCS_FLL_CNT_VAL_H_TOL,0xa2);
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out_8(phybase + PCS_FLL_MAN_CODE,0x85);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG1,0xd1);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG2,0x1f);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG3,0x47);
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out_8(phybase + PCS_POWER_STATE_CONFIG2,0x1b);
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out_8(phybase + PCS_RXEQTRAINING_WAIT_TIME,0x75);
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out_8(phybase + PCS_RXEQTRAINING_RUN_TIME,0x13);
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out_8(phybase + PCS_LFPS_TX_ECSTART_EQTLOCK,0x86);
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out_8(phybase + PCS_PWRUP_RESET_DLY_TIME_AUXCLK,0x04);
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out_8(phybase + PCS_TSYNC_RSYNC_TIME,0x44);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_L,0xe7);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_H,0x03);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_L,0x40);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_H,0x00);
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out_8(phybase + PCS_RX_SIGDET_LVL,0x88);
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out_8(phybase + USB3_PCS_TXDEEMPH_M6DB_V0,0x17);
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out_8(phybase + USB3_PCS_TXDEEMPH_M3P5DB_V0,0x0f);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0);
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out_8(phybase + USB3_PHY_START_CONTROL,0x03);
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out_8(phybase + USB3_PHY_SW_RESET,0x00);
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}
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static void usb_init_phy(int index)
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{
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void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
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void __iomem *usb_phy_bcr, *usb3_phy_bcr, *usb_gen_cfg, *usb_guctl, *phy_base;
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if (index == 0) {
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boot_clk_ctl = GCC_USB_0_BOOT_CLOCK_CTL;
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usb_bcr = GCC_USB0_BCR;
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qusb2_phy_bcr = GCC_QUSB2_0_PHY_BCR;
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usb_phy_bcr = GCC_USB0_PHY_BCR;
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usb3_phy_bcr = GCC_USB3PHY_0_PHY_BCR;
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usb_gen_cfg = USB30_1_GENERAL_CFG;
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usb_guctl = USB30_1_GUCTL;
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phy_base = USB30_PHY_1_QUSB2PHY_BASE;
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}
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else if (index == 1) {
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boot_clk_ctl = GCC_USB_1_BOOT_CLOCK_CTL;
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usb_bcr = GCC_USB1_BCR;
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qusb2_phy_bcr = GCC_QUSB2_1_PHY_BCR;
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phy_base = USB30_PHY_2_QUSB2PHY_BASE;
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}
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else {
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return;
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}
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//2. Enable SS Ref Clock
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setbits_le32(GCC_USB_SS_REF_CLK_EN, 0x1);
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//3. Disable USB Boot Clock
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clrbits_le32(boot_clk_ctl, 0x0);
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//4. GCC Reset USB0 BCR
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setbits_le32(usb_bcr, 0x1);
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//5. Delay 100us
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mdelay(10);
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//6. GCC Reset USB0 BCR
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clrbits_le32(usb_bcr, 0x1);
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//7. GCC_QUSB2_0_PHY_BCR
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setbits_le32(qusb2_phy_bcr, 0x1);
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//8. GCC_USB0_PHY_BCR
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setbits_le32(usb_phy_bcr, 0x1);
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setbits_le32(usb3_phy_bcr, 0x1);
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//9. Delay 100us
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mdelay(10);
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//10. GCC_USB0_PHY_BCR
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clrbits_le32(usb3_phy_bcr, 0x1);
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clrbits_le32(usb_phy_bcr, 0x1);
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//11. GCC_QUSB2_0_PHY_BCR
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clrbits_le32(qusb2_phy_bcr, 0x1);
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//12. Delay 100us
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mdelay(10);
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//20. Config user control register
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writel(0x0c80c010, usb_guctl);
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//21. Enable USB2 PHY Power down
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setbits_le32(phy_base+0xB4, 0x1);
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//22. PHY Config Sequence
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out_8(phy_base+0x80, 0xF8);
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out_8(phy_base+0x84, 0x83);
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out_8(phy_base+0x88, 0x83);
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out_8(phy_base+0x8C, 0xC0);
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out_8(phy_base+0x9C, 0x14);
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out_8(phy_base+0x08, 0x30);
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out_8(phy_base+0x0C, 0x79);
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out_8(phy_base+0x10, 0x21);
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out_8(phy_base+0x90, 0x00);
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out_8(phy_base+0x18, 0x00);
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out_8(phy_base+0x1C, 0x9F);
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out_8(phy_base+0x04, 0x80);
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//23. Disable USB2 PHY Power down
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clrbits_le32(phy_base+0xB4, 0x1);
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usb_init_ssphy(index);
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}
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int ipq_board_usb_init(void)
|
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{
|
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int i, nodeoff;
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char node, usb_node[4] = "usb\0";
|
||||
|
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for (i=0; i<CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
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node = i + '0';
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usb_node[3] = node;
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nodeoff = fdt_path_offset(gd->fdt_blob, usb_node);
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if (!fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0)) {
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usb_clock_init(i);
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usb_init_phy(i);
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}
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}
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return 0;
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||||
}
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||||
#endif
|
||||
|
||||
void ipq_fdt_fixup_usb_device_mode(void *blob)
|
||||
{
|
||||
int nodeoff, ret, node;
|
||||
const char *usb_dr_mode = "peripheral"; /* Supported mode */
|
||||
const char *usb_max_speed = "high-speed";/* Supported speed */
|
||||
const char *usb_node[] = {"/soc/usb3@8A00000/dwc3@8A00000"};
|
||||
const char *usb_cfg;
|
||||
|
||||
usb_cfg = getenv("usb_mode");
|
||||
if (!usb_cfg)
|
||||
return;
|
||||
|
||||
if (strcmp(usb_cfg, usb_dr_mode)) {
|
||||
printf("fixup_usb: usb_mode can be either 'peripheral' or not set\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (node = 0; node < ARRAY_SIZE(usb_node); node++) {
|
||||
nodeoff = fdt_path_offset(blob, usb_node[node]);
|
||||
if (nodeoff < 0) {
|
||||
printf("fixup_usb: unable to find node '%s'\n",
|
||||
usb_node[node]);
|
||||
return;
|
||||
}
|
||||
ret = fdt_setprop(blob, nodeoff, "dr_mode",
|
||||
usb_dr_mode,
|
||||
(strlen(usb_dr_mode) + 1));
|
||||
if (ret)
|
||||
printf("fixup_usb: 'dr_mode' cannot be set");
|
||||
|
||||
/* if mode is peripheral restricting to high-speed */
|
||||
ret = fdt_setprop(blob, nodeoff, "maximum-speed",
|
||||
usb_max_speed,
|
||||
(strlen(usb_max_speed) + 1));
|
||||
if (ret)
|
||||
printf("fixup_usb: 'maximum-speed' cannot be set");
|
||||
}
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
|
||||
|
|
@ -283,13 +611,7 @@ void ipq_fdt_fixup_socinfo(void *blob)
|
|||
return;
|
||||
}
|
||||
|
||||
void ipq_fdt_fixup_usb_device_mode(void *blob)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void fdt_fixup_auto_restart(void *blob)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,125 @@
|
|||
|
||||
#define CLOCK_UPDATE_TIMEOUT_US 1000
|
||||
#define KERNEL_AUTH_CMD 0x13
|
||||
|
||||
/* USB Registers */
|
||||
#define GCC_USB0_GDSCR 0x183E078
|
||||
#define GCC_SYS_NOC_USB0_AXI_CBCR 0x1826040
|
||||
#define GCC_SNOC_BUS_TIMEOUT1_AHB_CBCR 0x184700C
|
||||
#define GCC_USB0_MASTER_CFG_RCGR 0x183E010
|
||||
#define GCC_USB0_MASTER_CMD_RCGR 0x183E00C
|
||||
#define GCC_USB0_MASTER_CBCR 0x183E000
|
||||
#define GCC_USB0_SLEEP_CBCR 0x183E004
|
||||
#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x0183E024
|
||||
#define GCC_USB0_MOCK_UTMI_M 0x0183E028
|
||||
#define GCC_USB0_MOCK_UTMI_N 0x0183E02C
|
||||
#define GCC_USB0_MOCK_UTMI_D 0x0183E030
|
||||
#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x183E020
|
||||
#define GCC_USB0_MOCK_UTMI_CBCR 0x183E008
|
||||
#define GCC_USB0_PHY_CFG_AHB_CBCR 0x183E080
|
||||
#define GCC_USB0_AUX_CBCR 0x183E044
|
||||
#define GCC_USB0_PIPE_CBCR 0x183E040
|
||||
#define GCC_USB_SS_REF_CLK_EN 0x0183E07C
|
||||
#define GCC_USB_0_BOOT_CLOCK_CTL 0x1840000
|
||||
#define GCC_USB0_BCR 0x183E070
|
||||
#define GCC_QUSB2_0_PHY_BCR 0x184103C
|
||||
#define GCC_USB0_PHY_BCR 0x183E034
|
||||
#define GCC_USB3PHY_0_PHY_BCR 0x183E03C
|
||||
#define USB30_1_GENERAL_CFG 0x8AF8808
|
||||
#define USB30_1_GUCTL 0x8A0C12C
|
||||
#define USB30_PHY_1_QUSB2PHY_BASE 0x79000
|
||||
|
||||
#define GCC_USB1_GDSCR 0x183F078
|
||||
#define GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR 0x01847014
|
||||
#define GCC_USB1_MASTER_CBCR 0x183F000
|
||||
#define GCC_USB1_SLEEP_CBCR 0x183F004
|
||||
#define GCC_USB1_MOCK_UTMI_CFG_RCGR 0x183F024
|
||||
#define GCC_USB1_MOCK_UTMI_M 0x183F028
|
||||
#define GCC_USB1_MOCK_UTMI_N 0x0183F02C
|
||||
#define GCC_USB1_MOCK_UTMI_D 0x0183F030
|
||||
#define GCC_USB1_MOCK_UTMI_CMD_RCGR 0x183F020
|
||||
#define GCC_USB1_MOCK_UTMI_CBCR 0x183F008
|
||||
#define GCC_USB1_PHY_CFG_AHB_CBCR 0x183F080
|
||||
#define GCC_USB_1_BOOT_CLOCK_CTL 0x1841000
|
||||
#define GCC_USB1_BCR 0x183F070
|
||||
#define GCC_QUSB2_1_PHY_BCR 0x1841040
|
||||
#define USB30_PHY_2_QUSB2PHY_BASE 0x59000
|
||||
|
||||
#define USB30_PHY_1_USB3PHY_AHB2PHY_BASE 0x78000
|
||||
#define USB30_PHY_2_USB2PHY_AHB2PHY_BASE 0x58000
|
||||
|
||||
#define USB3_PHY_POWER_DOWN_CONTROL 0x804
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL 0xac
|
||||
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
|
||||
#define QSERDES_COM_CLK_SELECT 0x174
|
||||
#define QSERDES_COM_BG_TRIM 0x70
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x440
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
|
||||
#define QSERDES_COM_HSCLK_SEL 0x178
|
||||
#define QSERDES_COM_CMN_CONFIG 0x194
|
||||
#define QSERDES_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_COM_SYS_CLK_CTRL 0x3c
|
||||
#define QSERDES_COM_DEC_START_MODE0 0xd0
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xdc
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xe0
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xe4
|
||||
#define QSERDES_COM_CP_CTRL_MODE0 0x78
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE0 0x84
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE0 0x90
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE0 0x4c
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE0 0x50
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE0 0x54
|
||||
#define QSERDES_COM_CORE_CLK_EN 0x18c
|
||||
#define QSERDES_COM_LOCK_CMP_CFG 0xcc
|
||||
#define QSERDES_COM_VCO_TUNE_MAP 0x128
|
||||
#define QSERDES_COM_BG_TIMER 0x0c
|
||||
#define QSERDES_COM_SSC_EN_CENTER 0x10
|
||||
#define QSERDES_COM_SSC_PER1 0x1c
|
||||
#define QSERDES_COM_SSC_PER2 0x20
|
||||
#define QSERDES_COM_SSC_ADJ_PER1 0x14
|
||||
#define QSERDES_COM_SSC_ADJ_PER2 0x18
|
||||
#define QSERDES_COM_SSC_STEP_SIZE1 0x24
|
||||
#define QSERDES_COM_SSC_STEP_SIZE2 0x28
|
||||
#define QSERDES_RX_UCDR_SO_GAIN 0x410
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4d8
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4dc
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4e0
|
||||
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL 0x508
|
||||
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x50c
|
||||
#define QSERDES_RX_SIGDET_CNTRL 0x514
|
||||
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51c
|
||||
#define QSERDES_RX_SIGDET_ENABLES 0x510
|
||||
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D 0x268
|
||||
#define QSERDES_TX_RCV_DETECT_LVL_2 0x2ac
|
||||
#define QSERDES_TX_LANE_MODE 0x294
|
||||
#define PCS_TXDEEMPH_M6DB_V0 0x824
|
||||
#define PCS_TXDEEMPH_M3P5DB_V0 0x828
|
||||
#define PCS_FLL_CNTRL2 0x8c8
|
||||
#define PCS_FLL_CNTRL1 0x8c4
|
||||
#define PCS_FLL_CNT_VAL_L 0x8cc
|
||||
#define PCS_FLL_CNT_VAL_H_TOL 0x8d0
|
||||
#define PCS_FLL_MAN_CODE 0x8d4
|
||||
#define PCS_LOCK_DETECT_CONFIG1 0x880
|
||||
#define PCS_LOCK_DETECT_CONFIG2 0x884
|
||||
#define PCS_LOCK_DETECT_CONFIG3 0x888
|
||||
#define PCS_POWER_STATE_CONFIG2 0x864
|
||||
#define PCS_RXEQTRAINING_WAIT_TIME 0x8b8
|
||||
#define PCS_RXEQTRAINING_RUN_TIME 0x8bc
|
||||
#define PCS_LFPS_TX_ECSTART_EQTLOCK 0x8b0
|
||||
#define PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x8a0
|
||||
#define PCS_TSYNC_RSYNC_TIME 0x88c
|
||||
#define PCS_RCVR_DTCT_DLY_P1U2_L 0x870
|
||||
#define PCS_RCVR_DTCT_DLY_P1U2_H 0x874
|
||||
#define PCS_RCVR_DTCT_DLY_U3_L 0x878
|
||||
#define PCS_RCVR_DTCT_DLY_U3_H 0x87c
|
||||
#define PCS_RX_SIGDET_LVL 0x9d8
|
||||
#define USB3_PCS_TXDEEMPH_M6DB_V0 0x824
|
||||
#define USB3_PCS_TXDEEMPH_M3P5DB_V0 0x828
|
||||
#define QSERDES_RX_SIGDET_ENABLES 0x510
|
||||
#define USB3_PHY_START_CONTROL 0x808
|
||||
#define USB3_PHY_SW_RESET 0x800
|
||||
|
||||
struct smem_ram_ptn {
|
||||
char name[16];
|
||||
unsigned long long start;
|
||||
|
|
@ -120,6 +239,8 @@ extern const char *rsvd_node;
|
|||
extern const char *del_node[];
|
||||
extern const add_node_t add_fdt_node[];
|
||||
|
||||
int ipq_board_usb_init(void);
|
||||
|
||||
#define MSM_SDC1_BASE 0x7800000
|
||||
#define MSM_SDC1_SDHCI_BASE 0x7804000
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ CONFIG_CMD_FLASH=y
|
|||
# CONFIG_CMD_SF is not set
|
||||
# CONFIG_CMD_SPI is not set
|
||||
# CONFIG_CMD_I2C is not set
|
||||
# CONFIG_CMD_USB is not set
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_FPGA=y
|
||||
|
||||
#
|
||||
|
|
@ -256,7 +256,12 @@ CONFIG_REQUIRE_SERIAL_CONSOLE=y
|
|||
#
|
||||
# TPM support
|
||||
#
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
|
|
|
|||
|
|
@ -130,6 +130,25 @@ extern loff_t board_env_size;
|
|||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Block Device & Disk Partition Config
|
||||
*/
|
||||
#define HAVE_BLOCK_DEVICE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* USB Support
|
||||
*/
|
||||
#define CONFIG_USB_XHCI_IPQ
|
||||
#ifdef CONFIG_USB_XHCI_IPQ
|
||||
#define CONFIG_USB_XHCI
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SPI Flash Configs
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue