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board: qca: arm: ipq5332: Add support to reset two NAPA ports

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Change-Id: Ib98b60d0b57247598fdee41628202d68b24eec62
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
(cherry picked from commit 652bcba69b12ef8356b2c985274b58418c27f60d)
This commit is contained in:
Timple Raj M 2024-09-19 11:01:21 +05:30 • committed by Saahil Tomar
parent c8acb14709
commit d9d357c78b
3 changed files with 35 additions and 12 deletions
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1
arch/arm/dts/ipq5332-mi01.4.dts
View file

@ -172,6 +172,7 @@
qca808x_gpio = <51>; qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>; qca808x_gpio_cnt = <1>;
napa_gpio = <22>; napa_gpio = <22>;
napa_gpio_cnt = <1>;
qca8084_switch_enable = <1>; qca8084_switch_enable = <1>;
mdio_gpio { mdio_gpio {

1
arch/arm/dts/ipq5332-mi04.1.dts
View file

@ -173,6 +173,7 @@
qca808x_gpio = <51>; qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>; qca808x_gpio_cnt = <1>;
napa_gpio = <22>; napa_gpio = <22>;
napa_gpio_cnt = <1>;
qca8084_switch_enable = <1>; qca8084_switch_enable = <1>;
mdio_gpio { mdio_gpio {

45
board/qca/arm/ipq5332/ipq5332.c
View file

@ -1279,22 +1279,43 @@ void sfp_reset_init(void)
} }
} }
void qca8081_napa_reset(void) int get_napa_gpio(int napa_gpio[2])
{ {
unsigned int *napa_gpio_base; int napa_gpio_cnt = -1, node;
int node, gpio; int res = -1;
uint32_t cfg;
node = fdt_path_offset(gd->fdt_blob, "/ess-switch"); node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
if (node >= 0) { if (node >= 0) {
gpio = fdtdec_get_uint(gd->fdt_blob, node , "napa_gpio", -1); napa_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "napa_gpio_cnt", -1);
if (gpio != -1) { if (napa_gpio_cnt >= 1) {
napa_gpio_base = res = fdtdec_get_int_array(gd->fdt_blob, node, "napa_gpio",
(unsigned int *)GPIO_CONFIG_ADDR(gpio); (u32 *)napa_gpio, napa_gpio_cnt);
cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP; if (res >= 0)
writel(cfg, napa_gpio_base); return napa_gpio_cnt;
mdelay(100); }
gpio_set_value(gpio, 0x1); }
return res;
}
void qca8081_napa_reset(void)
{
int napa_gpio[2] = {-1, -1}, napa_gpio_cnt, i;
unsigned int *napa_gpio_base;
uint32_t cfg;
napa_gpio_cnt = get_napa_gpio(napa_gpio);
if (napa_gpio_cnt >= 1) {
for (i = 0; i < napa_gpio_cnt; i++) {
if (napa_gpio[i] >= 0) {
napa_gpio_base =
(unsigned int *)GPIO_CONFIG_ADDR(
napa_gpio[i]);
cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP;
writel(cfg, napa_gpio_base);
mdelay(100);
gpio_set_value(napa_gpio[i], 0x1);
}
} }
} }
} }