From d7f72cf927ac1fd330c34bf9dd5f0f65e52ff6f2 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Sun, 26 Apr 2020 16:24:02 +0530 Subject: [PATCH] ipq5018: Add PCIe clocks configuration Signed-off-by: Manikanta Mylavarapu Change-Id: I5ef7d1f6b447c4626992ad79e97608fbce9f01b2 --- board/qca/arm/ipq5018/ipq5018.c | 101 ++++++++++++++++++++++++++++++++ board/qca/arm/ipq5018/ipq5018.h | 21 ++++++- 2 files changed, 121 insertions(+), 1 deletion(-) diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index 75b9a02f98..8e9ce7b7af 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -851,6 +851,105 @@ int ipq_board_usb_init(void) #endif #ifdef CONFIG_PCI_IPQ +static void pcie_v2_clock_init(int id) +{ +#ifdef CONFIG_PCI + int cfg; + unsigned tmp; + void __iomem *base; + + /*single lane*/ + if (id == 0) { + base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; + /* Configure pcie1_aux_clk_src */ + cfg = (GCC_PCIE1_AUX_CFG_RCGR_SRC_SEL | + GCC_PCIE1_AUX_CFG_RCGR_SRC_DIV); + } else { /*double lane*/ + base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; + /* Configure pcie0_aux_clk_src */ + cfg = (GCC_PCIE0_AUX_CFG_RCGR_SRC_SEL | + GCC_PCIE0_AUX_CFG_RCGR_SRC_DIV); + } + + writel(cfg, base + PCIE_AUX_CFG_RCGR); + writel(CMD_UPDATE, base + PCIE_AUX_CMD_RCGR); + mdelay(100); + writel(ROOT_EN, base + PCIE_AUX_CMD_RCGR); + + if (id == 0) + /* Configure pcie1_axi_clk_src */ + cfg = (GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL | + GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV); + + else + /* Configure pcie0_axi_clk_src */ + cfg = (GCC_PCIE0_AXI_CFG_RCGR_SRC_SEL | + GCC_PCIE0_AXI_CFG_RCGR_SRC_DIV); + + writel(cfg, base + PCIE_AXI_CFG_RCGR); + writel(CMD_UPDATE, base + PCIE_AXI_CMD_RCGR); + mdelay(100); + writel(ROOT_EN, base + PCIE_AXI_CMD_RCGR); + + /* Configure CBCRs */ + if (id == 0) + writel(CLK_ENABLE, GCC_SYS_NOC_PCIE1_AXI_CBCR); + else + writel(CLK_ENABLE, GCC_SYS_NOC_PCIE0_AXI_CBCR); + + writel(CLK_ENABLE, base + PCIE_AHB_CBCR); + + tmp = readl(base + PCIE_AXI_M_CBCR); + tmp |= CLK_ENABLE; + writel(tmp, base + PCIE_AXI_M_CBCR); + + tmp = readl(base + PCIE_AXI_S_CBCR); + tmp |= CLK_ENABLE; + writel(tmp, base + PCIE_AXI_S_CBCR); + + writel(CLK_ENABLE, base + PCIE_AUX_CBCR); + + tmp = readl(base + PCIE_PIPE_CBCR); + tmp |= CLK_ENABLE; + writel(tmp, base + PCIE_PIPE_CBCR); + + writel(CLK_ENABLE, PCIE_AXI_S_BRIDGE_CBCR); +#endif + return; +} + +static void pcie_v2_clock_deinit(int id) +{ +#ifdef CONFIG_PCI + void __iomem *base; + + /*single lane*/ + if (id == 0) + base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; + else /*double lane*/ + base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; + + writel(0x0, base + PCIE_AUX_CFG_RCGR); + writel(0x0, base + PCIE_AUX_CMD_RCGR); + writel(0x0, base + PCIE_AXI_CFG_RCGR); + writel(0x0, base + PCIE_AXI_CMD_RCGR); + mdelay(100); + + if (id == 0) + writel(0x0, GCC_SYS_NOC_PCIE1_AXI_CBCR); + else + writel(0x0, GCC_SYS_NOC_PCIE0_AXI_CBCR); + + writel(0x0, base + PCIE_AHB_CBCR); + writel(0x0, base + PCIE_AXI_M_CBCR); + writel(0x0, base + PCIE_AXI_S_CBCR); + writel(0x0, base + PCIE_AUX_CBCR); + writel(0x0, base + PCIE_PIPE_CBCR); + writel(0x0, base + PCIE_AXI_S_BRIDGE_CBCR); +#endif + return; +} + void board_pci_init(int id) { int node, gpio_node; @@ -866,6 +965,7 @@ void board_pci_init(int id) if (gpio_node >= 0) qca_gpio_init(gpio_node); + pcie_v2_clock_init(id); return; } @@ -898,6 +998,7 @@ void board_pci_deinit() if (gpio_node >= 0) qca_gpio_deinit(gpio_node); + pcie_v2_clock_deinit(i); } return ; diff --git a/board/qca/arm/ipq5018/ipq5018.h b/board/qca/arm/ipq5018/ipq5018.h index bd9b1f5fe6..a617dfa551 100644 --- a/board/qca/arm/ipq5018/ipq5018.h +++ b/board/qca/arm/ipq5018/ipq5018.h @@ -227,7 +227,6 @@ #define CMD_UPDATE 0x1 #define ROOT_EN 0x2 -#define PIPE_CLK_ENABLE 0x4FF1 #define CLK_DISABLE 0x0 #define NOC_HANDSHAKE_FSM_EN (1 << 15) @@ -259,6 +258,11 @@ #define GCC_PCIE0_AXI_CMD_RCGR 0x01875050 #define GCC_PCIE0_AXI_CFG_RCGR 0x01875054 #define GCC_PCIE0_LINK_DOWN_BCR 0x018750A8 +#define GCC_PCIE0_AUX_CFG_RCGR_SRC_SEL (0 << 8) +#define GCC_PCIE0_AUX_CFG_RCGR_SRC_DIV 0x17 +#define GCC_PCIE0_AXI_CFG_RCGR_SRC_SEL (2 << 8) +#define GCC_PCIE0_AXI_CFG_RCGR_SRC_DIV 0x9 + #define GCC_PCIE1_BOOT_CLOCK_CTL 0x01876000 #define GCC_PCIE1_BCR 0x01876004 @@ -277,6 +281,21 @@ #define GCC_PCIE1_AXI_S_BRIDGE_CBCR 0x01876048 #define GCC_PCIE1_AXI_CMD_RCGR 0x01876050 #define GCC_PCIE1_AXI_CFG_RCGR 0x01876054 +#define GCC_PCIE1_AUX_CFG_RCGR_SRC_SEL (0 << 8) +#define GCC_PCIE1_AUX_CFG_RCGR_SRC_DIV 0x17 +#define GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL (1 << 8) +#define GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV 0x7 + +#define PCIE_AXI_M_CBCR 0x8 +#define PCIE_AXI_S_CBCR 0xC +#define PCIE_AHB_CBCR 0x10 +#define PCIE_AUX_CBCR 0x14 +#define PCIE_PIPE_CBCR 0x18 +#define PCIE_AUX_CMD_RCGR 0x20 +#define PCIE_AUX_CFG_RCGR 0x24 +#define PCIE_AXI_S_BRIDGE_CBCR 0x48 +#define PCIE_AXI_CMD_RCGR 0x50 +#define PCIE_AXI_CFG_RCGR 0x54 #define NOT_2D(two_d) (~two_d) #define NOT_N_MINUS_M(n,m) (~(n - m))