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driver: nand: qpic_nand: Fix proper clock source macro in set_clk_rate function.

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This change will fix proper clock source macro in set_clk_rate function.
Currently we are passing the wrong value to qpic_set_clk_rate for clock
source.

wrong:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, NAND_QSPI_MSTR_CONFIG);

The last argument should be clock source not register base address.

correct:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, GPLL0_CLK_SRC);

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ie9e07c253220924fd0c9287f7f0e2c5d42351128
This commit is contained in:
Md Sadre Alam 2020-12-07 10:58:36 +05:30
parent 1a756e2b23
commit d60219d19c
1 changed files with 1 additions and 1 deletions
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2
drivers/mtd/nand/qpic_nand.c
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@ -4515,7 +4515,7 @@ void qpic_nand_init(qpic_nand_cfg_t *qpic_nand_cfg)
qpic_reg_write_bam(NAND_QSPI_MSTR_CONFIG, qpic_reg_write_bam(NAND_QSPI_MSTR_CONFIG,
(FB_CLK_BIT | readl(NAND_QSPI_MSTR_CONFIG))); (FB_CLK_BIT | readl(NAND_QSPI_MSTR_CONFIG)));
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK,
NAND_QSPI_MSTR_CONFIG); GPLL0_CLK_SRC);
qpic_reg_write_bam(NAND_FLASH_SPI_CFG, 0x0); qpic_reg_write_bam(NAND_FLASH_SPI_CFG, 0x0);
qpic_reg_write_bam(NAND_FLASH_SPI_CFG, SPI_CFG_VAL); qpic_reg_write_bam(NAND_FLASH_SPI_CFG, SPI_CFG_VAL);
qpic_reg_write_bam(NAND_FLASH_SPI_CFG, qpic_reg_write_bam(NAND_FLASH_SPI_CFG,