diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b9fca6f548..0472c28e10 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -469,6 +469,14 @@ config ARCH_IPQ6018 select SYS_GENERIC_BOARD select QCA_COMMON +config ARCH_IPQ9048 + bool "QCA, IPQ9048" + select DM + select DM_SERIAL + select CPU_V7 + select SYS_GENERIC_BOARD + select QCA_COMMON + config ARCH_S5PC1XX bool "Samsung S5PC1XX" select CPU_V7 @@ -860,6 +868,7 @@ source "board/ipq40xx/Kconfig" source "board/ipq5018/Kconfig" source "board/ipq6018/Kconfig" source "board/ipq806x/Kconfig" +source "board/ipq9048/Kconfig" source "board/ipq807x/Kconfig" source "board/isee/igep0033/Kconfig" source "board/maxbcm/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e5d500ddcf..1da6d75a60 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -94,6 +94,8 @@ dtb-$(CONFIG_ARCH_IPQ6018) += ipq6018-cp01-c1.dtb \ ipq6018-db-cp01.dtb \ ipq6018-db-cp02.dtb +dtb-$(CONFIG_ARCH_IPQ9048) += ipq9048-emulation.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ rk3288-jerry.dtb \ diff --git a/arch/arm/dts/ipq9048-emulation.dts b/arch/arm/dts/ipq9048-emulation.dts new file mode 100644 index 0000000000..b71436e11b --- /dev/null +++ b/arch/arm/dts/ipq9048-emulation.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "ipq9048-soc.dtsi" +/ { + model ="QCA, IPQ9048-EMULATION"; + compatible = "qca,ipq9048", "qca,ipq9048-emulation"; + machid = <0xf030000>; + + aliases { + console = "/serial@78AF000"; + }; +}; diff --git a/arch/arm/dts/ipq9048-soc.dtsi b/arch/arm/dts/ipq9048-soc.dtsi new file mode 100644 index 0000000000..fcf6778663 --- /dev/null +++ b/arch/arm/dts/ipq9048-soc.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton.dtsi" +#include + +/ { + + serial@78AF000 { + compatible = "qca,ipq-uartdm"; + reg = <0x78AF000 0x200>; + id = <2>; + bit_rate = <0xff>; + status = "ok"; + m_value = <36>; + n_value = <15625>; + d_value = <15625>; + serial_gpio { + gpio1 { + gpio = <13>; + func = <2>; + pull = ; + drvstr = ; + oe = ; + }; + + gpio2 { + gpio = <14>; + func = <2>; + pull = ; + drvstr = ; + oe = ; + }; + }; + }; + + timer { + gcnt_cntcv_lo = <0x4a2000>; + gcnt_cntcv_hi = <0x4a2004>; + gpt_freq_hz = <24000000>; + timer_load_val = <0x00FFFFFF 0xFFFFFFFF>; + }; +}; + diff --git a/arch/arm/include/asm/arch-ipq9048/clk.h b/arch/arm/include/asm/arch-ipq9048/clk.h new file mode 100644 index 0000000000..72ee243d02 --- /dev/null +++ b/arch/arm/include/asm/arch-ipq9048/clk.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IPQ9048_CLK_H +#define IPQ9048_CLK_H + +#include + +#define GCC_BLSP1_UART1_BCR 0x1802028 +#define GCC_BLSP1_UART2_BCR 0x1803028 +#define GCC_BLSP1_UART3_BCR 0x1804028 +#define GCC_BLSP1_UART4_BCR 0x1805028 +#define GCC_BLSP1_UART5_BCR 0x1806028 +#define GCC_BLSP1_UART6_BCR 0x1807028 + +#define GCC_BLSP1_UART_BCR(id) ((id < 1) ? \ + (GCC_BLSP1_UART1_BCR):\ + (GCC_BLSP1_UART1_BCR + (0x1000 * id))) + +#define GCC_BLSP1_UART_APPS_CMD_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x04) +#define GCC_BLSP1_UART_APPS_CFG_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x08) +#define GCC_BLSP1_UART_APPS_M(id) (GCC_BLSP1_UART_BCR(id) + 0x0c) +#define GCC_BLSP1_UART_APPS_N(id) (GCC_BLSP1_UART_BCR(id) + 0x10) +#define GCC_BLSP1_UART_APPS_D(id) (GCC_BLSP1_UART_BCR(id) + 0x14) +#define GCC_BLSP1_UART_APPS_CBCR(id) (GCC_BLSP1_UART_BCR(id) + 0x18) + +#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000 +#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700 +#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F + +#define GCC_UART_CFG_RCGR_MODE_SHIFT 12 +#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8 +#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0 + +#define UART_RCGR_SRC_SEL 0x1 +#define UART_RCGR_SRC_DIV 0x0 +#define UART_RCGR_MODE 0x2 +#define UART_CMD_RCGR_UPDATE 0x1 +#define UART_CBCR_CLK_ENABLE 0x1 + +#define NOT_2D(two_d) (~two_d) +#define NOT_N_MINUS_M(n,m) (~(n - m)) +#define CLOCK_UPDATE_TIMEOUT_US 1000 + +int uart_clock_config(struct ipq_serial_platdata *plat); + +#endif /*IPQ9048_CLK_H*/ diff --git a/arch/arm/include/asm/arch-qca-common/qca_common.h b/arch/arm/include/asm/arch-qca-common/qca_common.h index c3bd9e2f8f..683c275b48 100644 --- a/arch/arm/include/asm/arch-qca-common/qca_common.h +++ b/arch/arm/include/asm/arch-qca-common/qca_common.h @@ -25,6 +25,10 @@ #include #endif +#ifdef CONFIG_ARCH_IPQ9048 +#include +#endif + #ifdef CONFIG_ARCH_IPQ807x #include #endif diff --git a/arch/arm/include/asm/arch-qca-common/qpic_nand.h b/arch/arm/include/asm/arch-qca-common/qpic_nand.h index 72e97d433b..9c33c96bae 100644 --- a/arch/arm/include/asm/arch-qca-common/qpic_nand.h +++ b/arch/arm/include/asm/arch-qca-common/qpic_nand.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2008, Google Inc. * All rights reserved. - * Copyright (c) 2009-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2020 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,7 +31,8 @@ #define __QPIC_NAND_H #if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI) \ - || defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ5018) + || defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ5018) \ + || defined(CONFIG_IPQ9048) #define QPIC_EBI2ND_BASE (0x079b0000) #else #error "QPIC NAND not supported" diff --git a/board/ipq9048/Kconfig b/board/ipq9048/Kconfig new file mode 100644 index 0000000000..14bb3b3e43 --- /dev/null +++ b/board/ipq9048/Kconfig @@ -0,0 +1,15 @@ +if ARCH_IPQ9048 + +config SYS_CPU + default "ipq9048" + +config SYS_BOARD + default "ipq9048" + +config SYS_VENDOR + default "qca/arm" + +config SYS_CONFIG_NAME + default "ipq9048" + +endif diff --git a/board/qca/arm/common/board_init.c b/board/qca/arm/common/board_init.c index 5410f71fe4..bc6ca15f66 100644 --- a/board/qca/arm/common/board_init.c +++ b/board/qca/arm/common/board_init.c @@ -92,8 +92,10 @@ __weak void sdi_disable(void) int board_init(void) { int ret; +#ifndef CONFIG_IPQ9048 uint32_t start_blocks; uint32_t size_blocks; +#endif #ifdef CONFIG_IPQ_REPORT_L2ERR u32 l2esr; diff --git a/board/qca/arm/ipq9048/Makefile b/board/qca/arm/ipq9048/Makefile new file mode 100644 index 0000000000..5b4984518d --- /dev/null +++ b/board/qca/arm/ipq9048/Makefile @@ -0,0 +1,5 @@ +ccflags-y += -I$(srctree)/board/qca/arm/ipq9048 +cppflags-y += -I$(srctree)/board/qca/arm/ipq9048 +obj-y := ipq9048.o +obj-y += clock.o + diff --git a/board/qca/arm/ipq9048/clock.c b/board/qca/arm/ipq9048/clock.c new file mode 100644 index 0000000000..dcaf3fa86c --- /dev/null +++ b/board/qca/arm/ipq9048/clock.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static void uart_configure_mux(u8 id) +{ + unsigned long cfg_rcgr; + + cfg_rcgr = readl(GCC_BLSP1_UART_APPS_CFG_RCGR(id)); + /* Clear mode, src sel, src div */ + cfg_rcgr &= ~(GCC_UART_CFG_RCGR_MODE_MASK | + GCC_UART_CFG_RCGR_SRCSEL_MASK | + GCC_UART_CFG_RCGR_SRCDIV_MASK); + + cfg_rcgr |= ((UART_RCGR_SRC_SEL << GCC_UART_CFG_RCGR_SRCSEL_SHIFT) + & GCC_UART_CFG_RCGR_SRCSEL_MASK); + + cfg_rcgr |= ((UART_RCGR_SRC_DIV << GCC_UART_CFG_RCGR_SRCDIV_SHIFT) + & GCC_UART_CFG_RCGR_SRCDIV_MASK); + + cfg_rcgr |= ((UART_RCGR_MODE << GCC_UART_CFG_RCGR_MODE_SHIFT) + & GCC_UART_CFG_RCGR_MODE_MASK); + + writel(cfg_rcgr, GCC_BLSP1_UART_APPS_CFG_RCGR(id)); +} + +static int uart_trigger_update(u8 id) +{ + unsigned long cmd_rcgr; + int timeout = 0; + + cmd_rcgr = readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id)); + cmd_rcgr |= UART_CMD_RCGR_UPDATE; + writel(cmd_rcgr, GCC_BLSP1_UART_APPS_CMD_RCGR(id)); + + while (readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id)) & UART_CMD_RCGR_UPDATE) { + if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) { + printf("Timeout waiting for UART clock update\n"); + return -ETIMEDOUT; + } + udelay(1); + } + return 0; +} + +int uart_clock_config(struct ipq_serial_platdata *plat) +{ + unsigned long cbcr_val; + int ret; + + uart_configure_mux(plat->port_id); + + writel(plat->m_value, GCC_BLSP1_UART_APPS_M(plat->port_id)); + writel(NOT_N_MINUS_M(plat->n_value, plat->m_value), + GCC_BLSP1_UART_APPS_N(plat->port_id)); + writel(NOT_2D(plat->d_value), GCC_BLSP1_UART_APPS_D(plat->port_id)); + + ret = uart_trigger_update(plat->port_id); + if (ret) + return ret; + + cbcr_val = readl(GCC_BLSP1_UART_APPS_CBCR(plat->port_id)); + cbcr_val |= UART_CBCR_CLK_ENABLE; + writel(cbcr_val, GCC_BLSP1_UART_APPS_CBCR(plat->port_id)); + return 0; +} + diff --git a/board/qca/arm/ipq9048/ipq9048.c b/board/qca/arm/ipq9048/ipq9048.c new file mode 100644 index 0000000000..13e777e792 --- /dev/null +++ b/board/qca/arm/ipq9048/ipq9048.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void qca_serial_init(struct ipq_serial_platdata *plat) +{ + int ret; + + if (plat->gpio_node < 0) { + printf("serial_init: unable to find gpio node\n"); + return; + } + + qca_gpio_init(plat->gpio_node); + plat->port_id = UART_PORT_ID(plat->reg_base); + ret = uart_clock_config(plat); + if (ret) + printf("UART clock config failed %d\n", ret); + + return; +} + +void reset_crashdump(void) +{ + return; +} + +void board_nand_init(void) +{ + return; +} +void enable_caches(void) +{ + icache_enable(); +} + +void disable_caches(void) +{ + icache_disable(); +} + +/** + * Set the uuid in bootargs variable for mounting rootfilesystem + */ +int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_flag) +{ + return 0; +} + +unsigned long timer_read_counter(void) +{ + return 0; +} + +void reset_cpu(unsigned long a) +{ + while (1); +} + +void reset_board(void) +{ + run_command("reset", 0); +} + +void set_flash_secondary_type(qca_smem_flash_info_t *smem) +{ + return; +}; + diff --git a/board/qca/arm/ipq9048/ipq9048.h b/board/qca/arm/ipq9048/ipq9048.h new file mode 100644 index 0000000000..14c08a51d5 --- /dev/null +++ b/board/qca/arm/ipq9048/ipq9048.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _IPQ9048_CDP_H_ +#define _IPQ9048_CDP_H_ + +#include +#include +#include + +#define BLSP1_UART0_BASE 0x078AF000 +#define UART_PORT_ID(reg) ((reg - BLSP1_UART0_BASE) / 0x1000) + +#define CLOCK_UPDATE_TIMEOUT_US 1000 + +#define KERNEL_AUTH_CMD 0x13 +#define SCM_CMD_SEC_AUTH 0x1F + +struct smem_ram_ptn { + char name[16]; + unsigned long long start; + unsigned long long size; + + /* RAM Partition attribute: READ_ONLY, READWRITE etc. */ + unsigned attr; + + /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */ + unsigned category; + + /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */ + unsigned domain; + + /* RAM Partition type: system, bootloader, appsboot, apps etc. */ + unsigned type; + + /* reserved for future expansion without changing version number */ + unsigned reserved2, reserved3, reserved4, reserved5; +} __attribute__ ((__packed__)); + +__weak void aquantia_phy_reset_init_done(void) {} +__weak void aquantia_phy_reset_init(void) {} + +struct smem_ram_ptable { +#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8 +#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2 + unsigned magic[2]; + unsigned version; + unsigned reserved1; + unsigned len; + unsigned buf; + struct smem_ram_ptn parts[32]; +} __attribute__ ((__packed__)); + +int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable); +void reset_crashdump(void); +void reset_board(void); + +typedef enum { + SMEM_SPINLOCK_ARRAY = 7, + SMEM_AARM_PARTITION_TABLE = 9, + SMEM_HW_SW_BUILD_ID = 137, + SMEM_USABLE_RAM_PARTITION_TABLE = 402, + SMEM_POWER_ON_STATUS_INFO = 403, + SMEM_MACHID_INFO_LOCATION = 425, + SMEM_IMAGE_VERSION_TABLE = 469, + SMEM_BOOT_FLASH_TYPE = 498, + SMEM_BOOT_FLASH_INDEX = 499, + SMEM_BOOT_FLASH_CHIP_SELECT = 500, + SMEM_BOOT_FLASH_BLOCK_SIZE = 501, + SMEM_BOOT_FLASH_DENSITY = 502, + SMEM_BOOT_DUALPARTINFO = 503, + SMEM_PARTITION_TABLE_OFFSET = 504, + SMEM_SPI_FLASH_ADDR_LEN = 505, + SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY, + SMEM_LAST_VALID_TYPE = SMEM_SPI_FLASH_ADDR_LEN, + SMEM_MAX_SIZE = SMEM_SPI_FLASH_ADDR_LEN + 1, +} smem_mem_type_t; + +__weak void qgic_init(void) {} +__weak void handle_noc_err(void) {} +#endif /* _IPQ9048_CDP_H_ */ diff --git a/configs/ipq9048_defconfig b/configs/ipq9048_defconfig new file mode 100644 index 0000000000..52aa32b223 --- /dev/null +++ b/configs/ipq9048_defconfig @@ -0,0 +1,301 @@ +CONFIG_ARM=y +CONFIG_HAS_VBAR=y +CONFIG_CPU_V7=y +CONFIG_ARCH_IPQ9048=y +CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_MALLOC_F=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EXPERT=y +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_FIT_SIGNATURE is not set +CONFIG_SYS_EXTRA_OPTIONS="" +CONFIG_SYS_PROMPT="IPQ9048# " + +# +# Commands +# + +# +# Info commands +# +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y + +# +# Boot commands +# +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_GO=y +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set + +# +# Environment commands +# +CONFIG_CMD_EXPORTENV=y +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ENV_EXISTS=y + +# +# Memory commands +# +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CRC32=y +# CONFIG_LOOPW is not set +# CONFIG_CMD_MEMTEST is not set +# CONFIG_CMD_MX_CYCLIC is not set +# CONFIG_CMD_MEMINFO is not set + +# +# Device access commands +# +CONFIG_CMD_DM=y +# CONFIG_CMD_DEMO is not set +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +# CONFIG_CMD_NAND is not set +# CONFIG_CMD_SF is not set +# CONFIG_CMD_SPI is not set +# CONFIG_CMD_I2C is not set +# CONFIG_CMD_USB is not set +CONFIG_CMD_FPGA=y + +# +# Shell scripting commands +# +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_SETEXPR=y + +# +# Network commands +# +CONFIG_CMD_NET=y +# CONFIG_CMD_TFTPPUT is not set +# CONFIG_CMD_TFTPSRV is not set +# CONFIG_CMD_RARP is not set +# CONFIG_CMD_DHCP is not set +CONFIG_CMD_NFS=y +# CONFIG_CMD_PING is not set +# CONFIG_CMD_CDP is not set +# CONFIG_CMD_SNTP is not set +# CONFIG_CMD_DNS is not set +# CONFIG_CMD_LINK_LOCAL is not set + +# +# Misc commands +# +# CONFIG_CMD_TIME is not set +CONFIG_CMD_MISC=y +# CONFIG_CMD_TIMER is not set + +# +# Boot timing +# +# CONFIG_BOOTSTAGE is not set +CONFIG_BOOTSTAGE_USER_COUNT=20 +CONFIG_BOOTSTAGE_STASH_ADDR=0 +CONFIG_BOOTSTAGE_STASH_SIZE=4096 + +# +# Power commands +# + +# +# Security commands +# +CONFIG_SUPPORT_OF_CONTROL=y + +# +# Device Tree Control +# +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +# CONFIG_OF_EMBED is not set +CONFIG_NET=y +# CONFIG_NET_RANDOM_ETHADDR is not set +# CONFIG_NETCONSOLE is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_DM=y +CONFIG_DM_WARN=y +CONFIG_DM_DEVICE_REMOVE=y +CONFIG_DM_STDIO=y +CONFIG_DM_SEQ_ALIAS=y +# CONFIG_REGMAP is not set +# CONFIG_DEVRES is not set +CONFIG_SIMPLE_BUS=y +# CONFIG_CLK is not set +# CONFIG_CPU is not set + +# +# Hardware crypto devices +# +# CONFIG_FSL_CAAM is not set + +# +# Demo for driver model +# +# CONFIG_DM_DEMO is not set + +# +# DFU support +# +# CONFIG_DFU_TFTP is not set + +# +# GPIO Support +# +# CONFIG_LPC32XX_GPIO is not set +# CONFIG_VYBRID_GPIO is not set + +# +# I2C support +# +# CONFIG_DM_I2C_COMPAT is not set +# CONFIG_CROS_EC_KEYB is not set + +# +# LED Support +# +# CONFIG_LED is not set + +# +# Multifunction device drivers +# +# CONFIG_CROS_EC is not set +# CONFIG_FSL_SEC_MON is not set +# CONFIG_PCA9551_LED is not set +# CONFIG_RESET is not set + +# +# MMC Host controller Support +# +# CONFIG_DM_MMC is not set + +# +# NAND Device Support +# +# CONFIG_NAND_DENALI is not set +# CONFIG_NAND_VF610_NFC is not set +# CONFIG_NAND_PXA3XX is not set + +# +# Generic NAND options +# + +# +# SPI Flash Support +# +# CONFIG_SPI_FLASH is not set +# CONFIG_DM_ETH is not set +# CONFIG_PHYLIB is not set +# CONFIG_NETDEVICES is not set + +# +# PCI +# +# CONFIG_DM_PCI is not set + +# +# Pin controllers +# +# CONFIG_PINCTRL is not set + +# +# Power +# +# CONFIG_DM_PMIC is not set +# CONFIG_DM_REGULATOR is not set +# CONFIG_RAM is not set + +# +# Real Time Clock +# +# CONFIG_DM_RTC is not set + +# +# Serial drivers +# +CONFIG_REQUIRE_SERIAL_CONSOLE=y +# CONFIG_DEBUG_UART is not set + +# +# Sound support +# +# CONFIG_SOUND is not set + +# +# SPI Support +# +# CONFIG_FSL_ESPI is not set +# CONFIG_TI_QSPI is not set +# CONFIG_DM_THERMAL is not set + +# +# TPM support +# +# CONFIG_USB is not set + +# +# Graphics support +# +# CONFIG_VIDEO_VESA is not set +# CONFIG_VIDEO_LCD_ANX9804 is not set +# CONFIG_VIDEO_LCD_SSD2828 is not set +# CONFIG_DISPLAY_PORT is not set +# CONFIG_VIDEO_TEGRA124 is not set +# CONFIG_VIDEO_BRIDGE is not set +# CONFIG_PHYS_TO_BUS is not set + +# +# File systems +# + +# +# Library routines +# +# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set +CONFIG_HAVE_PRIVATE_LIBGCC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_HZ=1000 +# CONFIG_SYS_VSNPRINTF is not set +CONFIG_REGEX=y +# CONFIG_LIB_RAND is not set +# CONFIG_CMD_DHRYSTONE is not set +# CONFIG_RSA is not set +# CONFIG_TPM is not set + +# +# Hashing Support +# +# CONFIG_SHA1 is not set +# CONFIG_SHA256 is not set +# CONFIG_SHA_HW_ACCEL is not set + +# +# Compression Support +# +# CONFIG_LZ4 is not set +# CONFIG_ERRNO_STR is not set +# CONFIG_UNIT_TEST is not set + diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c8a3465721..0bc09124eb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_IPQ806x) += ipq_gpio.o obj-$(CONFIG_ARCH_IPQ40xx) += ipq_gpio.o obj-$(CONFIG_ARCH_IPQ5018) += ipq_gpio.o obj-$(CONFIG_ARCH_IPQ6018) += ipq_gpio.o +obj-$(CONFIG_ARCH_IPQ9048) += ipq_gpio.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0913e80b08..84516cab17 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_IPQ806x) += qca_uart.o obj-$(CONFIG_ARCH_IPQ40xx) += qca_uart.o obj-$(CONFIG_ARCH_IPQ5018) += qca_uart.o obj-$(CONFIG_ARCH_IPQ6018) += qca_uart.o +obj-$(CONFIG_ARCH_IPQ9048) += qca_uart.o ifdef CONFIG_DM_SERIAL obj-y += serial-uclass.o obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o diff --git a/include/common.h b/include/common.h index 0fe5ffc595..c707d113f9 100644 --- a/include/common.h +++ b/include/common.h @@ -41,6 +41,9 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_IPQ6018) #include <../board/qca/arm/ipq6018/ipq6018.h> +#elif defined(CONFIG_IPQ9048) +#include <../board/qca/arm/ipq9048/ipq9048.h> + #elif defined(CONFIG_IPQ_RUMI) #include <../board/qca/arm/ipq807x/ipq807x.h> #endif @@ -413,7 +416,7 @@ ulong getenv_hex(const char *varname, ulong default_val); * Return -1 if variable does not exist (default to true) */ int getenv_yesno(const char *var); -#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ5018_ENV) || defined(CONFIG_IPQ6018_ENV) +#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ5018_ENV) || defined(CONFIG_IPQ6018_ENV) || defined(CONFIG_IPQ9048_ENV) extern int (*saveenv)(void); #else int saveenv (void); diff --git a/include/configs/ipq9048.h b/include/configs/ipq9048.h new file mode 100644 index 0000000000..763a078ef3 --- /dev/null +++ b/include/configs/ipq9048.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2016-2018,2020 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _IPQ9048_H +#define _IPQ9048_H + +#ifndef DO_DEPS_ONLY +#include +#endif + +#define CONFIG_IPQ9048 + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_IPQ_NO_RELOC + +#define CONFIG_IPQ9048_UART +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +/* +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE_MAX (256 << 10) // 256 KB +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (256 << 10)) +*/ + +#define CONFIG_ENV_IS_NOWHERE 1 +/* + * Size of malloc() pool + */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */ + +/* + + svc_sp --> -------------- + irq_sp --> | | + fiq_sp --> | | + bd --> | | + gd --> | | + pgt --> | | + malloc --> | | + text_base --> |------------| +*/ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\ + CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\ + GENERATED_BD_INFO_SIZE) + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define TLMM_BASE 0x01000000 +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000) +#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x4A900000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20)) + +#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE +#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE +#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100) + +#define CONFIG_OF_COMBINE 1 + +#define CONFIG_QCA_SMEM_BASE 0x4AB00000 + +#define CONFIG_IPQ_FDT_HIGH 0x4A400000 +#define CONFIG_IPQ_NO_MACS 6 +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +/* + * IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region. + * CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting + * address of WLAN Area. + * TFTP file can only be written in Linux HLOS region and WLAN AREA. + */ +#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20)) +#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21)) +#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size) + +#ifndef __ASSEMBLY__ +#include +extern loff_t board_env_offset; +extern loff_t board_env_range; +extern loff_t board_env_size; +#endif + +#define CONFIG_IPQ9048_ENV 1 +#define CONFIG_ENV_OFFSET board_env_offset +#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX +#define CONFIG_ENV_RANGE board_env_range +#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10)) + +#define CONFIG_ENV_IS_IN_NAND 1 + +/* + * NAND Flash Configs + */ + +/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode + * CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode. + * BAM is enabled by default. + */ +#define CONFIG_QPIC_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_YAFFS +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* + * Expose SPI driver as a pseudo NAND driver to make use + * of U-Boot's MTD framework. + */ +#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \ + CONFIG_IPQ_MAX_SPI_DEVICE + +#define CONFIG_IPQ_MAX_NAND_DEVICE 1 +#define CONFIG_IPQ_MAX_SPI_DEVICE 1 + +#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0 +#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1 + +#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX +#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX + +#define QCA_SPI_NOR_DEVICE "spi0.0" +#define CONFIG_QUP_SPI_USE_DMA 1 + +/* + * U-Boot Env Configs + */ +#define CONFIG_OF_LIBFDT 1 + +/* NSS firmware loaded using bootm */ +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8" +#define QCA_ROOT_FS_PART_NAME "rootfs" + +#define CONFIG_BOOTDELAY 2 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define NUM_ALT_PARTITION 16 + +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE + +#define CONFIG_CMD_BOOTZ + +/* + * Below Configs need to be updated after enabling reset_crashdump + * Included now to avoid build failure + */ +#define SET_MAGIC 0x1 +#define CLEAR_MAGIC 0x0 +#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9 +#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10 +#define SCM_CMD_TZ_PSHOLD 0x15 +/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes + * Cache flush and invalidation based on L1 cache, so the cache line + * size is configured to 64 */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +/*#define CONFIG_SYS_DCACHE_OFF*/ + +/* Enabling this flag will report any L2 errors. + * By default we are disabling it */ +/*#define CONFIG_IPQ_REPORT_L2ERR*/ + +#endif /* _IPQ9048_H */ + diff --git a/include/dt-bindings/qcom/gpio-ipq9048.h b/include/dt-bindings/qcom/gpio-ipq9048.h new file mode 100644 index 0000000000..e595b44e69 --- /dev/null +++ b/include/dt-bindings/qcom/gpio-ipq9048.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016-2018,2020 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IPQ9048_GPIO_H__ +#define __DT_BINDINGS_IPQ9048_GPIO_H__ + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Output value */ +#define GPIO_OUT_LOW 0 +#define GPIO_OUT_HIGH 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_OE_DISABLE 0 +#define GPIO_OE_ENABLE 1 + +/* GPIO VM */ +#define GPIO_VM_ENABLE 1 +#define GPIO_VM_DISABLE 0 + +/* GPIO OD */ +#define GPIO_OD_ENABLE 1 +#define GPIO_OD_DISABLE 0 + +/* GPIO PULLUP RES */ +#define GPIO_PULL_RES0 0 +#define GPIO_PULL_RES1 1 +#define GPIO_PULL_RES2 2 +#define GPIO_PULL_RES3 3 + +#endif