diff --git a/drivers/net/ipq_common/ipq_qca8084.c b/drivers/net/ipq_common/ipq_qca8084.c
index 8f0c12a98e..6f223b1166 100644
--- a/drivers/net/ipq_common/ipq_qca8084.c
+++ b/drivers/net/ipq_common/ipq_qca8084.c
@@ -1389,7 +1389,7 @@ int ipq_qca8084_hw_init(phy_info_t * phy_info[])
 	int ret = 0;
 	int mode0 = -1, mode1 = -1, node = -1;
 	qca8084_work_mode_t work_mode;
-	u32 port_bmp = 0x3e, cpu_bmp = 0x1;
+	u32 port_bmp, cpu_bmp;
 
 	int chip_type = chip_ver_get();
 
@@ -1411,6 +1411,10 @@ int ipq_qca8084_hw_init(phy_info_t * phy_info[])
 		return mode1;
 	}
 
+	port_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_lan_bmp", 0x3e);
+
+	cpu_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_cpu_bmp", 0x1);
+
 	ipq_qca8084_switch_reset();
 
 	ret = ipq_qca8084_work_mode_init(mode0, mode1);
diff --git a/drivers/net/ipq_common/ipq_qca8084_clk.c b/drivers/net/ipq_common/ipq_qca8084_clk.c
index 36ef2a44f2..b11df733d6 100644
--- a/drivers/net/ipq_common/ipq_qca8084_clk.c
+++ b/drivers/net/ipq_common/ipq_qca8084_clk.c
@@ -1220,7 +1220,6 @@ void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp)
 	uint32_t qca8084_port_id = 0;
 	/* clock type mask value for 6 manhattan ports */
 	uint8_t clk_mask[PORT5 + 1] = {0};
-	static uint8_t gcc_common_clk_init = 0;
 	uint8_t switch_flag = 0;
 	qca8084_clk_parent_t uniphy_index = QCA8084_P_UNIPHY0_RX;
 
@@ -1267,22 +1266,19 @@ void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp)
 			return;
 	}
 
-	if (!gcc_common_clk_init) {
-		qca8084_gcc_common_clk_parent_enable(clk_mode);
-		gcc_common_clk_init = 1;
+	qca8084_gcc_common_clk_parent_enable(clk_mode);
 
-		/* Initialize the uniphy raw clock, if the port4 is in bypass mode, the uniphy0
-		 * raw clock need to be dynamically updated between UQXGMII_SPEED_2500M_CLK and
-		 * UQXGMII_SPEED_1000M_CLK according to the realtime link speed.
-		 */
-		uniphy_index = QCA8084_P_UNIPHY0_RX;
-		while (uniphy_index <= QCA8084_P_UNIPHY1_TX) {
-			/* the uniphy raw clock may be already initialized. */
-			if (0 == qca8084_uniphy_raw_clock_get(uniphy_index))
-				qca8084_uniphy_raw_clock_set(uniphy_index,
-						UQXGMII_SPEED_2500M_CLK);
-			uniphy_index++;
-		}
+	/* Initialize the uniphy raw clock, if the port4 is in bypass mode, the uniphy0
+	 * raw clock need to be dynamically updated between UQXGMII_SPEED_2500M_CLK and
+	 * UQXGMII_SPEED_1000M_CLK according to the realtime link speed.
+	 */
+	uniphy_index = QCA8084_P_UNIPHY0_RX;
+	while (uniphy_index <= QCA8084_P_UNIPHY1_TX) {
+		/* the uniphy raw clock may be already initialized. */
+		if (0 == qca8084_uniphy_raw_clock_get(uniphy_index))
+			qca8084_uniphy_raw_clock_set(uniphy_index,
+					UQXGMII_SPEED_2500M_CLK);
+		uniphy_index++;
 	}
 
 	qca8084_port_id = 0;