mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
Merge "driver: net: devsoc: removed the extra ports and uniphy"
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commit
c4a471eeb6
3 changed files with 130 additions and 395 deletions
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@ -877,8 +877,7 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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int clk[4] = {0};
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int phy_addr = -1, node = -1;
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int aquantia_port[2] = {-1, -1}, aquantia_port_cnt = -1;
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int sfp_port[2] = {-1, -1}, sfp_port_cnt = -1;
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int sgmii_mode = -1, sfp_mode = -1, sgmii_fiber = -1;
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int sgmii_mode = -1;
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int phy_node = -1, res = -1;
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node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
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@ -892,15 +891,6 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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if (res < 0)
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printf("Error: Aquantia port details not provided in DT\n");
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}
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sfp_port_cnt = fdtdec_get_uint(gd->fdt_blob, node, "sfp_port_cnt", -1);
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if (sfp_port_cnt >= 1) {
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res = fdtdec_get_int_array(gd->fdt_blob, node, "sfp_port",
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(u32 *)sfp_port, sfp_port_cnt);
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if (res < 0)
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printf("Error: SFP port details not provided in DT\n");
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}
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}
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phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
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@ -912,71 +902,33 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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*/
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for (i = 0; i < DEVSOC_PHY_MAX; i++) {
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#ifndef CONFIG_DEVSOC_RUMI
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if (i == sfp_port[0] || i == sfp_port[1]) {
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status = phy_status_get_from_ppe(i);
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duplex = FAL_FULL_DUPLEX;
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/* SFP Port can be enabled in USXGMII0 or USXGMII1 i.e
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* SFP Port can be port5 or port6 (with port id - 4 or 5).
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* Port5 (port id - 4) -> Serdes1
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* Port6 (port id - 5) -> Serdes2
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*/
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if (i == 4) {
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sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode1", -1);
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if (sfp_mode < 0) {
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printf("Error: switch_mac_mode1 not specified in dts\n");
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return sfp_mode;
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}
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} else if (i == 5) {
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sfp_mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode2", -1);
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if (sfp_mode < 0) {
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printf("Error: switch_mac_mode2 not specified in dts\n");
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return sfp_mode;
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}
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} else {
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printf("Error: SFP Port can be enabled in USXGMII0 or USXGMII1 (Port5 or Port6) only in devsoc platform\n");
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}
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if (sfp_mode == EPORT_WRAPPER_SGMII_FIBER) {
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sgmii_fiber = 1;
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curr_speed[i] = FAL_SPEED_1000;
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} else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) {
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sgmii_fiber = 0;
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curr_speed[i] = FAL_SPEED_10000;
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} else if (sfp_mode == EPORT_WRAPPER_SGMII_PLUS) {
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sgmii_fiber = 0;
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curr_speed[i] = FAL_SPEED_2500;
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} else {
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printf("Error: Wrong mode specified for SFP Port in DT\n");
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return sfp_mode;
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}
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} else {
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if (!priv->ops[i]) {
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printf("Phy ops not mapped\n");
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continue;
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}
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phy_get_ops = priv->ops[i];
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if (!phy_get_ops->phy_get_link_status ||
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!phy_get_ops->phy_get_speed ||
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!phy_get_ops->phy_get_duplex) {
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printf("Error:Link status/Get speed/Get duplex not mapped\n");
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return -1;
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}
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if (phy_node >= 0) {
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/*
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* For each ethernet port, one node should be added
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* inside port_phyinfo with appropriate phy address
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*/
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phy_addr = phy_info[i]->phy_address;
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} else {
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printf("Error:Phy addresses not configured in DT\n");
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return -1;
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}
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status = phy_get_ops->phy_get_link_status(priv->mac_unit, phy_addr);
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phy_get_ops->phy_get_speed(priv->mac_unit, phy_addr, &curr_speed[i]);
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phy_get_ops->phy_get_duplex(priv->mac_unit, phy_addr, &duplex);
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if (!priv->ops[i]) {
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printf("Phy ops not mapped\n");
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continue;
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}
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phy_get_ops = priv->ops[i];
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if (!phy_get_ops->phy_get_link_status ||
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!phy_get_ops->phy_get_speed ||
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!phy_get_ops->phy_get_duplex) {
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printf("Error:Link status/Get speed/Get duplex not mapped\n");
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return -1;
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}
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if (phy_node >= 0) {
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/*
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* For each ethernet port, one node should be added
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* inside port_phyinfo with appropriate phy address
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*/
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phy_addr = phy_info[i]->phy_address;
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} else {
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printf("Error:Phy addresses not configured in DT\n");
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return -1;
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}
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status = phy_get_ops->phy_get_link_status(priv->mac_unit, phy_addr);
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phy_get_ops->phy_get_speed(priv->mac_unit, phy_addr, &curr_speed[i]);
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phy_get_ops->phy_get_duplex(priv->mac_unit, phy_addr, &duplex);
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if (status == 0) {
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linkup++;
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@ -1008,28 +960,21 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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switch (curr_speed[i]) {
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case FAL_SPEED_10:
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mac_speed = 0x0;
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clk[0] = 0x209;
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clk[0] = 0x309;
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clk[1] = 0x9;
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clk[2] = 0x309;
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clk[2] = 0x409;
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clk[3] = 0x9;
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if (i == aquantia_port[0] || i == aquantia_port[1]) {
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clk[1] = 0x18;
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clk[3] = 0x18;
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if (i == 4) {
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clk[0] = 0x413;
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clk[2] = 0x513;
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} else {
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clk[0] = 0x213;
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clk[2] = 0x313;
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}
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clk[0] = 0x313;
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clk[2] = 0x413;
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}
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if (phy_node >= 0) {
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if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
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set_sgmii_mode(i, 1);
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if (i == 4) {
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clk[0] = 0x409;
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clk[2] = 0x509;
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}
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clk[0] = 0x309;
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clk[2] = 0x409;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1038,25 +983,21 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_100:
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mac_speed = 0x1;
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clk[0] = 0x209;
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clk[0] = 0x309;
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clk[1] = 0x0;
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clk[2] = 0x309;
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clk[2] = 0x409;
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clk[3] = 0x0;
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if (i == aquantia_port[0] || i == aquantia_port[1]) {
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clk[1] = 0x4;
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clk[3] = 0x4;
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if (i == 4) {
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clk[0] = 0x409;
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clk[2] = 0x509;
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}
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clk[0] = 0x309;
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clk[2] = 0x409;
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}
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if (phy_node >= 0) {
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if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
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set_sgmii_mode(i, 1);
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if (i == 4) {
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clk[0] = 0x409;
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clk[2] = 0x509;
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}
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clk[0] = 0x309;
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clk[2] = 0x409;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1065,31 +1006,19 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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break;
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case FAL_SPEED_1000:
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mac_speed = 0x2;
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clk[0] = 0x201;
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clk[0] = 0x301;
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clk[1] = 0x0;
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clk[2] = 0x301;
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clk[2] = 0x401;
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clk[3] = 0x0;
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if (i == aquantia_port[0] || i == aquantia_port[1]) {
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if (i == 4) {
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clk[0] = 0x404;
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clk[2] = 0x504;
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} else {
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clk[0] = 0x204;
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clk[2] = 0x304;
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}
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} else if (i == sfp_port[0] || i == sfp_port[1]) {
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if (i == 4) {
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clk[0] = 0x401;
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clk[2] = 0x501;
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}
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clk[0] = 0x304;
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clk[2] = 0x404;
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}
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if (phy_node >= 0) {
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if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
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set_sgmii_mode(i, 1);
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if (i == 4) {
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clk[0] = 0x401;
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clk[2] = 0x501;
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}
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clk[0] = 0x301;
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clk[2] = 0x401;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1101,34 +1030,15 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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clk[3] = 0x0;
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if (i == aquantia_port[0] || i == aquantia_port[1]) {
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mac_speed = 0x4;
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if (i == 4) {
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clk[0] = 0x407;
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clk[2] = 0x507;
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} else {
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clk[0] = 0x207;
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clk[2] = 0x307;
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}
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} else if (i == sfp_port[0] || i == sfp_port[1]) {
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mac_speed = 0x2;
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if (i == 4) {
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clk[0] = 0x401;
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clk[2] = 0x501;
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} else {
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clk[0] = 0x201;
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clk[2] = 0x301;
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}
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clk[0] = 0x307;
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clk[2] = 0x407;
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}
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if (phy_node >= 0) {
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if (phy_info[i]->phy_type == QCA8081_PHY_TYPE) {
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mac_speed = 0x2;
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set_sgmii_mode(i, 0);
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if (i == 4) {
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clk[0] = 0x401;
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clk[2] = 0x501;
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} else {
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clk[0] = 0x201;
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clk[2] = 0x301;
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}
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clk[0] = 0x301;
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clk[2] = 0x401;
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}
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}
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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@ -1139,13 +1049,8 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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mac_speed = 0x5;
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clk[1] = 0x0;
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clk[3] = 0x0;
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if (i == 4) {
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clk[0] = 0x403;
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clk[2] = 0x503;
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} else {
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clk[0] = 0x203;
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clk[2] = 0x303;
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}
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clk[0] = 0x303;
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clk[2] = 0x403;
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], curr_speed[i],
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dp[duplex]);
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@ -1154,13 +1059,8 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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mac_speed = 0x3;
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clk[1] = 0x0;
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clk[3] = 0x0;
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if (i == 4) {
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clk[0] = 0x401;
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clk[2] = 0x501;
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} else {
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clk[0] = 0x201;
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clk[2] = 0x301;
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}
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clk[0] = 0x301;
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clk[2] = 0x401;
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printf("eth%d PHY%d %s Speed :%d %s duplex\n",
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priv->mac_unit, i, lstatus[status], curr_speed[i],
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dp[duplex]);
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@ -1175,51 +1075,19 @@ static int devsoc_eth_init(struct eth_device *eth_dev, bd_t *this)
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sgmii_mode = get_sgmii_mode(i);
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ppe_port_bridge_txmac_set(i + 1, 1);
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if (sgmii_mode == 1) { /* SGMII Mode */
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if (i == 4)
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ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII0_RGMII4);
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else if (i == 5)
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ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII0_RGMII4);
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ppe_uniphy_mode_set(0x0, EPORT_WRAPPER_SGMII0_RGMII4);
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} else if (sgmii_mode == 0) { /* SGMII Plus Mode */
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if (i == 4)
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ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII_PLUS);
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else if (i == 5)
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ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII_PLUS);
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ppe_uniphy_mode_set(0x0, EPORT_WRAPPER_SGMII_PLUS);
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}
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}
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}
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if (i == sfp_port[0] || i == sfp_port[1]) {
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if (sgmii_fiber) { /* SGMII Fiber mode */
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ppe_port_bridge_txmac_set(i + 1, 1);
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if (i == 4)
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ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII_FIBER);
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else
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ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII_FIBER);
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ppe_port_mux_mac_type_set(i + 1, EPORT_WRAPPER_SGMII_FIBER);
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} else if (sfp_mode == EPORT_WRAPPER_10GBASE_R) { /* 10GBASE_R mode */
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if (i == 4)
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ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_10GBASE_R);
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else
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ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_10GBASE_R);
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ppe_port_mux_mac_type_set(i + 1, EPORT_WRAPPER_10GBASE_R);
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} else { /* SGMII Plus Mode */
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ppe_port_bridge_txmac_set(i + 1, 1);
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if (i == 4)
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ppe_uniphy_mode_set(0x1, EPORT_WRAPPER_SGMII_PLUS);
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else if (i == 5)
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ppe_uniphy_mode_set(0x2, EPORT_WRAPPER_SGMII_PLUS);
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}
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}
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devsoc_speed_clock_set(i, clk);
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devsoc_port_mac_clock_reset(i);
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if (i == aquantia_port[0] || i == aquantia_port[1])
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devsoc_uxsgmii_speed_set(i, mac_speed, duplex, status);
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else if ((i == sfp_port[0] || i == sfp_port[1]) && sgmii_fiber == 0)
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devsoc_10g_r_speed_set(i, status);
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else
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devsoc_pqsgmii_speed_set(i, mac_speed, status);
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#else
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@ -36,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define pr_info(fmt, args...) printf(fmt, ##args);
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extern int is_uniphy_enabled(int uniphy_index);
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extern void uniphy_port5_clock_source_set(void);
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/*
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* devsoc_ppe_reg_read()
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*/
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@ -212,6 +209,58 @@ void ppe_port_bridge_txmac_set(int port_id, int status)
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}
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void ppe_port_txmac_status_set(uint32_t port)
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{
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uint32_t reg_value = 0;
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pr_debug("DEBUGGING txmac_status_set......... PORTID = %d\n", port);
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devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value);
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reg_value |=TE;
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devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
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pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
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PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
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reg_value);
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}
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void ppe_port_rxmac_status_set(uint32_t port)
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{
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uint32_t reg_value = 0;
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pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port);
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devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
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MAC_RX_CONFIGURATION_ADDRESS +
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(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value);
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reg_value |= 0x300000c0;
|
||||
reg_value |=RE;
|
||||
reg_value |=ACS;
|
||||
reg_value |=CST;
|
||||
devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
MAC_RX_CONFIGURATION_ADDRESS +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value);
|
||||
|
||||
pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address = 0x%x -> Value = %u\n",
|
||||
PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_RX_CONFIGURATION_ADDRESS +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION),
|
||||
reg_value);
|
||||
}
|
||||
|
||||
void ppe_mac_packet_filter_set(uint32_t port)
|
||||
{
|
||||
pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port);
|
||||
devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
MAC_PACKET_FILTER_ADDRESS +
|
||||
(port * MAC_PACKET_FILTER_INC), 0x80000081);
|
||||
pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n",
|
||||
PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS +
|
||||
(port * MAC_PACKET_FILTER_ADDRESS),
|
||||
0x80000081);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DEVSOC_RUMI
|
||||
/*
|
||||
* devsoc_port_mac_clock_reset()
|
||||
|
|
@ -249,58 +298,6 @@ void devsoc_port_mac_clock_reset(int port)
|
|||
reg_val &= ~GCC_PPE_PORT2_MAC_ARES;
|
||||
reg_val1 &= ~GCC_PORT2_ARES;
|
||||
break;
|
||||
case 2:
|
||||
/* Assert */
|
||||
reg_val |= GCC_PPE_PORT3_MAC_ARES;
|
||||
reg_val1 |= GCC_PORT3_ARES;
|
||||
writel(reg_val, NSS_CC_PPE_RESET_ADDR);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
mdelay(150);
|
||||
/* De-Assert */
|
||||
reg_val = readl(NSS_CC_PPE_RESET_ADDR);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
reg_val &= ~GCC_PPE_PORT3_MAC_ARES;
|
||||
reg_val1 &= ~GCC_PORT3_ARES;
|
||||
break;
|
||||
case 3:
|
||||
/* Assert */
|
||||
reg_val |= GCC_PPE_PORT4_MAC_ARES;
|
||||
reg_val1 |= GCC_PORT4_ARES;
|
||||
writel(reg_val, NSS_CC_PPE_RESET_ADDR);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
mdelay(150);
|
||||
/* De-Assert */
|
||||
reg_val = readl(NSS_CC_PPE_RESET_ADDR);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
reg_val &= ~GCC_PPE_PORT4_MAC_ARES;
|
||||
reg_val1 &= ~GCC_PORT4_ARES;
|
||||
break;
|
||||
case 4:
|
||||
/* Assert */
|
||||
reg_val |= GCC_PPE_PORT5_MAC_ARES;
|
||||
reg_val1 |= GCC_PORT5_ARES;
|
||||
writel(reg_val, NSS_CC_PPE_RESET_ADDR);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
mdelay(150);
|
||||
/* De-Assert */
|
||||
reg_val = readl(NSS_CC_PPE_RESET_ADDR);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
reg_val &= ~GCC_PPE_PORT5_MAC_ARES;
|
||||
reg_val1 &= ~GCC_PORT5_ARES;
|
||||
break;
|
||||
case 5:
|
||||
/* Assert */
|
||||
reg_val |= GCC_PPE_PORT6_MAC_ARES;
|
||||
reg_val1 |= GCC_PORT6_ARES;
|
||||
writel(reg_val, NSS_CC_PPE_RESET_ADDR);
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
mdelay(150);
|
||||
/* De-Assert */
|
||||
reg_val = readl(NSS_CC_PPE_RESET_ADDR);
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
reg_val &= ~GCC_PPE_PORT6_MAC_ARES;
|
||||
reg_val1 &= ~GCC_PORT6_ARES;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -417,71 +414,16 @@ void ppe_xgmac_speed_set(uint32_t port, int speed)
|
|||
|
||||
}
|
||||
|
||||
void ppe_port_txmac_status_set(uint32_t port)
|
||||
{
|
||||
uint32_t reg_value = 0;
|
||||
|
||||
pr_debug("DEBUGGING txmac_status_set......... PORTID = %d\n", port);
|
||||
devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), ®_value);
|
||||
|
||||
reg_value |=TE;
|
||||
devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION), reg_value);
|
||||
|
||||
pr_debug("NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION Address = 0x%x -> Value = %u\n",
|
||||
PPE_SWITCH_NSS_SWITCH_XGMAC0 + (port * NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION),
|
||||
reg_value);
|
||||
}
|
||||
|
||||
void ppe_port_rxmac_status_set(uint32_t port)
|
||||
{
|
||||
uint32_t reg_value = 0;
|
||||
|
||||
pr_debug("DEBUGGING rxmac_status_set......... PORTID = %d\n", port);
|
||||
devsoc_ppe_reg_read(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
MAC_RX_CONFIGURATION_ADDRESS +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), ®_value);
|
||||
|
||||
reg_value |= 0x5ee00c0;
|
||||
reg_value |=RE;
|
||||
reg_value |=ACS;
|
||||
reg_value |=CST;
|
||||
devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
MAC_RX_CONFIGURATION_ADDRESS +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION), reg_value);
|
||||
|
||||
pr_debug("NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION Address = 0x%x -> Value = %u\n",
|
||||
PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_RX_CONFIGURATION_ADDRESS +
|
||||
(port * NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION),
|
||||
reg_value);
|
||||
}
|
||||
|
||||
void ppe_mac_packet_filter_set(uint32_t port)
|
||||
{
|
||||
pr_debug("DEBUGGING mac_packet_filter_set......... PORTID = %d\n", port);
|
||||
devsoc_ppe_reg_write(PPE_SWITCH_NSS_SWITCH_XGMAC0 +
|
||||
MAC_PACKET_FILTER_ADDRESS +
|
||||
(port * MAC_PACKET_FILTER_INC), 0x81);
|
||||
pr_debug("NSS_SWITCH_XGMAC_MAC_PACKET_FILTER Address = 0x%x -> Value = %u\n",
|
||||
PPE_SWITCH_NSS_SWITCH_XGMAC0 + MAC_PACKET_FILTER_ADDRESS +
|
||||
(port * MAC_PACKET_FILTER_ADDRESS),
|
||||
0x81);
|
||||
}
|
||||
|
||||
void devsoc_uxsgmii_speed_set(int port, int speed, int duplex,
|
||||
int status)
|
||||
{
|
||||
#ifndef CONFIG_DEVSOC_RUMI
|
||||
uint32_t uniphy_index;
|
||||
|
||||
/* Setting the speed only for PORT5 and PORT6 */
|
||||
if (port == (PORT5 - PPE_UNIPHY_INSTANCE1))
|
||||
uniphy_index = PPE_UNIPHY_INSTANCE1;
|
||||
else if (port == (PORT6 - PPE_UNIPHY_INSTANCE1))
|
||||
uniphy_index = PPE_UNIPHY_INSTANCE2;
|
||||
else
|
||||
if (port == PORT0)
|
||||
uniphy_index = PPE_UNIPHY_INSTANCE0;
|
||||
else
|
||||
uniphy_index = PPE_UNIPHY_INSTANCE1;
|
||||
|
||||
ppe_uniphy_usxgmii_autoneg_completed(uniphy_index);
|
||||
ppe_uniphy_usxgmii_speed_set(uniphy_index, speed);
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@
|
|||
#include <fdtdec.h>
|
||||
#include "ipq_phy.h"
|
||||
|
||||
extern int is_uniphy_enabled(int uniphy_index);
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
extern int ipq_mdio_write(int mii_id,
|
||||
|
|
@ -149,27 +148,6 @@ static void ppe_uniphy_reset(enum uniphy_reset_type rst_type, bool enable)
|
|||
reg_val &= ~0x4;
|
||||
writel(reg_val, GCC_UNIPHY0_MISC + GCC_UNIPHY_REG_INC);
|
||||
break;
|
||||
case UNIPHY2_SOFT_RESET:
|
||||
reg_val = readl(GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC));
|
||||
reg_val1 = readl(NSS_CC_UNIPHY_MISC_RESET);
|
||||
if (enable) {
|
||||
reg_val |= 0x1;
|
||||
reg_val1 |= 0x3000;
|
||||
} else {
|
||||
reg_val &= ~0x1;
|
||||
reg_val1 &= ~0x3000;
|
||||
}
|
||||
writel(reg_val, GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC));
|
||||
writel(reg_val1, NSS_CC_UNIPHY_MISC_RESET);
|
||||
break;
|
||||
case UNIPHY2_XPCS_RESET:
|
||||
reg_val = readl(GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC));
|
||||
if (enable)
|
||||
reg_val |= 0x4;
|
||||
else
|
||||
reg_val &= ~0x4;
|
||||
writel(reg_val, GCC_UNIPHY0_MISC + (2 * GCC_UNIPHY_REG_INC));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -179,10 +157,8 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
|
|||
{
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
mdelay(100);
|
||||
|
||||
writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
|
|
@ -192,14 +168,10 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
|
|||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
|
||||
} else if (uniphy_index == 1) {
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
|
||||
}
|
||||
mdelay(100);
|
||||
ppe_uniphy_calibration(uniphy_index);
|
||||
|
|
@ -212,10 +184,8 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
|
|||
{
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
mdelay(100);
|
||||
|
||||
writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
|
|
@ -224,14 +194,10 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
|
|||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
|
||||
} else if (uniphy_index == 1) {
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
|
||||
}
|
||||
mdelay(100);
|
||||
}
|
||||
|
|
@ -249,23 +215,14 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
|
|||
mdelay(500);
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
mdelay(100);
|
||||
|
||||
if (uniphy_index == 1) {
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
|
||||
} else if (uniphy_index == 2) {
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8);
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8);
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8);
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8);
|
||||
}
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + (uniphy_index * 0x8));
|
||||
writel(0x0, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8));
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8));
|
||||
writel(0x0, NSS_CC_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8));
|
||||
|
||||
switch (mode) {
|
||||
case EPORT_WRAPPER_SGMII_FIBER:
|
||||
|
|
@ -294,28 +251,17 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
|
|||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
|
||||
} else if (uniphy_index == 1) {
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
|
||||
}
|
||||
mdelay(100);
|
||||
|
||||
if (uniphy_index == 1) {
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT5 - 1) * 0x8);
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT5 - 1) * 0x8);
|
||||
} else if (uniphy_index == 2) {
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (PORT6 - 1) * 0x8);
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 8);
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + (PORT6 - 1) * 0x8);
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (PORT6 - 1) * 0x8);
|
||||
}
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + (uniphy_index * 0x8));
|
||||
writel(0x1, NSS_CC_UNIPHY_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8));
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + (uniphy_index * 0x8));
|
||||
writel(0x1, NSS_CC_PORT1_RX_CBCR + 0x4 + (uniphy_index * 0x8));
|
||||
|
||||
ppe_uniphy_calibration(uniphy_index);
|
||||
}
|
||||
|
|
@ -340,10 +286,8 @@ static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
|
|||
{
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
|
||||
writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
+ PPE_UNIPHY_MODE_CONTROL);
|
||||
|
|
@ -354,14 +298,10 @@ static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
|
|||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
|
||||
} else if (uniphy_index == 1) {
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
|
||||
}
|
||||
mdelay(100);
|
||||
|
||||
|
|
@ -369,10 +309,8 @@ static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
|
|||
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false);
|
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else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
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||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -391,10 +329,8 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
|||
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, true);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, true);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, true);
|
||||
mdelay(100);
|
||||
|
||||
writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
|
||||
|
|
@ -404,14 +340,10 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
|||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY0_SOFT_RESET, false);
|
||||
} else if (uniphy_index == 1) {
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY1_SOFT_RESET, false);
|
||||
} else {
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, true);
|
||||
mdelay(100);
|
||||
ppe_uniphy_reset(UNIPHY2_SOFT_RESET, false);
|
||||
}
|
||||
mdelay(100);
|
||||
|
||||
|
|
@ -419,10 +351,8 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
|||
|
||||
if (uniphy_index == 0)
|
||||
ppe_uniphy_reset(UNIPHY0_XPCS_RESET, false);
|
||||
else if (uniphy_index == 1)
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
|
||||
else
|
||||
ppe_uniphy_reset(UNIPHY2_XPCS_RESET, false);
|
||||
ppe_uniphy_reset(UNIPHY1_XPCS_RESET, false);
|
||||
mdelay(100);
|
||||
|
||||
ppe_uniphy_10g_r_linkup(uniphy_index);
|
||||
|
|
@ -442,11 +372,6 @@ static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
|
|||
|
||||
void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
|
||||
{
|
||||
if (!is_uniphy_enabled(uniphy_index)) {
|
||||
printf("Uniphy %u is disabled\n", uniphy_index);
|
||||
return;
|
||||
}
|
||||
|
||||
switch(mode) {
|
||||
case EPORT_WRAPPER_PSGMII:
|
||||
ppe_uniphy_psgmii_mode_set(uniphy_index);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue