diff --git a/arch/arm/include/asm/arch-ipq5332/clk.h b/arch/arm/include/asm/arch-ipq5332/clk.h
index e8f6826dd5..69b1972992 100644
--- a/arch/arm/include/asm/arch-ipq5332/clk.h
+++ b/arch/arm/include/asm/arch-ipq5332/clk.h
@@ -89,14 +89,17 @@
  * GCC-SDCC Registers
  */
 
-#define GCC_SDCC1_BCR				0x01833000
-#define GCC_SDCC1_APPS_CMD_RCGR			0x01833004
-#define GCC_SDCC1_APPS_CFG_RCGR			0x01833008
-#define GCC_SDCC1_APPS_M			0x0183300C
-#define GCC_SDCC1_APPS_N			0x01833010
-#define GCC_SDCC1_APPS_D			0x01833014
-#define GCC_SDCC1_APPS_CBCR			0x01833034
-#define GCC_SDCC1_AHB_CBCR			0x0183301C
+#define GCC_SDCC1_BCR				0x1833000
+#define GCC_SDCC1_APPS_CMD_RCGR			0x1833004
+#define GCC_SDCC1_APPS_CFG_RCGR			0x1833008
+#define GCC_SDCC1_APPS_M			0x183300C
+#define GCC_SDCC1_APPS_N			0x1833010
+#define GCC_SDCC1_APPS_D			0x1833014
+#define GCC_SDCC1_APPS_CBCR			0x183302C
+#define GCC_SDCC1_AHB_CBCR			0x1833034
+#define GCC_SDCC1_APPS_CFG_RCGR_MODE_SEL	(2 << 12)
+#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL		(2 << 8)
+#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV		(0xB << 0)
 
 /*
  * Ethernet Clocks
diff --git a/board/qca/arm/ipq5332/clock.c b/board/qca/arm/ipq5332/clock.c
index 82ce447ad8..65f99593bd 100644
--- a/board/qca/arm/ipq5332/clock.c
+++ b/board/qca/arm/ipq5332/clock.c
@@ -85,27 +85,26 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
 void emmc_clock_init(void)
 {
 #ifdef QCA_CLOCK_ENABLE
-	/* Enable root clock generator */
-	writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR);
-	/* Add 10us delay for CLK_OFF to get cleared */
-	udelay(10);
-	writel(readl(GCC_SDCC1_AHB_CBCR)|0x1, GCC_SDCC1_AHB_CBCR);
-	/* PLL0 - 192Mhz */
-	writel(0x20B, GCC_SDCC1_APPS_CFG_RCGR);
-	/* Delay for clock operation complete */
-	udelay(10);
-	writel(0x1, GCC_SDCC1_APPS_M);
-	/* check this M, N D value while debugging
-	 * because as per clock tool the actual M, N, D
-	 * values are M=1, N=FA, D=F9
+	int cfg;
+
+	/* Configure sdcc1_apps_clk_src */
+	cfg = (GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL |
+		GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV |
+		GCC_SDCC1_APPS_CFG_RCGR_MODE_SEL);
+	writel(cfg, GCC_SDCC1_APPS_CFG_RCGR);
+	/*
+	 * Mode is dual edge,
+	 * For 192Mhz doesn't require MND value
+	 * 1152 / 6 = 192
 	 */
-	writel(0xFC, GCC_SDCC1_APPS_N);
-	writel(0xFD, GCC_SDCC1_APPS_D);
-	/* Delay for clock operation complete */
+	writel(CMD_UPDATE, GCC_SDCC1_APPS_CMD_RCGR);
+	mdelay(10);
+	writel(ROOT_EN, GCC_SDCC1_APPS_CMD_RCGR);
+
+	/* Configure CBCRs */
+	writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
 	udelay(10);
-	/* Update APPS_CMD_RCGR to reflect source selection */
-	writel(readl(GCC_SDCC1_APPS_CMD_RCGR)|0x1, GCC_SDCC1_APPS_CMD_RCGR);
-	/* Add 10us delay for clock update to complete */
+	writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
 	udelay(10);
 #else
 	return;