mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 08:51:31 +01:00
Merge "ipq9574: update peripheral clk"
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commit
bdda3ea85e
5 changed files with 415 additions and 272 deletions
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@ -92,6 +92,7 @@
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lane = <1>;
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status = "disabled";
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skip_phy_int = <1>;
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id = <0>;
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};
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pci@20000000 {
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@ -112,6 +113,7 @@
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lane = <2>;
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status = "disabled";
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skip_phy_int = <1>;
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id = <2>;
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};
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pci@18000000 {
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@ -132,6 +134,7 @@
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lane = <2>;
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status = "disabled";
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skip_phy_int = <1>;
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id = <3>;
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};
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pci@10000000 {
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@ -152,6 +155,7 @@
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lane = <1>;
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status = "disabled";
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skip_phy_int = <1>;
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id = <1>;
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};
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timer {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2016, 2018, 2021 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -73,6 +73,157 @@ void i2c_clock_config(void);
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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/*
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* Qpic SPI Nand clock
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*/
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#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004
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#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008
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#define GCC_QPIC_IO_MACRO_CBCR 0x183200C
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#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010
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#define GCC_QPIC_CBCR_ADDR 0x1832014
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#define GCC_QPIC_SLEEP_CBCR 0x1832018
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#define IO_MACRO_CLK_320_MHZ 320000000
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#define IO_MACRO_CLK_266_MHZ 266000000
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#define IO_MACRO_CLK_228_MHZ 228000000
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#define IO_MACRO_CLK_200_MHZ 200000000
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#define IO_MACRO_CLK_100_MHZ 100000000
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#define IO_MACRO_CLK_24MHZ 24000000
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#define QPIC_IO_MACRO_CLK 0
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#define QPIC_CORE_CLK 1
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#define XO_CLK_SRC 2
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#define GPLL0_CLK_SRC 3
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#define FB_CLK_BIT (1 << 4)
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#define UPDATE_EN 0x1
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/*
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* GCC-SDCC
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*/
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#define GCC_SDCC1_BCR 0x1833000
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#define GCC_SDCC1_APPS_CMD_RCGR 0x1833004
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#define GCC_SDCC1_APPS_CFG_RCGR 0x1833008
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#define GCC_SDCC1_APPS_M 0x183300C
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#define GCC_SDCC1_APPS_N 0x1833010
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#define GCC_SDCC1_APPS_D 0x1833014
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#define GCC_SDCC1_APPS_CBCR 0x183302C
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#define GCC_SDCC1_AHB_CBCR 0x1833034
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#define SDCC1_M_VAL 0x1
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#define SDCC1_N_VAL 0xFC
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#define SDCC1_D_VAL 0xFD
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV (0xB << 0)
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/*
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* USB
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*/
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#define GCC_USB_BCR 0x182C000
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#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
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#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
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#define GCC_USB0_AUX_CMD_RCGR 0x182C018
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#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
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#define GCC_USB0_AUX_M 0x182C020
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#define GCC_USB0_AUX_N 0x182C024
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#define GCC_USB0_AUX_D 0x182C028
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#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
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#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
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#define GCC_USB0_MOCK_UTMI_M 0x182C034
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#define GCC_USB0_MOCK_UTMI_N 0x182C038
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#define GCC_USB0_MOCK_UTMI_D 0x182C03C
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#define GCC_USB0_MASTER_CBCR 0x182C044
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#define GCC_USB0_AUX_CBCR 0x182C048
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#define GCC_USB0_MOCK_UTMI_CBCR 0x182C04C
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#define GCC_USB0_PIPE_CBCR 0x182C054
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#define GCC_USB0_SLEEP_CBCR 0x182C058
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#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
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#define GCC_USB_0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_QUSB2_0_PHY_BCR 0x182C068
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#define GCC_USB0_PHY_BCR 0x182C06C
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#define GCC_USB3PHY_0_PHY_BCR 0x182C070
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#define GCC_USB0_PHY_PIPE_MISC 0x182C074
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#define AUX_M 0x0
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#define AUX_N 0x0
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#define AUX_D 0x0
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#define SW_COLLAPSE_ENABLE (1 << 0)
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#define SW_OVERRIDE_ENABLE (1 << 2)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0xb << 0)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (0 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (1 << 0)
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#define UTMI_M 0x1
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#define UTMI_N 0xf7
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#define UTMI_D 0xf6
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#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
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#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0 << 0)
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/*
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* PCIE
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*/
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#define GCC_PCIE_BASE 0x1828000
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#define GCC_PCIE_REG(_offset, _index) (GCC_PCIE_BASE + _offset +\
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(_index * 0x1000))
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#define GCC_PCIE_BCR 0x0
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#define GCC_PCIE_AUX_CMD_RCGR 0x4
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#define GCC_PCIE_AUX_CFG_RCGR 0x8
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#define GCC_PCIE_AUX_M 0xC
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#define GCC_PCIE_AUX_N 0x10
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#define GCC_PCIE_AUX_D 0x14
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#define GCC_PCIE_AXI_M_CMD_RCGR 0x18
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#define GCC_PCIE_AXI_M_CFG_RCGR 0x1C
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#define GCC_PCIE_AXI_S_CMD_RCGR 0x20
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#define GCC_PCIE_AXI_S_CFG_RCGR 0x24
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#define GCC_PCIE_RCHNG_CMD_RCGR 0x28
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#define GCC_PCIE_RCHNG_CFG_RCGR 0x2C
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#define GCC_PCIE_AHB_CBCR 0x30
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#define GCC_PCIE_AUX_CBCR 0x34
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#define GCC_PCIE_AXI_M_CBCR 0x38
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#define GCC_PCIE_AXI_S_CBCR 0x3C
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#define GCC_PCIE_AXI_S_BRIDGE_CBCR 0x40
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#define GCC_PCIE_PIPE_CBCR 0x44
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#define GCC_PCIE_BOOT_CLOCK_CTL 0x50
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#define GCC_PCIE_LINK_DOWN_BCR 0x54
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#define GCC_PCIE_MISC_RESET 0x58
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#define GCC_PCIEPHY_PHY_BCR 0x5C
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#define GCC_PCIE_PHY_BCR 0x60
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#define GCC_PCIE_PHY_PIPE_MISC 0x64
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (0 << 8)
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0 << 0)
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#define GCC_PCIE_AXI_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_PCIE_AXI_CFG_RCGR_SRC_DIV (7 << 0)
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define PIPE_CLK_ENABLE 0x4FF1
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#define CLK_DISABLE 0x0
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#define NOC_HANDSHAKE_FSM_EN (1 << 15)
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#define GCC_PCIE_RCHNG_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_PCIE_RCHNG_CFG_RCGR_SRC_DIV (0xF << 0)
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#define GCC_PCIE_PHY_PIPE_MISC_SRC_SEL (0x1 << 8)
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#ifdef CONFIG_QPIC_NAND
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void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
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int req_clk_src_type);
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id);
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void usb_clock_deinit(void);
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#endif
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void);
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void emmc_clock_reset(void);
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#endif
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id);
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void pcie_v2_clock_deinit(int pcie_id);
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#endif
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#endif /*IPQ9574_CLK_H*/
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@ -100,3 +100,201 @@ int uart_clock_config(struct ipq_serial_platdata *plat)
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return 0;
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}
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#ifdef CONFIG_QPIC_NAND
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void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, int req_clk_src_type)
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{
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switch (blk_type) {
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case QPIC_IO_MACRO_CLK:
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/* select the clk source for IO_PAD_MACRO
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* clk source wil be either XO = 24MHz. or GPLL0 = 800MHz.
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*/
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if (req_clk_src_type == XO_CLK_SRC) {
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/* default XO clock will enabled
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* i.e XO clock = 24MHz.
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* so div value will 0.
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* Input clock to IO_MACRO will be divided by 4 by default
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* by hardware and then taht clock will be go on bus.
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* i.e 24/4MHz = 6MHz i.e 6MHz will go onto the bus.
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*/
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writel(0x0, GCC_QPIC_IO_MACRO_CFG_RCGR);
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} else if (req_clk_src_type == GPLL0_CLK_SRC) {
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/* selct GPLL0 clock source 800MHz
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* so 800/4 = 200MHz.
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* Input clock to IO_MACRO will be divided by 4 by default
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* by hardware and then that clock will be go on bus.
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* i.e 200/4MHz = 50MHz i.e 50MHz will go onto the bus.
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*/
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if (clk_rate == IO_MACRO_CLK_320_MHZ)
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writel(0x104, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_266_MHZ)
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writel(0x105, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_228_MHZ)
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writel(0x106, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_100_MHZ)
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writel(0x10F, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_200_MHZ)
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writel(0x107, GCC_QPIC_IO_MACRO_CFG_RCGR);
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} else {
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printf("wrong clk src selection requested.\n");
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}
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/* Enablle update bit to update the new configuration */
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writel((UPDATE_EN | readl(GCC_QPIC_IO_MACRO_CMD_RCGR)),
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GCC_QPIC_IO_MACRO_CMD_RCGR);
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/* Enable the QPIC_IO_MACRO_CLK */
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writel(0x1, GCC_QPIC_IO_MACRO_CBCR);
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break;
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case QPIC_CORE_CLK:
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/* To DO if needed for QPIC core clock setting */
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break;
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default:
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printf("wrong qpic block type\n");
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break;
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}
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}
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#endif
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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int cfg;
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/* Configure pcie_aux_clk_src */
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cfg = (GCC_PCIE_AUX_CFG_RCGR_SRC_SEL | GCC_PCIE_AUX_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_PCIE_REG(GCC_PCIE_AUX_CFG_RCGR, pcie_id));
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writel(CMD_UPDATE, GCC_PCIE_REG(GCC_PCIE_AUX_CMD_RCGR, pcie_id));
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mdelay(100);
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writel(ROOT_EN, GCC_PCIE_REG(GCC_PCIE_AUX_CMD_RCGR, pcie_id));
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/* Configure CBCRs */
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AHB_CBCR, pcie_id));
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AXI_M_CBCR, pcie_id));
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AXI_S_CBCR, pcie_id));
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AUX_CBCR, pcie_id));
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writel(PIPE_CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_PIPE_CBCR, pcie_id));
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writel(CLK_ENABLE, GCC_PCIE_REG(GCC_PCIE_AXI_S_BRIDGE_CBCR, pcie_id));
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/* Configure pcie_rchng_clk_src */
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cfg = (GCC_PCIE_RCHNG_CFG_RCGR_SRC_SEL
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| GCC_PCIE_RCHNG_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_PCIE_REG(GCC_PCIE_RCHNG_CFG_RCGR, pcie_id));
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writel(CMD_UPDATE, GCC_PCIE_REG(GCC_PCIE_RCHNG_CMD_RCGR, pcie_id));
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mdelay(100);
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writel(ROOT_EN, GCC_PCIE_REG(GCC_PCIE_RCHNG_CMD_RCGR, pcie_id));
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#endif
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}
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void pcie_v2_clock_deinit(int pcie_id)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AUX_CMD_RCGR, pcie_id));
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mdelay(100);
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AHB_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AXI_M_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AXI_S_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AUX_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_PIPE_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_AXI_S_BRIDGE_CBCR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_RCHNG_CFG_RCGR, pcie_id));
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writel(0x0, GCC_PCIE_REG(GCC_PCIE_RCHNG_CMD_RCGR, pcie_id));
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#endif
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}
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#endif
|
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id)
|
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{
|
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#ifndef CONFIG_IPQ9574_RUMI
|
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int cfg;
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/* Configure usb0_master_clk_src */
|
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cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL |
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GCC_USB0_MASTER_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_USB0_MASTER_CFG_RCGR);
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writel(CMD_UPDATE, GCC_USB0_MASTER_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MASTER_CMD_RCGR);
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|
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/* Configure usb0_mock_utmi_clk_src */
|
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cfg = (GCC_USB_MOCK_UTMI_SRC_SEL |
|
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GCC_USB_MOCK_UTMI_SRC_DIV);
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writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR);
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writel(UTMI_M, GCC_USB0_MOCK_UTMI_M);
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writel(UTMI_N, GCC_USB0_MOCK_UTMI_N);
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writel(UTMI_D, GCC_USB0_MOCK_UTMI_D);
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writel(CMD_UPDATE, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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|
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/* Configure usb0_aux_clk_src */
|
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cfg = (GCC_USB0_AUX_CFG_SRC_SEL |
|
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GCC_USB0_AUX_CFG_SRC_DIV);
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writel(cfg, GCC_USB0_AUX_CFG_RCGR);
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writel(AUX_M, GCC_USB0_AUX_M);
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writel(AUX_N, GCC_USB0_AUX_N);
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writel(AUX_D, GCC_USB0_AUX_D);
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writel(CMD_UPDATE, GCC_USB0_AUX_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_AUX_CMD_RCGR);
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/* Configure CBCRs */
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writel((readl(GCC_USB0_MASTER_CBCR) | CLK_ENABLE),
|
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GCC_USB0_MASTER_CBCR);
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writel(CLK_ENABLE, GCC_USB0_SLEEP_CBCR);
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writel(CLK_ENABLE, GCC_USB0_MOCK_UTMI_CBCR);
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writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN),
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GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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#endif
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}
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void usb_clock_deinit(void)
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{
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#ifndef CONFIG_IPQ9574_RUMI
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/* Disable clocks */
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB0_MASTER_CBCR);
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writel(0, GCC_USB0_SLEEP_CBCR);
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writel(0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0, GCC_USB0_AUX_CBCR);
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#endif
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}
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#endif
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void)
|
||||
{
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||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
int cfg;
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||||
|
||||
/* Configure sdcc1_apps_clk_src */
|
||||
cfg = (GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL
|
||||
| GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV);
|
||||
writel(cfg, GCC_SDCC1_APPS_CFG_RCGR);
|
||||
writel(SDCC1_M_VAL, GCC_SDCC1_APPS_M);
|
||||
writel(SDCC1_N_VAL, GCC_SDCC1_APPS_N);
|
||||
writel(SDCC1_D_VAL, GCC_SDCC1_APPS_D);
|
||||
writel(CMD_UPDATE, GCC_SDCC1_APPS_CMD_RCGR);
|
||||
mdelay(100);
|
||||
writel(ROOT_EN, GCC_SDCC1_APPS_CMD_RCGR);
|
||||
|
||||
/* Configure CBCRs */
|
||||
writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
|
||||
udelay(10);
|
||||
writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
|
||||
#endif
|
||||
}
|
||||
|
||||
void emmc_clock_reset(void)
|
||||
{
|
||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
writel(0x1, GCC_SDCC1_BCR);
|
||||
udelay(10);
|
||||
writel(0x0, GCC_SDCC1_BCR);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,7 +30,9 @@
|
|||
|
||||
#define DLOAD_MAGIC_COOKIE 0x10
|
||||
#define DLOAD_DISABLED 0x40
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct sdhci_host mmc_host;
|
||||
extern int ipq9574_edma_init(void *cfg);
|
||||
extern int ipq_spi_init(u16);
|
||||
|
|
@ -76,65 +78,6 @@ void fdt_fixup_qpic(void *blob)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_QPIC_NAND
|
||||
void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, int req_clk_src_type)
|
||||
{
|
||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
switch (blk_type) {
|
||||
case QPIC_IO_MACRO_CLK:
|
||||
/* select the clk source for IO_PAD_MACRO
|
||||
* clk source wil be either XO = 24MHz. or GPLL0 = 800MHz.
|
||||
*/
|
||||
if (req_clk_src_type == XO_CLK_SRC) {
|
||||
/* default XO clock will enabled
|
||||
* i.e XO clock = 24MHz.
|
||||
* so div value will 0.
|
||||
* Input clock to IO_MACRO will be divided by 4 by default
|
||||
* by hardware and then taht clock will be go on bus.
|
||||
* i.e 24/4MHz = 6MHz i.e 6MHz will go onto the bus.
|
||||
*/
|
||||
writel(0x0, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
|
||||
} else if (req_clk_src_type == GPLL0_CLK_SRC) {
|
||||
/* selct GPLL0 clock source 800MHz
|
||||
* so 800/4 = 200MHz.
|
||||
* Input clock to IO_MACRO will be divided by 4 by default
|
||||
* by hardware and then that clock will be go on bus.
|
||||
* i.e 200/4MHz = 50MHz i.e 50MHz will go onto the bus.
|
||||
*/
|
||||
if (clk_rate == IO_MACRO_CLK_320_MHZ)
|
||||
writel(0x104, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
else if (clk_rate == IO_MACRO_CLK_266_MHZ)
|
||||
writel(0x105, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
else if (clk_rate == IO_MACRO_CLK_228_MHZ)
|
||||
writel(0x106, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
else if (clk_rate == IO_MACRO_CLK_100_MHZ)
|
||||
writel(0x10F, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
else if (clk_rate == IO_MACRO_CLK_200_MHZ)
|
||||
writel(0x107, GCC_QPIC_IO_MACRO_CFG_RCGR);
|
||||
|
||||
} else {
|
||||
printf("wrong clk src selection requested.\n");
|
||||
}
|
||||
|
||||
/* Enablle update bit to update the new configuration */
|
||||
writel((UPDATE_EN | readl(GCC_QPIC_IO_MACRO_CMD_RCGR)),
|
||||
GCC_QPIC_IO_MACRO_CMD_RCGR);
|
||||
|
||||
/* Enable the QPIC_IO_MACRO_CLK */
|
||||
writel(0x1, GCC_QPIC_IO_MACRO_CBCR);
|
||||
|
||||
break;
|
||||
case QPIC_CORE_CLK:
|
||||
/* To DO if needed for QPIC core clock setting */
|
||||
break;
|
||||
default:
|
||||
printf("wrong qpic block type\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void qpic_emulation_set_clk(void)
|
||||
{
|
||||
|
|
@ -175,29 +118,6 @@ void board_nand_init(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_QCA_MMC
|
||||
void emmc_clock_config(void)
|
||||
{
|
||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
int cfg;
|
||||
|
||||
/* Configure sdcc1_apps_clk_src */
|
||||
cfg = (GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL
|
||||
| GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV);
|
||||
writel(cfg, GCC_SDCC1_APPS_CFG_RCGR);
|
||||
writel(SDCC1_M_VAL, GCC_SDCC1_APPS_M);
|
||||
writel(SDCC1_N_VAL, GCC_SDCC1_APPS_N);
|
||||
writel(SDCC1_D_VAL, GCC_SDCC1_APPS_D);
|
||||
writel(CMD_UPDATE, GCC_SDCC1_APPS_CMD_RCGR);
|
||||
mdelay(100);
|
||||
writel(ROOT_EN, GCC_SDCC1_APPS_CMD_RCGR);
|
||||
|
||||
/* Configure CBCRs */
|
||||
writel(readl(GCC_SDCC1_APPS_CBCR) | CLK_ENABLE, GCC_SDCC1_APPS_CBCR);
|
||||
udelay(10);
|
||||
writel(readl(GCC_SDCC1_AHB_CBCR) | CLK_ENABLE, GCC_SDCC1_AHB_CBCR);
|
||||
#endif
|
||||
}
|
||||
|
||||
void mmc_iopad_config(struct sdhci_host *host)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -215,26 +135,13 @@ void sdhci_bus_pwr_off(struct sdhci_host *host)
|
|||
sdhci_writeb(host,(val & (~SDHCI_POWER_ON)), SDHCI_POWER_CONTROL);
|
||||
}
|
||||
|
||||
void emmc_clock_disable(void)
|
||||
{
|
||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
/* Clear divider */
|
||||
writel(0x0, GCC_SDCC1_MISC);
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_mmc_deinit(void)
|
||||
{
|
||||
emmc_clock_disable();
|
||||
}
|
||||
|
||||
void emmc_clock_reset(void)
|
||||
{
|
||||
#ifndef CONFIG_IPQ9574_RUMI
|
||||
writel(0x1, GCC_SDCC1_BCR);
|
||||
udelay(10);
|
||||
writel(0x0, GCC_SDCC1_BCR);
|
||||
#endif
|
||||
/*
|
||||
* since we do not have misc register in ipq9574
|
||||
* so simply return from this function
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
|
|
@ -255,10 +162,9 @@ int board_mmc_init(bd_t *bis)
|
|||
mmc_host.cfg.part_type = PART_TYPE_EFI;
|
||||
mmc_host.quirks = SDHCI_QUIRK_BROKEN_VOLTAGE;
|
||||
|
||||
emmc_clock_disable();
|
||||
emmc_clock_reset();
|
||||
udelay(10);
|
||||
emmc_clock_config();
|
||||
emmc_clock_init();
|
||||
|
||||
if (add_sdhci(&mmc_host, 200000000, 400000)) {
|
||||
printf("add_sdhci fail!\n");
|
||||
|
|
@ -297,12 +203,9 @@ void board_usb_deinit(int id)
|
|||
|
||||
/* Enable USB PHY Power down */
|
||||
setbits_le32(USB30_PHY_1_QUSB2PHY_BASE + 0xB4, 0x1);
|
||||
/* Disable clocks */
|
||||
writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
|
||||
writel(0xcff0, GCC_USB0_MASTER_CBCR);
|
||||
writel(0, GCC_USB0_SLEEP_CBCR);
|
||||
writel(0, GCC_USB0_MOCK_UTMI_CBCR);
|
||||
writel(0, GCC_USB0_AUX_CBCR);
|
||||
|
||||
usb_clock_deinit();
|
||||
|
||||
/* GCC_QUSB2_0_PHY_BCR */
|
||||
set_mdelay_clearbits_le32(GCC_QUSB2_0_PHY_BCR, 0x1, 10);
|
||||
/* GCC_USB0_PHY_BCR */
|
||||
|
|
@ -311,50 +214,6 @@ void board_usb_deinit(int id)
|
|||
set_mdelay_clearbits_le32(GCC_USB_BCR, 0x1, 10);
|
||||
}
|
||||
|
||||
static void usb_clock_init(int id)
|
||||
{
|
||||
int cfg;
|
||||
/* Configure usb0_master_clk_src */
|
||||
cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL |
|
||||
GCC_USB0_MASTER_CFG_RCGR_SRC_DIV);
|
||||
writel(cfg, GCC_USB0_MASTER_CFG_RCGR);
|
||||
writel(CMD_UPDATE, GCC_USB0_MASTER_CMD_RCGR);
|
||||
mdelay(100);
|
||||
writel(ROOT_EN, GCC_USB0_MASTER_CMD_RCGR);
|
||||
|
||||
/* Configure usb0_mock_utmi_clk_src */
|
||||
cfg = (GCC_USB_MOCK_UTMI_SRC_SEL |
|
||||
GCC_USB_MOCK_UTMI_SRC_DIV);
|
||||
writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR);
|
||||
writel(UTMI_M, GCC_USB0_MOCK_UTMI_M);
|
||||
writel(UTMI_N, GCC_USB0_MOCK_UTMI_N);
|
||||
writel(UTMI_D, GCC_USB0_MOCK_UTMI_D);
|
||||
writel(CMD_UPDATE, GCC_USB0_MOCK_UTMI_CMD_RCGR);
|
||||
mdelay(100);
|
||||
writel(ROOT_EN, GCC_USB0_MOCK_UTMI_CMD_RCGR);
|
||||
|
||||
/* Configure usb0_aux_clk_src */
|
||||
cfg = (GCC_USB0_AUX_CFG_SRC_SEL |
|
||||
GCC_USB0_AUX_CFG_SRC_DIV);
|
||||
writel(cfg, GCC_USB0_AUX_CFG_RCGR);
|
||||
writel(AUX_M, GCC_USB0_AUX_M);
|
||||
writel(AUX_N, GCC_USB0_AUX_N);
|
||||
writel(AUX_D, GCC_USB0_AUX_D);
|
||||
writel(CMD_UPDATE, GCC_USB0_AUX_CMD_RCGR);
|
||||
mdelay(100);
|
||||
writel(ROOT_EN, GCC_USB0_AUX_CMD_RCGR);
|
||||
|
||||
/* Configure CBCRs */
|
||||
writel((readl(GCC_USB0_MASTER_CBCR) | CLK_ENABLE),
|
||||
GCC_USB0_MASTER_CBCR);
|
||||
writel(CLK_ENABLE, GCC_USB0_SLEEP_CBCR);
|
||||
writel(CLK_ENABLE, GCC_USB0_MOCK_UTMI_CBCR);
|
||||
writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN),
|
||||
GCC_USB0_PHY_CFG_AHB_CBCR);
|
||||
writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
|
||||
writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
|
||||
}
|
||||
|
||||
static void usb_init_hsphy(void __iomem *phybase)
|
||||
{
|
||||
/* Enable QUSB2PHY Power down */
|
||||
|
|
@ -562,7 +421,7 @@ void ipq_fdt_fixup_usb_device_mode(void *blob)
|
|||
#ifdef CONFIG_PCI_IPQ
|
||||
void board_pci_init(int id)
|
||||
{
|
||||
int node, gpio_node;
|
||||
int node, gpio_node, pci_no;
|
||||
char name[16];
|
||||
|
||||
snprintf(name, sizeof(name), "pci%d", id);
|
||||
|
|
@ -576,12 +435,15 @@ void board_pci_init(int id)
|
|||
if (gpio_node >= 0)
|
||||
qca_gpio_init(gpio_node);
|
||||
|
||||
pci_no = fdtdec_get_int(gd->fdt_blob, node, "id", 0);
|
||||
pcie_v2_clock_init(pci_no);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void board_pci_deinit()
|
||||
{
|
||||
int node, gpio_node, i, err;
|
||||
int node, gpio_node, i, err, pci_no;
|
||||
char name[16];
|
||||
struct fdt_resource parf;
|
||||
struct fdt_resource pci_phy;
|
||||
|
|
@ -607,7 +469,8 @@ void board_pci_deinit()
|
|||
gpio_node = fdt_subnode_offset(gd->fdt_blob, node, "pci_gpio");
|
||||
if (gpio_node >= 0)
|
||||
qca_gpio_deinit(gpio_node);
|
||||
|
||||
pci_no = fdtdec_get_int(gd->fdt_blob, node, "id", 0);
|
||||
pcie_v2_clock_deinit(pci_no);
|
||||
}
|
||||
|
||||
return ;
|
||||
|
|
|
|||
|
|
@ -18,93 +18,59 @@
|
|||
#include <asm/u-boot.h>
|
||||
#include <asm/arch-qca-common/qca_common.h>
|
||||
|
||||
#define CLK_TOGGLE_ENABLE 0x1
|
||||
#define GCC_NSS_PPE_RESET 0x01868014
|
||||
#define CLK_TOGGLE_ENABLE 0x1
|
||||
#define GCC_NSS_PPE_RESET 0x01868014
|
||||
|
||||
/*
|
||||
* PPE ASSERT and DEASSERT values
|
||||
*/
|
||||
#define PPE_ASSERT 0xf0000
|
||||
#define PPE_DEASSERT 0x0
|
||||
#define PPE_ASSERT 0xf0000
|
||||
#define PPE_DEASSERT 0x0
|
||||
|
||||
/*
|
||||
* EDMA HW ASSERT and DEASSERT values
|
||||
*/
|
||||
#define GCC_EDMA_HW_RESET_ASSERT 0x300000
|
||||
#define GCC_EDMA_HW_RESET_DEASSERT 0x0
|
||||
#define GCC_EDMA_HW_RESET_ASSERT 0x300000
|
||||
#define GCC_EDMA_HW_RESET_DEASSERT 0x0
|
||||
|
||||
/*
|
||||
* NSS Port ASSERT and DEASSERT values
|
||||
*/
|
||||
#define NSS_PORT1_ASSERT 0x1000003
|
||||
#define NSS_PORT2_ASSERT 0x200000c
|
||||
#define NSS_PORT3_ASSERT 0x4000030
|
||||
#define NSS_PORT4_ASSERT 0x8000300
|
||||
#define NSS_PORT5_ASSERT 0x10000c00
|
||||
#define NSS_PORT1_ASSERT 0x1000003
|
||||
#define NSS_PORT2_ASSERT 0x200000c
|
||||
#define NSS_PORT3_ASSERT 0x4000030
|
||||
#define NSS_PORT4_ASSERT 0x8000300
|
||||
#define NSS_PORT5_ASSERT 0x10000c00
|
||||
|
||||
#define BLSP1_UART0_BASE 0x078AF000
|
||||
#define BLSP1_UART0_BASE 0x078AF000
|
||||
#define UART_PORT_ID(reg) ((reg - BLSP1_UART0_BASE) / 0x1000)
|
||||
|
||||
#define CLOCK_UPDATE_TIMEOUT_US 1000
|
||||
#define CLOCK_UPDATE_TIMEOUT_US 1000
|
||||
|
||||
#define KERNEL_AUTH_CMD 0x1E
|
||||
#define SCM_CMD_SEC_AUTH 0x1F
|
||||
#define KERNEL_AUTH_CMD 0x1E
|
||||
#define SCM_CMD_SEC_AUTH 0x1F
|
||||
|
||||
#ifdef CONFIG_SMEM_VERSION_C
|
||||
#define RAM_PART_NAME_LENGTH 16
|
||||
#define RAM_PART_NAME_LENGTH 16
|
||||
|
||||
#define SECONDARY_CORE_STACKSZ (8 * 1024)
|
||||
#define CPU_POWER_DOWN (1 << 16)
|
||||
#define SECONDARY_CORE_STACKSZ (8 * 1024)
|
||||
#define CPU_POWER_DOWN (1 << 16)
|
||||
|
||||
#define ARM_PSCI_TZ_FN_BASE 0x84000000
|
||||
#define ARM_PSCI_TZ_FN(n) (ARM_PSCI_TZ_FN_BASE + (n))
|
||||
#define ARM_PSCI_TZ_FN_BASE 0x84000000
|
||||
#define ARM_PSCI_TZ_FN(n) (ARM_PSCI_TZ_FN_BASE + (n))
|
||||
|
||||
#define ARM_PSCI_TZ_FN_CPU_OFF ARM_PSCI_TZ_FN(2)
|
||||
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
|
||||
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
|
||||
#define ARM_PSCI_TZ_FN_CPU_OFF ARM_PSCI_TZ_FN(2)
|
||||
#define ARM_PSCI_TZ_FN_CPU_ON ARM_PSCI_TZ_FN(3)
|
||||
#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
|
||||
|
||||
/*
|
||||
* GCC-QPIC Registers
|
||||
*/
|
||||
#define GCC_QPIC_IO_MACRO_CBCR 0x183200C
|
||||
#define GCC_QPIC_CBCR_ADDR 0x1832014
|
||||
#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010
|
||||
#define GCC_QPIC_SLEEP_CBCR 0x1832018
|
||||
#define QPIC_CBCR_VAL 0x80004FF1
|
||||
#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004
|
||||
#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008
|
||||
#define IO_MACRO_CLK_320_MHZ 320000000
|
||||
#define IO_MACRO_CLK_266_MHZ 266000000
|
||||
#define IO_MACRO_CLK_228_MHZ 228000000
|
||||
#define IO_MACRO_CLK_200_MHZ 200000000
|
||||
#define IO_MACRO_CLK_100_MHZ 100000000
|
||||
#define IO_MACRO_CLK_24MHZ 24000000
|
||||
#define QPIC_IO_MACRO_CLK 0
|
||||
#define QPIC_CORE_CLK 1
|
||||
#define XO_CLK_SRC 2
|
||||
#define GPLL0_CLK_SRC 3
|
||||
#define FB_CLK_BIT (1 << 4)
|
||||
#define UPDATE_EN 0x1
|
||||
#define QPIC_CBCR_VAL 0x80004FF1
|
||||
|
||||
/*
|
||||
* GCC-SDCC Registers
|
||||
*/
|
||||
#define GCC_SDCC1_APPS_CBCR 0x183302C
|
||||
#define GCC_SDCC1_APPS_CFG_RCGR 0x1833008
|
||||
#define GCC_SDCC1_APPS_CMD_RCGR 0x1833004
|
||||
#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL (2 << 8)
|
||||
#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV (0xB << 0)
|
||||
#define GCC_SDCC1_APPS_M 0x183300C
|
||||
#define GCC_SDCC1_APPS_N 0x1833010
|
||||
#define GCC_SDCC1_APPS_D 0x1833014
|
||||
#define SDCC1_M_VAL 0x1
|
||||
#define SDCC1_N_VAL 0xFC
|
||||
#define SDCC1_D_VAL 0xFD
|
||||
|
||||
#define GCC_SDCC1_BCR 0x1833000
|
||||
#define GCC_SDCC1_AHB_CBCR 0x1833034
|
||||
|
||||
#define PSCI_RESET_SMC_ID 0x84000009
|
||||
#define PSCI_RESET_SMC_ID 0x84000009
|
||||
|
||||
#define set_mdelay_clearbits_le32(addr, value, delay) \
|
||||
setbits_le32(addr, value); \
|
||||
|
|
@ -112,63 +78,25 @@
|
|||
clrbits_le32(addr, value); \
|
||||
|
||||
/* USB Registers */
|
||||
#define SW_COLLAPSE_ENABLE (1 << 0)
|
||||
#define SW_OVERRIDE_ENABLE (1 << 2)
|
||||
#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
|
||||
#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
|
||||
#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0xb << 0)
|
||||
#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
|
||||
#define GCC_USB0_MASTER_CBCR 0x182C044
|
||||
#define GCC_USB0_SLEEP_CBCR 0x182C058
|
||||
#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
|
||||
#define GCC_USB_MOCK_UTMI_SRC_SEL (0 << 8)
|
||||
#define GCC_USB_MOCK_UTMI_SRC_DIV (1 << 0)
|
||||
#define UTMI_M 0x1
|
||||
#define UTMI_N 0xf7
|
||||
#define UTMI_D 0xf6
|
||||
#define GCC_USB0_MOCK_UTMI_M 0x182C034
|
||||
#define GCC_USB0_MOCK_UTMI_N 0x182C038
|
||||
#define GCC_USB0_MOCK_UTMI_D 0x182C03C
|
||||
#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
|
||||
#define GCC_USB0_MOCK_UTMI_CBCR 0x182C04C
|
||||
#define GCC_USB0_PHY_PIPE_MISC 0x182C074
|
||||
#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
|
||||
#define GCC_USB0_AUX_CBCR 0x182C048
|
||||
#define GCC_USB0_PIPE_CBCR 0x182C054
|
||||
#define GCC_USB_0_BOOT_CLOCK_CTL 0x182C060
|
||||
#define GCC_USB_BCR 0x182C000
|
||||
#define GCC_QUSB2_0_PHY_BCR 0x182C068
|
||||
#define GCC_USB0_PHY_BCR 0x182C06C
|
||||
#define GCC_USB3PHY_0_PHY_BCR 0x182C070
|
||||
#define USB30_1_GUCTL 0x8A0C12C
|
||||
#define USB30_1_FLADJ 0x8A0C630
|
||||
#define USB30_PHY_1_QUSB2PHY_BASE 0x7B000
|
||||
#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
|
||||
#define GCC_USB0_AUX_CMD_RCGR 0x182C018
|
||||
#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
|
||||
#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
|
||||
#define GCC_USB0_AUX_CFG_SRC_DIV (0 << 0)
|
||||
#define GCC_USB0_AUX_M 0x182C020
|
||||
#define GCC_USB0_AUX_N 0x182C024
|
||||
#define GCC_USB0_AUX_D 0x182C028
|
||||
#define AUX_M 0x0
|
||||
#define AUX_N 0x0
|
||||
#define AUX_D 0x0
|
||||
|
||||
#define USB30_PHY_1_QUSB2PHY_BASE 0x7B000
|
||||
#define USB30_PHY_1_USB3PHY_AHB2PHY_BASE 0x7D000
|
||||
#define USB3_PHY_POWER_DOWN_CONTROL 0x804
|
||||
|
||||
#define USB3_PHY_POWER_DOWN_CONTROL 0x804
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL 0xac
|
||||
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
|
||||
#define QSERDES_COM_CLK_SELECT 0x174
|
||||
#define QSERDES_COM_BG_TRIM 0x70
|
||||
#define USB30_1_GUCTL 0x8A0C12C
|
||||
#define USB30_1_FLADJ 0x8A0C630
|
||||
|
||||
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL 0xac
|
||||
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
|
||||
#define QSERDES_COM_CLK_SELECT 0x174
|
||||
#define QSERDES_COM_BG_TRIM 0x70
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x440
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
|
||||
#define QSERDES_COM_HSCLK_SEL 0x178
|
||||
#define QSERDES_COM_CMN_CONFIG 0x194
|
||||
#define QSERDES_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_COM_SYS_CLK_CTRL 0x3c
|
||||
#define QSERDES_COM_DEC_START_MODE0 0xd0
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
|
||||
#define QSERDES_COM_HSCLK_SEL 0x178
|
||||
#define QSERDES_COM_CMN_CONFIG 0x194
|
||||
#define QSERDES_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_COM_SYS_CLK_CTRL 0x3c
|
||||
#define QSERDES_COM_DEC_START_MODE0 0xd0
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xdc
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xe0
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xe4
|
||||
|
|
@ -228,7 +156,8 @@
|
|||
#define QSERDES_RX_SIGDET_ENABLES 0x510
|
||||
#define USB3_PHY_START_CONTROL 0x808
|
||||
#define USB3_PHY_SW_RESET 0x800
|
||||
#define NOC_HANDSHAKE_FSM_EN (1 << 15)
|
||||
#define NOC_HANDSHAKE_FSM_EN (1 << 15)
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_IPQ
|
||||
void board_pci_init(int id);
|
||||
|
|
@ -319,8 +248,6 @@ int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
|
|||
int smem_ram_ptable_init_v2(struct usable_ram_partition_table *usable_ram_partition_table);
|
||||
void reset_crashdump(void);
|
||||
void reset_board(void);
|
||||
void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
|
||||
int req_clk_src_type);
|
||||
|
||||
typedef enum {
|
||||
SMEM_SPINLOCK_ARRAY = 7,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue