mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
AU_LINUX_QSDK_FIG_TARGET_ALL.12.0.000.818
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAmGlMKAACgkQoUgPZYCpAfHA5gCguluFwsFIYsm3gl5l0BBrId8c HfwAnjQ82ZpAJJ7SpVbI9CTlHgW3a7An =EyHt -----END PGP SIGNATURE----- Merge AU_LINUX_QSDK_FIG_TARGET_ALL.12.0.000.818 on remote branch Change-Id: I1719455d53dda13668de3175f170ce69b15e025e Signed-off-by: Linux Build Service Account <lnxbuild@localhost>
This commit is contained in:
Linux Build Service Account
commit
bd898eb759
15 changed files with 224 additions and 124 deletions
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@ -37,6 +37,10 @@
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <4>;
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rd_pipe_0 = <5>;
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wr_pipe_1 = <6>;
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rd_pipe_1 = <7>;
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wr_pipe_2 = <8>;
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rd_pipe_2 = <9>;
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status = "ok";
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spi_gpio {
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blsp0_spi_clk {
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@ -81,6 +81,17 @@
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <12>;
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rd_pipe_0 = <13>;
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wr_pipe_1 = <14>;
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rd_pipe_1 = <15>;
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wr_pipe_2 = <16>;
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rd_pipe_2 = <17>;
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wr_pipe_3 = <18>;
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rd_pipe_3 = <19>;
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wr_pipe_4 = <20>;
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rd_pipe_4 = <21>;
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wr_pipe_5 = <22>;
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rd_pipe_5 = <23>;
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spi_gpio {
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gpio1 {
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gpio = <38>;
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@ -61,6 +61,17 @@
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <12>;
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rd_pipe_0 = <13>;
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wr_pipe_1 = <14>;
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rd_pipe_1 = <15>;
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wr_pipe_2 = <16>;
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rd_pipe_2 = <17>;
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wr_pipe_3 = <18>;
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rd_pipe_3 = <19>;
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wr_pipe_4 = <20>;
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rd_pipe_4 = <21>;
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wr_pipe_5 = <22>;
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rd_pipe_5 = <23>;
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};
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nand: nand-controller@79B0000 {
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@ -88,6 +88,16 @@
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <12>;
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rd_pipe_0 = <13>;
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wr_pipe_1 = <14>;
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rd_pipe_1 = <15>;
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wr_pipe_2 = <16>;
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rd_pipe_2 = <17>;
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wr_pipe_3 = <18>;
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rd_pipe_3 = <19>;
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wr_pipe_4 = <20>;
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rd_pipe_4 = <21>;
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wr_pipe_5 = <22>;
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rd_pipe_5 = <23>;
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status = "ok";
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spi_gpio {
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};
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@ -531,6 +531,19 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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if (argc < 2)
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return CMD_RET_USAGE;
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#ifdef CONFIG_QSPI_LAYOUT_SWITCH
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if (strcmp(argv[1], "exit") == 0) {
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if (ubi_initialized) {
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printf("!! Detaching UBI partition\n");
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ubi_exit();
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del_mtd_partitions(ubi_dev.mtd_info);
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put_mtd_device(ubi_dev.mtd_info);
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ubi_initialized = 0;
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}
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return 0;
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}
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#endif
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if (strcmp(argv[1], "part") == 0) {
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const char *vid_header_offset = NULL;
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22
common/usb.c
22
common/usb.c
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@ -46,6 +46,8 @@
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#define TRANSCEND_USB_VENDOR_ID 0x8564
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#define TRANSCEND_USB_PRODUCT_ID 0x1000
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#define SP_USB_VENDOR_ID 0x058f
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#define SP_USB_PRODUCT_ID 0x6387
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static int asynch_allowed;
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char usb_started; /* flag for the started/stopped USB status */
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@ -1091,18 +1093,22 @@ int usb_select_config(struct usb_device *dev)
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le16_to_cpus(&dev->descriptor.idProduct);
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le16_to_cpus(&dev->descriptor.bcdDevice);
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/*The Transcend device fails for get configuration length. Adding
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delay about 10 micro secs to fix this.*/
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if (dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
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dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID)
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/*The Transcend and Silicon-power devices fails for get configuration length.
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Adding delay about 10 micro secs to fix this.*/
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if ((dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
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dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID) ||
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(dev->descriptor.idVendor == SP_USB_VENDOR_ID &&
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dev->descriptor.idProduct == SP_USB_PRODUCT_ID))
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udelay(10);
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/* only support for one config for now */
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err = usb_get_configuration_len(dev, 0);
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/*The Transcend device fails for get configuration number. Adding
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delay about 10 micro secs to fix this.*/
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if (dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
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dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID)
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/*The Transcend and Silicon-power devices fails for get configuration number.
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Adding delay about 10 micro secs to fix this.*/
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if ((dev->descriptor.idVendor == TRANSCEND_USB_VENDOR_ID &&
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dev->descriptor.idProduct == TRANSCEND_USB_PRODUCT_ID) ||
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(dev->descriptor.idVendor == SP_USB_VENDOR_ID &&
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dev->descriptor.idProduct == SP_USB_PRODUCT_ID))
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udelay(10);
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if (err >= 0) {
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@ -49,6 +49,16 @@ typedef unsigned long addr_t;
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static uint32_t hw_ver;
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unsigned int qpic_training_offset = 0;
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#ifdef CONFIG_QSPI_LAYOUT_SWITCH
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enum qpic_nand_layout {
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QPIC_NAND_LAYOUT_SBL,
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QPIC_NAND_LAYOUT_LINUX,
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QPIC_NAND_LAYOUT_MAX
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};
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enum qpic_nand_layout qpic_layout = QPIC_NAND_LAYOUT_LINUX;
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#endif
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#ifdef CONFIG_QPIC_SERIAL
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static struct qpic_serial_nand_params qpic_serial_nand_tbl[] = {
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{
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@ -940,6 +950,10 @@ static void qpic_serial_update_dev_params(struct mtd_info *mtd)
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uint32_t ecc_bits;
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dev->page_size = serial_params->page_size;
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#ifdef CONFIG_QSPI_LAYOUT_SWITCH
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if (serial_params->page_size == 4096 && qpic_layout == QPIC_NAND_LAYOUT_SBL)
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dev->page_size = 2048;
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#endif
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mtd->writesize = dev->page_size;
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dev->block_size = serial_params->pgs_per_blk * (dev->page_size);
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mtd->erasesize = dev->block_size;
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@ -4699,8 +4713,19 @@ void qpic_nand_init(qpic_nand_cfg_t *qpic_nand_cfg)
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buf += mtd->oobsize;
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#ifdef CONFIG_QSPI_SERIAL_TRAINING
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/* start serial training here */
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#ifdef CONFIG_QSPI_LAYOUT_SWITCH
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if (qpic_layout != QPIC_NAND_LAYOUT_SBL)
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ret = qpic_execute_serial_training(mtd);
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else {
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ret = 0;
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printf("!! Skip serial traning in SBL layout\n");
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}
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#else
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ret = qpic_execute_serial_training(mtd);
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#endif
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if (ret) {
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printf("Error in serial training.\n");
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printf("switch back to 50MHz with feed back clock bit enabled\n");
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@ -5125,3 +5150,65 @@ void Read_onfi_ParameterPage_DataStructure(unsigned char *ParPage, int size)
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printf("512-767 bytes are value of bytes 0-255\n");
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}
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#endif
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#ifdef CONFIG_QSPI_LAYOUT_SWITCH
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static int qpic_nand_deinit(void)
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{
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int ret = 0;
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struct mtd_info *mtd = &nand_info[CONFIG_QPIC_NAND_NAND_INFO_IDX];
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struct qpic_nand_dev *dev = MTD_QPIC_NAND_DEV(mtd);
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if (run_command("ubi exit", 0) != CMD_RET_SUCCESS)
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return CMD_RET_FAILURE;
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#ifdef CONFIG_MTD_DEVICE
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ret = del_mtd_device(mtd);
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if (ret < 0)
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return ret;
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#endif
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dev->cfg0 = 0;
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dev->cfg1 = 0;
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dev->ecc_bch_cfg = 0;
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free(dev->buffers);
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return ret;
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}
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static int do_qpic_nand_cmd(cmd_tbl_t *cmdtp, int flag,
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int argc, char * const argv[])
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{
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int ret;
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if (argc != 2 || serial_params->page_size == 2048)
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return CMD_RET_USAGE;
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if (strcmp(argv[1], "sbl") == 0) {
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if (qpic_layout == QPIC_NAND_LAYOUT_SBL) {
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printf("Already in sbl layout\n");
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return CMD_RET_SUCCESS;
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}
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qpic_layout = QPIC_NAND_LAYOUT_SBL;
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} else if (strcmp(argv[1], "linux") == 0) {
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if (qpic_layout == QPIC_NAND_LAYOUT_LINUX) {
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printf("Already in linux layout\n");
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return CMD_RET_SUCCESS;
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}
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qpic_layout = QPIC_NAND_LAYOUT_LINUX;
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} else
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return CMD_RET_USAGE;
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ret = qpic_nand_deinit();
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if (ret < 0)
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return CMD_RET_FAILURE;
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nand_curr_device = -1;
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qpic_nand_init(NULL);
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(qpic_nand, 2, 1, do_qpic_nand_cmd,
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"Switch between SBL and Linux kernel page on 4K NAND Flash.",
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"qpic_nand (sbl | linux)");
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#endif
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@ -40,8 +40,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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static unsigned int read_pipe[NO_OF_QUPS];
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static unsigned int write_pipe[NO_OF_QUPS];
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static unsigned int read_pipe[CONFIG_IPQ_MAX_BLSP_QUPS];
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static unsigned int write_pipe[CONFIG_IPQ_MAX_BLSP_QUPS];
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static unsigned char qup_pipe_initialized = 0;
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static int check_bit_state(uint32_t reg_addr, int bit_num, int val,
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@ -177,7 +177,7 @@ static void qup_pipe_init(void)
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qup_pipe_initialized = 1;
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node = fdt_path_offset(gd->fdt_blob, "/spi");
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if (node >= 0) {
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for(i = 0; i < NO_OF_QUPS; i++) {
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for(i = 0; i < CONFIG_IPQ_MAX_BLSP_QUPS; i++) {
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snprintf(rd_pipe_name, sizeof(rd_pipe_name),
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"rd_pipe_%01d", i);
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@ -352,19 +352,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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memset(ds, 0, sizeof(struct ipq_spi_slave));
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/*
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* QCA BLSP supports SPI Flash
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* on different BLSP0 and BLSP1
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* on different BLSP 0 to CONFIG_IPQ_MAX_BLSP_QUPS-1
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* with different number of chip selects (CS, channels):
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*/
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if ((bus > BLSP1_SPI)
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|| ((bus == BLSP0_SPI) && (cs > 2))
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|| ((bus == BLSP1_SPI) && (cs > 0))) {
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if (bus >= CONFIG_IPQ_MAX_BLSP_QUPS){
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printf("SPI error: unsupported bus %d "
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"(Supported busses 0,1 and 2) or chipselect\n", bus);
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"Supported busses 0 to %d\n", bus, CONFIG_IPQ_MAX_BLSP_QUPS-1);
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goto err;
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}
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ds->slave.bus = bus;
|
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ds->slave.cs = cs;
|
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|
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BLSP_SPI_REGISTERS(spi_reg[bus]);
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|
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ds->regs = &spi_reg[bus];
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|
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/* TODO For different clock frequency */
|
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|
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@ -384,7 +384,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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/* DMA mode */
|
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ds->use_dma = CONFIG_QUP_SPI_USE_DMA;
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if (ds->slave.cs == 1 &&
|
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if (ds->slave.cs >= 1 &&
|
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cs_is_valid(ds->slave.bus, ds->slave.cs)) {
|
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/* GPIO Configuration for SPI NAND */
|
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blsp_pin_config(ds->slave.bus, ds->slave.cs);
|
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|
|
|
|||
|
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@ -31,73 +31,51 @@
|
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#ifndef _IPQ_SPI_BAM_H_
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#define _IPQ_SPI_BAM_H_
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|
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#define QUP0_BASE 0x78b5000
|
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#define QUP1_BASE 0x78b6000
|
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#define QUP_BASE 0x78b5000
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#define BLSP0_BAM_BASE 0x7884000
|
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|
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#define BLSP0_QUP_REG_BASE (QUP0_BASE + 0x00000000)
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#define BLSP1_QUP_REG_BASE (QUP1_BASE + 0x00000000)
|
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#define BLSP_QUP_REG_BASE(p) (QUP_BASE + (p*0x1000) )
|
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|
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#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300)
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#define BLSP1_SPI_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000300)
|
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#define BLSP_SPI_CONFIG_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000300)
|
||||
|
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#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304)
|
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#define BLSP1_SPI_IO_CONTROL_REG (BLSP1_QUP_REG_BASE + 0x00000304)
|
||||
#define BLSP_SPI_IO_CONTROL_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000304)
|
||||
|
||||
#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308)
|
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#define BLSP1_SPI_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x00000308)
|
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#define BLSP_SPI_ERROR_FLAGS_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000308)
|
||||
|
||||
#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310)
|
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#define BLSP1_SPI_DEASSERT_WAIT_REG (BLSP1_QUP_REG_BASE + 0x00000310)
|
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#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c)
|
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#define BLSP1_SPI_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x0000030c)
|
||||
#define BLSP_SPI_DEASSERT_WAIT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000310)
|
||||
|
||||
#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000)
|
||||
#define BLSP1_QUP_CONFIG_REG (BLSP1_QUP_REG_BASE + 0x00000000)
|
||||
#define BLSP_SPI_ERROR_FLAGS_EN_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000030c)
|
||||
|
||||
#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c)
|
||||
#define BLSP1_QUP_ERROR_FLAGS_REG (BLSP1_QUP_REG_BASE + 0x0000001c)
|
||||
#define BLSP_QUP_CONFIG_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000000)
|
||||
|
||||
#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020)
|
||||
#define BLSP1_QUP_ERROR_FLAGS_EN_REG (BLSP1_QUP_REG_BASE + 0x00000020)
|
||||
#define BLSP_QUP_ERROR_FLAGS_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000001c)
|
||||
|
||||
#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028)
|
||||
#define BLSP1_QUP_OPERATIONAL_MASK (BLSP1_QUP_REG_BASE + 0x00000028)
|
||||
#define BLSP_QUP_ERROR_FLAGS_EN_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000020)
|
||||
|
||||
#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018)
|
||||
#define BLSP1_QUP_OPERATIONAL_REG (BLSP1_QUP_REG_BASE + 0x00000018)
|
||||
#define BLSP_QUP_OPERATIONAL_MASK(p) (BLSP_QUP_REG_BASE(p) + 0x00000028)
|
||||
|
||||
#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008)
|
||||
#define BLSP1_QUP_IO_MODES_REG (BLSP1_QUP_REG_BASE + 0x00000008)
|
||||
#define BLSP_QUP_OPERATIONAL_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000018)
|
||||
|
||||
#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004)
|
||||
#define BLSP1_QUP_STATE_REG (BLSP1_QUP_REG_BASE + 0x00000004)
|
||||
#define BLSP_QUP_IO_MODES_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000008)
|
||||
|
||||
#define BLSP_QUP_STATE_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000004)
|
||||
|
||||
#define BLSP0_QUP_INPUT_FIFOc_REG(c) \
|
||||
(BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c))
|
||||
#define BLSP1_QUP_INPUT_FIFOc_REG(c) \
|
||||
(BLSP1_QUP_REG_BASE + 0x00000218 + 4 * (c))
|
||||
#define BLSP_QUP_INPUT_FIFOc_REG(p, c) \
|
||||
(BLSP_QUP_REG_BASE(p) + 0x00000218 + 4 * (c))
|
||||
|
||||
#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \
|
||||
(BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c))
|
||||
#define BLSP1_QUP_OUTPUT_FIFOc_REG(c) \
|
||||
(BLSP1_QUP_REG_BASE + 0x00000110 + 4 * (c))
|
||||
#define BLSP_QUP_OUTPUT_FIFOc_REG(p, c) \
|
||||
(BLSP_QUP_REG_BASE(p) + 0x00000110 + 4 * (c))
|
||||
|
||||
#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200)
|
||||
#define BLSP1_QUP_MX_INPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000200)
|
||||
#define BLSP_QUP_MX_INPUT_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000200)
|
||||
|
||||
#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100)
|
||||
#define BLSP1_QUP_MX_OUTPUT_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000100)
|
||||
#define BLSP_QUP_MX_OUTPUT_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000100)
|
||||
|
||||
#define BLSP0_QUP_MX_READ_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000208)
|
||||
#define BLSP1_QUP_MX_READ_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000208)
|
||||
#define BLSP_QUP_MX_READ_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000208)
|
||||
|
||||
#define BLSP0_QUP_MX_WRITE_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000150)
|
||||
#define BLSP1_QUP_MX_WRITE_COUNT_REG (BLSP1_QUP_REG_BASE + 0x00000150)
|
||||
#define BLSP_QUP_MX_WRITE_COUNT_REG(p) (BLSP_QUP_REG_BASE(p) + 0x00000150)
|
||||
|
||||
#define BLSP_QUP_SW_RESET_REG(p) (BLSP_QUP_REG_BASE(p) + 0x0000000C)
|
||||
|
||||
#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c)
|
||||
#define BLSP1_QUP_SW_RESET_REG (BLSP1_QUP_REG_BASE + 0x0000000c)
|
||||
|
||||
#define QUP_STATE_VALID_BIT 2
|
||||
#define QUP_STATE_VALID 1
|
||||
|
|
@ -191,52 +169,28 @@ struct blsp_spi {
|
|||
unsigned int qup_deassert_wait;
|
||||
};
|
||||
|
||||
static const struct blsp_spi spi_reg[] = {
|
||||
/* BLSP0 registers for SPI interface */
|
||||
{
|
||||
BLSP0_SPI_CONFIG_REG,
|
||||
BLSP0_SPI_IO_CONTROL_REG,
|
||||
BLSP0_SPI_ERROR_FLAGS_REG,
|
||||
BLSP0_SPI_ERROR_FLAGS_EN_REG,
|
||||
BLSP0_QUP_CONFIG_REG,
|
||||
BLSP0_QUP_ERROR_FLAGS_REG,
|
||||
BLSP0_QUP_ERROR_FLAGS_EN_REG,
|
||||
BLSP0_QUP_OPERATIONAL_REG,
|
||||
BLSP0_QUP_IO_MODES_REG,
|
||||
BLSP0_QUP_STATE_REG,
|
||||
BLSP0_QUP_INPUT_FIFOc_REG(0),
|
||||
BLSP0_QUP_OUTPUT_FIFOc_REG(0),
|
||||
BLSP0_QUP_MX_INPUT_COUNT_REG,
|
||||
BLSP0_QUP_MX_OUTPUT_COUNT_REG,
|
||||
BLSP0_QUP_MX_READ_COUNT_REG,
|
||||
BLSP0_QUP_MX_WRITE_COUNT_REG,
|
||||
BLSP0_QUP_SW_RESET_REG,
|
||||
BLSP0_QUP_OPERATIONAL_MASK,
|
||||
BLSP0_SPI_DEASSERT_WAIT_REG,
|
||||
},
|
||||
/* BLSP1 registers for SPI interface */
|
||||
{
|
||||
BLSP1_SPI_CONFIG_REG,
|
||||
BLSP1_SPI_IO_CONTROL_REG,
|
||||
BLSP1_SPI_ERROR_FLAGS_REG,
|
||||
BLSP1_SPI_ERROR_FLAGS_EN_REG,
|
||||
BLSP1_QUP_CONFIG_REG,
|
||||
BLSP1_QUP_ERROR_FLAGS_REG,
|
||||
BLSP1_QUP_ERROR_FLAGS_EN_REG,
|
||||
BLSP1_QUP_OPERATIONAL_REG,
|
||||
BLSP1_QUP_IO_MODES_REG,
|
||||
BLSP1_QUP_STATE_REG,
|
||||
BLSP1_QUP_INPUT_FIFOc_REG(0),
|
||||
BLSP1_QUP_OUTPUT_FIFOc_REG(0),
|
||||
BLSP1_QUP_MX_INPUT_COUNT_REG,
|
||||
BLSP1_QUP_MX_OUTPUT_COUNT_REG,
|
||||
BLSP1_QUP_MX_READ_COUNT_REG,
|
||||
BLSP1_QUP_MX_WRITE_COUNT_REG,
|
||||
BLSP1_QUP_SW_RESET_REG,
|
||||
BLSP1_QUP_OPERATIONAL_MASK,
|
||||
BLSP1_SPI_DEASSERT_WAIT_REG,
|
||||
},
|
||||
};
|
||||
struct blsp_spi spi_reg[CONFIG_IPQ_MAX_BLSP_QUPS];
|
||||
|
||||
#define BLSP_SPI_REGISTERS(x) \
|
||||
x.spi_config = BLSP_SPI_CONFIG_REG(bus);\
|
||||
x.io_control = BLSP_SPI_IO_CONTROL_REG(bus);\
|
||||
x.error_flags = BLSP_SPI_ERROR_FLAGS_REG(bus);\
|
||||
x.error_flags_en = BLSP_SPI_ERROR_FLAGS_EN_REG(bus);\
|
||||
x.qup_config = BLSP_QUP_CONFIG_REG(bus);\
|
||||
x.qup_error_flags = BLSP_QUP_ERROR_FLAGS_REG(bus);\
|
||||
x.qup_error_flags_en = BLSP_QUP_ERROR_FLAGS_EN_REG(bus);\
|
||||
x.qup_operational = BLSP_QUP_OPERATIONAL_REG(bus);\
|
||||
x.qup_io_modes = BLSP_QUP_IO_MODES_REG(bus);\
|
||||
x.qup_state = BLSP_QUP_STATE_REG(bus);\
|
||||
x.qup_input_fifo = BLSP_QUP_INPUT_FIFOc_REG(bus, 0);\
|
||||
x.qup_output_fifo = BLSP_QUP_OUTPUT_FIFOc_REG(bus, 0);\
|
||||
x.qup_mx_input_count = BLSP_QUP_MX_INPUT_COUNT_REG(bus);\
|
||||
x.qup_mx_output_count = BLSP_QUP_MX_OUTPUT_COUNT_REG(bus);\
|
||||
x.qup_mx_read_count = BLSP_QUP_MX_READ_COUNT_REG(bus);\
|
||||
x.qup_mx_write_count = BLSP_QUP_MX_WRITE_COUNT_REG(bus);\
|
||||
x.qup_sw_reset = BLSP_QUP_SW_RESET_REG(bus);\
|
||||
x.qup_op_mask = BLSP_QUP_OPERATIONAL_MASK(bus);\
|
||||
x.qup_deassert_wait = BLSP_SPI_DEASSERT_WAIT_REG(bus);\
|
||||
|
||||
#define SUCCESS 0
|
||||
#define FAILURE 1
|
||||
|
|
@ -268,14 +222,6 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
|
|||
#define DATA_CONSUMER_PIPE_INDEX 0
|
||||
#define DATA_PRODUCER_PIPE_INDEX 1
|
||||
|
||||
/* QUP0 BAM pipe numbers */
|
||||
#define QUP0_DATA_CONSUMER_PIPE 12
|
||||
#define QUP0_DATA_PRODUCER_PIPE 13
|
||||
|
||||
/* QUP1 BAM pipe numbers */
|
||||
#define QUP1_DATA_CONSUMER_PIPE 6
|
||||
#define QUP1_DATA_PRODUCER_PIPE 7
|
||||
|
||||
/* QUP0 BAM pipe groups */
|
||||
#define QUP0_DATA_PRODUCER_PIPE_GRP 0
|
||||
#define QUP0_DATA_CONSUMER_PIPE_GRP 0
|
||||
|
|
@ -284,8 +230,6 @@ static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave)
|
|||
#define QUP1_DATA_PRODUCER_PIPE_GRP 0
|
||||
#define QUP1_DATA_CONSUMER_PIPE_GRP 0
|
||||
|
||||
#define NO_OF_QUPS 2
|
||||
|
||||
/* QUP EE */
|
||||
#define QUP_SPI_EE 0
|
||||
|
||||
|
|
|
|||
|
|
@ -199,6 +199,7 @@ typedef struct {
|
|||
#define CONFIG_SYS_MAX_NAND_DEVICE (CONFIG_IPQ_MAX_NAND_DEVICE + \
|
||||
CONFIG_IPQ_MAX_SPI_DEVICE)
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 2
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 2
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
|
||||
|
|
|
|||
|
|
@ -294,6 +294,7 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 3
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
|
|
|
|||
|
|
@ -248,7 +248,7 @@ extern loff_t board_env_size;
|
|||
CONFIG_IPQ_MAX_SPI_DEVICE
|
||||
|
||||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
|
||||
#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
|
||||
|
|
|
|||
|
|
@ -214,6 +214,7 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
|
|
|
|||
|
|
@ -207,6 +207,7 @@ extern loff_t board_env_size;
|
|||
#endif /* QSPI DEBUG */
|
||||
#define CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
|
||||
#define CONFIG_QSPI_SERIAL_TRAINING
|
||||
#define CONFIG_QSPI_LAYOUT_SWITCH
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -219,6 +220,7 @@ extern loff_t board_env_size;
|
|||
#define CONFIG_IPQ_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_IPQ_MAX_SPI_DEVICE 1
|
||||
|
||||
#define CONFIG_IPQ_MAX_BLSP_QUPS 6
|
||||
#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
|
||||
#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
|
||||
|
||||
|
|
|
|||
|
|
@ -533,6 +533,9 @@ class Flash_Script(FlashScript):
|
|||
else:
|
||||
pass
|
||||
|
||||
def switch_layout_qpic(self, layout):
|
||||
self.append("qpic_nand %s" % layout)
|
||||
|
||||
its_tmpl = Template("""
|
||||
/dts-v1/;
|
||||
|
||||
|
|
@ -1098,7 +1101,13 @@ class Pack(object):
|
|||
if part_info.which_flash == 0:
|
||||
offset = part_info.offset
|
||||
script.erase(offset, part_info.length)
|
||||
if ARCH_NAME in ["ipq9574", "ipq9574_64"]:
|
||||
if self.flash_type == "nand-4k" and section_conf == "sbl1":
|
||||
script.switch_layout_qpic("sbl")
|
||||
script.write(offset, img_size)
|
||||
if ARCH_NAME in ["ipq9574", "ipq9574_64"]:
|
||||
if self.flash_type == "nand-4k" and section_conf == "sbl1":
|
||||
script.switch_layout_qpic("linux")
|
||||
else:
|
||||
offset = part_info.offset
|
||||
script.nand_write(offset, part_info.length, img_size, spi_nand)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue