mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
qca: ipq40xx: Adding board specific files
Change-Id: I367b352146ad34d1564f6f861b0dd4a902572562 Signed-off-by: Akila N <akilan@codeaurora.org>
This commit is contained in:
Akila N
parent
00a91730cf
commit
bbe6202f7c
4 changed files with 2035 additions and 0 deletions
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@ -1107,6 +1107,18 @@ extern unsigned int __machine_arch_type;
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#define MACH_TYPE_COLIBRI_T30 4493
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#define MACH_TYPE_APALIS_T30 4513
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#define MACH_TYPE_OMAPL138_LCDK 2495
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#define MACH_TYPE_IPQ40XX_AP_DK01_1_S1 0x8010200
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#define MACH_TYPE_IPQ40XX_AP_DK01_1_C1 0x8010000
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#define MACH_TYPE_IPQ40XX_AP_DK01_1_C2 0x8010100
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#define MACH_TYPE_IPQ40XX_AP_DK04_1_C1 0x8010001
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#define MACH_TYPE_IPQ40XX_AP_DK04_1_C4 0x8010301
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#define MACH_TYPE_IPQ40XX_AP_DK04_1_C2 0x8010101
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#define MACH_TYPE_IPQ40XX_AP_DK04_1_C3 0x8010201
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#define MACH_TYPE_IPQ40XX_AP_DK06_1_C1 0x8010005
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#define MACH_TYPE_IPQ40XX_AP_DK07_1_C1 0x8010006
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#define MACH_TYPE_IPQ40XX_DB_DK01_1_C1 0x1010002
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#define MACH_TYPE_IPQ40XX_DB_DK02_1_C1 0x1010003
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#define MACH_TYPE_IPQ40XX_TB832 0x1010004
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#ifdef CONFIG_ARCH_EBSA110
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# ifdef machine_arch_type
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686
board/qca/ipq40xx/ipq40xx.c
Normal file
686
board/qca/ipq40xx/ipq40xx.c
Normal file
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@ -0,0 +1,686 @@
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/*
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* Copyright (c) 2015, 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <environment.h>
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#include <configs/ipq40xx.h>
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#include "ipq40xx.h"
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#include "ipq40xx_board_param.h"
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#include <part.h>
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#include <asm/arch-ipq40xx/smem.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Don't have this as a '.bss' variable. The '.bss' and '.rel.dyn'
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* sections seem to overlap.
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*
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* $ arm-none-linux-gnueabi-objdump -h u-boot
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* . . .
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* 8 .rel.dyn 00004ba8 40630b0c 40630b0c 00038b0c 2**2
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* CONTENTS, ALLOC, LOAD, READONLY, DATA
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* 9 .bss 0000559c 40630b0c 40630b0c 00000000 2**3
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* ALLOC
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* . . .
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*
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* board_early_init_f() initializes this variable, resulting in one
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* of the relocation entries present in '.rel.dyn' section getting
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* corrupted. Hence, when relocate_code()'s 'fixrel' executes, it
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* patches a wrong address, which incorrectly modifies some global
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* variable resulting in a crash.
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*
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* Moral of the story: Global variables that are written before
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* relocate_code() gets executed cannot be in '.bss'
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*/
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board_ipq40xx_params_t *gboard_param = (board_ipq40xx_params_t *)0xbadb0ad;
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#define DLOAD_DISABLE 0x1
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#define RESERVE_ADDRESS_START 0x87B00000 /*TZAPPS, SMEM and TZ Regions */
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#define RESERVE_ADDRESS_SIZE 0x500000
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#define SET_MAGIC 0x1
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#define CLEAR_MAGIC 0x0
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#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
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#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
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#define BOOT_VERSION 0
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#define TZ_VERSION 1
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/*******************************************************
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Function description: Board specific initialization.
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I/P : None
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O/P : integer, 0 - no error.
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********************************************************/
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static board_ipq40xx_params_t *get_board_param(unsigned int machid)
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{
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unsigned int index;
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printf("machid : 0x%0x\n", machid);
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for (index = 0; index < NUM_IPQ40XX_BOARDS; index++) {
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if (machid == board_params[index].machid)
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return &board_params[index];
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}
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BUG_ON(index == NUM_IPQ40XX_BOARDS);
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printf("cdp: Invalid machine id 0x%x\n", machid);
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for (;;);
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}
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int board_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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/*
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* This function is called in the very beginning.
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* Retreive the machtype info from SMEM and map the board specific
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* parameters. Shared memory region at Dram address 0x40400000
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* contains the machine id/ board type data polulated by SBL.
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*/
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int board_early_init_f(void)
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{
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/*Retrieve the machid of the board from smem*/
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gboard_param = get_board_param(smem_get_board_platform_type());
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return 0;
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}
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void enable_caches(void)
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{
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icache_enable();
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}
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void clear_l2cache_err(void)
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{
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return;
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}
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void reset_cpu(ulong addr)
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{
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}
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int dram_init(void)
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{
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struct smem_ram_ptable rtable;
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int i;
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int mx = ARRAY_SIZE(rtable.parts);
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if (smem_ram_ptable_init(&rtable) > 0) {
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gd->ram_size = 0;
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for (i = 0; i < mx; i++) {
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if (rtable.parts[i].category == RAM_PARTITION_SDRAM &&
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rtable.parts[i].type == RAM_PARTITION_SYS_MEMORY) {
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gd->ram_size += rtable.parts[i].size;
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}
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}
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gboard_param->ddr_size = gd->ram_size;
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} else {
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gd->ram_size = gboard_param->ddr_size;
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}
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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struct flash_node_info {
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const char *compat; /* compatible string */
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int type; /* mtd flash type */
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int idx; /* flash index */
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};
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int ipq_fdt_fixup_spi_nor_params(void *blob)
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{
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int nodeoff, ret;
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qca_smem_flash_info_t sfi;
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uint32_t val;
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/* Get flash parameters from smem */
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smem_get_boot_flash(&sfi.flash_type,
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&sfi.flash_index,
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&sfi.flash_chip_select,
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&sfi.flash_block_size,
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&sfi.flash_density);
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nodeoff = fdt_node_offset_by_compatible(blob, -1, "n25q128a11");
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if (nodeoff < 0) {
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printf("ipq: fdt fixup unable to find compatible node\n");
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return nodeoff;
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}
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val = cpu_to_fdt32(sfi.flash_block_size);
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ret = fdt_setprop(blob, nodeoff, "sector-size",
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&val, sizeof(uint32_t));
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if (ret) {
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printf("%s: unable to set sector size\n", __func__);
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return -1;
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}
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val = cpu_to_fdt32(sfi.flash_density);
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ret = fdt_setprop(blob, nodeoff, "density",
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&val, sizeof(uint32_t));
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if (ret) {
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printf("%s: unable to set density\n", __func__);
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return -1;
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}
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return 0;
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}
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void ipq_fdt_mem_rsvd_fixup(void *blob)
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{
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u32 val[2], dload;
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int nodeoff, ret;
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dload = htonl(DLOAD_DISABLE);
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val[0] = htonl(RESERVE_ADDRESS_START);
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val[1] = htonl(RESERVE_ADDRESS_SIZE);
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/* Reserve only the TZ and SMEM memory region and free the rest */
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nodeoff = fdt_path_offset(blob, "/reserved-memory/rsvd2");
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if (nodeoff < 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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ret = fdt_del_node(blob, nodeoff);
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if (ret != 0) {
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debug("ipq: fdt fixup unable to delete node\n");
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return;
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}
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nodeoff = fdt_path_offset(blob, "/reserved-memory/wifi_dump");
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if (nodeoff < 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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ret = fdt_del_node(blob, nodeoff);
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if (ret != 0) {
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debug("ipq: fdt fixup unable to delete node\n");
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return;
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}
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nodeoff = fdt_path_offset(blob, "/reserved-memory/rsvd1");
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if (nodeoff < 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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ret = fdt_setprop(blob, nodeoff, "reg", val, sizeof(val));
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if (ret != 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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/* Set the dload_status to DLOAD_DISABLE */
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nodeoff = fdt_path_offset(blob, "/soc/qca,scm_restart_reason");
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if (nodeoff < 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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ret = fdt_setprop(blob, nodeoff, "dload_status", &dload, sizeof(dload));
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if (ret != 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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reset_crashdump();
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}
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void ipq_fdt_fixup_version(void *blob)
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{
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int nodeoff, ret;
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char ver[OEM_VERSION_STRING_LENGTH + VERSION_STRING_LENGTH + 1];
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nodeoff = fdt_node_offset_by_compatible(blob, -1, "qcom,ipq40xx");
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if (nodeoff < 0) {
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debug("ipq: fdt fixup unable to find compatible node\n");
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return;
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}
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if (!smem_get_build_version(ver, sizeof(ver), BOOT_VERSION)) {
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debug("BOOT Build Version: %s\n", ver);
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ret = fdt_setprop(blob, nodeoff, "boot_version",
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ver, strlen(ver));
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if (ret)
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debug("%s: unable to set Boot version\n", __func__);
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}
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if (!smem_get_build_version(ver, sizeof(ver), TZ_VERSION)) {
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debug("TZ Build Version: %s\n", ver);
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ret = fdt_setprop(blob, nodeoff, "tz_version",
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ver, strlen(ver));
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if (ret)
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debug("%s: unable to set TZ version\n", __func__);
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}
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}
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void ipq_fdt_fixup_mtdparts(void *blob, struct flash_node_info *ni)
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{
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struct mtd_device *dev;
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char *parts;
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int noff;
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parts = getenv("mtdparts");
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if (!parts)
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return;
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if (mtdparts_init() != 0)
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return;
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for (; ni->compat; ni++) {
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noff = fdt_node_offset_by_compatible(blob, -1, ni->compat);
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while (noff != -FDT_ERR_NOTFOUND) {
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dev = device_find(ni->type, ni->idx);
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if (dev) {
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if (fdt_node_set_part_info(blob, noff, dev))
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return; /* return on error */
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}
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/* Jump to next flash node */
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noff = fdt_node_offset_by_compatible(blob, noff,
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ni->compat);
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}
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}
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}
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/*
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* For newer kernel that boot with device tree (3.14+), all of memory is
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* described in the /memory node, including areas that the kernel should not be
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* touching.
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*
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* By default, u-boot will walk the dram bank info and populate the /memory
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* node; here, overwrite this behavior so we describe all of memory instead.
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*/
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void ft_board_setup(void *blob, bd_t *bd)
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{
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u64 memory_start = CONFIG_SYS_SDRAM_BASE;
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u64 memory_size = gboard_param->ddr_size;
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char *mtdparts = NULL;
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char parts_str[256];
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qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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struct flash_node_info nodes[] = {
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{ "qcom,msm-nand", MTD_DEV_TYPE_NAND, 0 },
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{ "spinand,mt29f", MTD_DEV_TYPE_NAND, 1 },
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{ "n25q128a11", MTD_DEV_TYPE_NAND, 2 },
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{ NULL, 0, -1 }, /* Terminator */
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};
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fdt_fixup_memory_banks(blob, &memory_start, &memory_size, 1);
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ipq_fdt_fixup_version(blob);
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#ifndef CONFIG_QCA_APPSBL_DLOAD
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ipq_fdt_mem_rsvd_fixup(blob);
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#endif
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if (sfi->flash_type == SMEM_BOOT_NAND_FLASH) {
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mtdparts = "mtdparts=nand0";
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} else if (sfi->flash_type == SMEM_BOOT_SPI_FLASH) {
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/* Patch NOR block size and density for
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* generic probe case */
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ipq_fdt_fixup_spi_nor_params(blob);
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if (gboard_param->spi_nand_available &&
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get_which_flash_param("rootfs") == 0) {
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sprintf(parts_str,
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"mtdparts=nand1:0x%x@0(rootfs);spi0.0",
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IPQ_NAND_ROOTFS_SIZE);
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mtdparts = parts_str;
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} else if (gboard_param->nor_nand_available &&
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get_which_flash_param("rootfs") == 0) {
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sprintf(parts_str,
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"mtdparts=nand0:0x%x@0(rootfs);spi0.0",
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IPQ_NAND_ROOTFS_SIZE);
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mtdparts = parts_str;
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} else {
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mtdparts = "mtdparts=spi0.0";
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}
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}
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if (mtdparts) {
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mtdparts = qca_smem_part_to_mtdparts(mtdparts);
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if (mtdparts != NULL) {
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debug("mtdparts = %s\n", mtdparts);
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setenv("mtdparts", mtdparts);
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}
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setenv("mtdids", gboard_param->mtdids);
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ipq_fdt_fixup_mtdparts(blob, nodes);
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}
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dcache_disable();
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ipq40xx_set_ethmac_addr();
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fdt_fixup_ethernet(blob);
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#ifdef CONFIG_QCA_MMC
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board_mmc_deinit();
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#endif
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#ifdef CONFIG_QCA_MMC
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int board_mmc_env_init(void)
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{
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block_dev_desc_t *blk_dev;
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disk_partition_t disk_info;
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int ret;
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if (mmc_init(mmc_host.mmc)) {
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/* The HS mode command(cmd6) is getting timed out. So mmc card is
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* not getting initialized properly. Since the env partition is not
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* visible, the env default values are writing into the default
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* partition (start of the mmc device). So do a reset again.
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*/
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if (mmc_init(mmc_host.mmc)) {
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printf("MMC init failed \n");
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return -1;
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}
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}
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blk_dev = mmc_get_dev(mmc_host.dev_num);
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ret = find_part_efi(blk_dev, "0:APPSBLENV", &disk_info);
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if (ret > 0) {
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board_env_offset = disk_info.start * disk_info.blksz;
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board_env_size = disk_info.size * disk_info.blksz;
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board_env_range = board_env_size;
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BUG_ON(board_env_size > CONFIG_ENV_SIZE_MAX);
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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if (!gboard_param->mmc_gpio_count)
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return 0;
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qca_configure_gpio(gboard_param->mmc_gpio,
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gboard_param->mmc_gpio_count);
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mmc_host.base = MSM_SDC1_BASE;
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mmc_host.clk_mode = MMC_IDENTIFY_MODE;
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emmc_clock_config(mmc_host.clk_mode);
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ret = qca_mmc_init(bis, &mmc_host);
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if (!ret && sfi->flash_type == SMEM_BOOT_MMC_FLASH) {
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ret = board_mmc_env_init();
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}
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|
||||
return ret;
|
||||
}
|
||||
|
||||
void board_mmc_deinit(void)
|
||||
{
|
||||
emmc_clock_disable();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IPQ40XX_PCI
|
||||
void pcie_config_gpio(pcie_params_t *cfg, int enable)
|
||||
{
|
||||
int i;
|
||||
gpio_func_data_t *gpio_data;
|
||||
gpio_data = cfg->pci_gpio;
|
||||
|
||||
for (i = 0; i < cfg->pci_gpio_count; i++) {
|
||||
if (enable)
|
||||
gpio_tlmm_config(gpio_data->gpio, gpio_data->func,
|
||||
gpio_data->out, gpio_data->pull,
|
||||
gpio_data->drvstr, gpio_data->oe,
|
||||
gpio_data->gpio_vm, gpio_data->gpio_od_en,
|
||||
gpio_data->gpio_pu_res);
|
||||
else
|
||||
gpio_tlmm_config(gpio_data->gpio, gpio_data->func,
|
||||
GPIO_OUT_LOW, GPIO_NO_PULL,
|
||||
GPIO_2MA, GPIO_OE_DISABLE,
|
||||
GPIO_VM_DISABLE, GPIO_OD_DISABLE,
|
||||
gpio_data->gpio_pu_res);
|
||||
gpio_data++;
|
||||
}
|
||||
}
|
||||
|
||||
void pcie_controller_reset(int id)
|
||||
{
|
||||
uint32_t val;
|
||||
pcie_params_t *cfg;
|
||||
cfg = &gboard_param->pcie_cfg[id];
|
||||
|
||||
/* Enable PCIE CLKS */
|
||||
pcie_clock_enable(GCC_PCIE_SLEEP_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AXI_M_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AXI_S_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AHB_CBCR);
|
||||
|
||||
/* Assert cc_pcie20_core_ares */
|
||||
writel(PCIE_RST_CTRL_PIPE_ARES, cfg->pcie_rst);
|
||||
|
||||
/* Assert cc_pcie20_core_sticky_area */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_PIPE_STICKY_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* Assert cc_pcie20_phy_ahb_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_PIPE_PHY_AHB_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
gpio_set_value(PCIE_RST_GPIO, GPIO_OUT_LOW);
|
||||
|
||||
/* Assert cc_pcie20_mstr_axi_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_AXI_M_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* Assert cc_pcie20_mstr_sticky_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_AXI_M_STICKY_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* Assert cc_pcie20_slv_axi_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_AXI_S_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* Assert cc_pcie20_ahb_ares; */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val |= PCIE_RST_CTRL_AHB_ARES;
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_phy_ahb_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_AHB_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_pciephy_phy_ares*/
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_PIPE_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_core_sticky_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_PIPE_STICKY_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
mdelay(5);
|
||||
|
||||
gpio_set_value(PCIE_RST_GPIO, GPIO_OUT_HIGH);
|
||||
|
||||
/* DeAssert cc_pcie20_mstr_axi_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_AXI_M_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_mstr_axi_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_AXI_M_STICKY_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_slv_axi_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_AXI_S_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
|
||||
/* DeAssert cc_pcie20_ahb_ares */
|
||||
val = readl(cfg->pcie_rst);
|
||||
val &= ~(PCIE_RST_CTRL_PIPE_PHY_AHB_ARES);
|
||||
writel(val, cfg->pcie_rst);
|
||||
}
|
||||
|
||||
static void ipq_pcie_config_controller(int id)
|
||||
{
|
||||
pcie_params_t *cfg;
|
||||
cfg = &gboard_param->pcie_cfg[id];
|
||||
|
||||
/*
|
||||
* program and enable address translation region 0 (device config
|
||||
* address space); region type config;
|
||||
* axi config address range to device config address range
|
||||
*/
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_VIEWPORT);
|
||||
|
||||
writel(4, cfg->pcie20 + PCIE20_PLR_IATU_CTRL1);
|
||||
writel((1 << 31), cfg->pcie20 + PCIE20_PLR_IATU_CTRL2);
|
||||
writel(cfg->axi_conf , cfg->pcie20 + PCIE20_PLR_IATU_LBAR);
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_UBAR);
|
||||
writel((cfg->axi_conf + PCIE_AXI_CONF_SIZE - 1),
|
||||
cfg->pcie20 + PCIE20_PLR_IATU_LAR);
|
||||
writel(MSM_PCIE_DEV_CFG_ADDR,
|
||||
cfg->pcie20 + PCIE20_PLR_IATU_LTAR);
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_UTAR);
|
||||
|
||||
/*
|
||||
* program and enable address translation region 2 (device resource
|
||||
* address space); region type memory;
|
||||
* axi device bar address range to device bar address range
|
||||
*/
|
||||
writel(2, cfg->pcie20 + PCIE20_PLR_IATU_VIEWPORT);
|
||||
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_CTRL1);
|
||||
writel((1 << 31), cfg->pcie20 + PCIE20_PLR_IATU_CTRL2);
|
||||
writel(cfg->axi_bar_start, cfg->pcie20 + PCIE20_PLR_IATU_LBAR);
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_UBAR);
|
||||
writel((cfg->axi_bar_start + cfg->axi_bar_size
|
||||
- PCIE_AXI_CONF_SIZE - 1), cfg->pcie20 + PCIE20_PLR_IATU_LAR);
|
||||
writel(cfg->axi_bar_start, cfg->pcie20 + PCIE20_PLR_IATU_LTAR);
|
||||
writel(0, cfg->pcie20 + PCIE20_PLR_IATU_UTAR);
|
||||
|
||||
/* 1K PCIE buffer setting */
|
||||
writel(0x3, cfg->pcie20 + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
|
||||
writel(0x1, cfg->pcie20 + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
|
||||
}
|
||||
|
||||
void pcie_linkup(int id)
|
||||
{
|
||||
int j, val;
|
||||
pcie_params_t *cfg;
|
||||
cfg = &gboard_param->pcie_cfg[id];
|
||||
|
||||
pcie_clock_enable(GCC_PCIE_SLEEP_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AXI_M_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AXI_S_CBCR);
|
||||
pcie_clock_enable(GCC_PCIE_AHB_CBCR);
|
||||
|
||||
pcie_controller_reset(id);
|
||||
mdelay(200);
|
||||
|
||||
writel(SLV_ADDR_SPACE_SZ, cfg->parf + PARF_SLV_ADDR_SPACE_SIZE);
|
||||
mdelay(100);
|
||||
|
||||
writel(0x0, cfg->pcie20 + PCIE_0_PORT_FORCE_REG);
|
||||
val = (L1_ENTRANCE_LATENCY(3) |
|
||||
L0_ENTRANCE_LATENCY(3) |
|
||||
COMMON_CLK_N_FTS(128) |
|
||||
ACK_N_FTS(128));
|
||||
writel(val, cfg->pcie20 + PCIE_0_ACK_F_ASPM_CTRL_REG);
|
||||
|
||||
val = (FAST_TRAINING_SEQ(128) |
|
||||
NUM_OF_LANES(2) |
|
||||
DIRECT_SPEED_CHANGE);
|
||||
writel(val, cfg->pcie20 + PCIE_0_GEN2_CTRL_REG);
|
||||
writel(PCI_TYPE0_BUS_MASTER_EN,
|
||||
cfg->pcie20 + PCIE_0_TYPE0_STATUS_COMMAND_REG_1);
|
||||
|
||||
writel(DBI_RO_WR_EN, cfg->pcie20 + PCIE_0_MISC_CONTROL_1_REG);
|
||||
writel(0x0002FD7F, cfg->pcie20 + 0x84);
|
||||
|
||||
val = (PCIE_CAP_ASPM_OPT_COMPLIANCE |
|
||||
PCIE_CAP_LINK_BW_NOT_CAP |
|
||||
PCIE_CAP_DLL_ACTIVE_REP_CAP |
|
||||
PCIE_CAP_L1_EXIT_LATENCY(4) |
|
||||
PCIE_CAP_L0S_EXIT_LATENCY(4) |
|
||||
PCIE_CAP_MAX_LINK_WIDTH(1) |
|
||||
PCIE_CAP_MAX_LINK_SPEED(1));
|
||||
writel(val, cfg->pcie20 + PCIE_0_LINK_CAPABILITIES_REG);
|
||||
|
||||
writel(PCIE_CAP_CPL_TIMEOUT_DISABLE,
|
||||
cfg->pcie20 + PCIE_0_DEVICE_CONTROL2_DEVICE_STATUS2_REG);
|
||||
|
||||
writel(0x10110008, cfg->pcie20 + PCIE_0_TYPE0_LINK_CONTROL_LINK_STATUS_REG_1);
|
||||
|
||||
writel(LTSSM_EN, cfg->parf + PCIE_0_PCIE20_PARF_LTSSM);
|
||||
|
||||
mdelay(200);
|
||||
|
||||
for (j = 0; j < 400; j++) {
|
||||
val = readl(cfg->pcie20 + PCIE_0_TYPE0_LINK_CONTROL_LINK_STATUS_REG_1);
|
||||
if (val & (1 << 29)) {
|
||||
printf("PCI%d Link Intialized\n", id);
|
||||
cfg->linkup = 1;
|
||||
break;
|
||||
}
|
||||
udelay(100);
|
||||
}
|
||||
ipq_pcie_config_controller(id);
|
||||
}
|
||||
|
||||
void board_pci_init()
|
||||
{
|
||||
int i;
|
||||
pcie_params_t *cfg;
|
||||
|
||||
for (i = 0; i < PCI_MAX_DEVICES; i++) {
|
||||
cfg = &gboard_param->pcie_cfg[i];
|
||||
pcie_config_gpio(cfg, ENABLE);
|
||||
|
||||
pcie_controller_reset(i);
|
||||
|
||||
pcie_linkup(i);
|
||||
}
|
||||
}
|
||||
|
||||
void board_pci_deinit(void)
|
||||
{
|
||||
int i;
|
||||
pcie_params_t *cfg;
|
||||
|
||||
for (i = 0; i < PCI_MAX_DEVICES; i++) {
|
||||
cfg = &gboard_param->pcie_cfg[i];
|
||||
|
||||
writel(1, cfg->parf + PCIE20_PARF_PHY_CTRL);
|
||||
|
||||
pcie_config_gpio(cfg, DISABLE);
|
||||
}
|
||||
|
||||
/* Disable PCIE CLKS */
|
||||
pcie_clock_disable(GCC_PCIE_SLEEP_CBCR);
|
||||
pcie_clock_disable(GCC_PCIE_AXI_M_CBCR);
|
||||
pcie_clock_disable(GCC_PCIE_AXI_S_CBCR);
|
||||
pcie_clock_disable(GCC_PCIE_AHB_CBCR);
|
||||
}
|
||||
#endif /* CONFIG_IPQ40XX_PCI */
|
||||
122
board/qca/ipq40xx/ipq40xx.h
Normal file
122
board/qca/ipq40xx/ipq40xx.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2015, 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _IPQ40XX_CDP_H_
|
||||
#define _IPQ40XX_CDP_H_
|
||||
|
||||
#include <configs/ipq40xx.h>
|
||||
#include <asm/arch-qcom-common/gpio.h>
|
||||
#include <asm/u-boot.h>
|
||||
#include <phy.h>
|
||||
|
||||
#define NO_OF_DBG_UART_GPIOS 2
|
||||
#ifdef CONFIG_IPQ40XX_I2C
|
||||
#define NO_OF_I2C_GPIOS 2
|
||||
#endif
|
||||
#define MAX_CONF_NAME 5
|
||||
|
||||
unsigned int smem_get_board_machtype(void);
|
||||
|
||||
#define IPQ40XX_EDMA_DEV 1
|
||||
typedef struct {
|
||||
uint count;
|
||||
u8 addr[7];
|
||||
} ipq40xx_edma_phy_addr_t;
|
||||
|
||||
/* ipq40xx edma Paramaters */
|
||||
typedef struct {
|
||||
uint base;
|
||||
int unit;
|
||||
uint mac_conn_to_phy;
|
||||
phy_interface_t phy;
|
||||
ipq40xx_edma_phy_addr_t phy_addr;
|
||||
const char phy_name[MDIO_NAME_LEN];
|
||||
} ipq40xx_edma_board_cfg_t;
|
||||
|
||||
typedef struct {
|
||||
int gpio;
|
||||
unsigned int func;
|
||||
unsigned int out;
|
||||
unsigned int pull;
|
||||
unsigned int drvstr;
|
||||
unsigned int oe;
|
||||
unsigned int gpio_vm;
|
||||
unsigned int gpio_od_en;
|
||||
unsigned int gpio_pu_res;
|
||||
} gpio_func_data_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned int uart_dm_base;
|
||||
gpio_func_data_t *dbg_uart_gpio;
|
||||
} uart_cfg_t;
|
||||
|
||||
#ifdef CONFIG_IPQ40XX_I2C
|
||||
typedef struct {
|
||||
unsigned int i2c_base;
|
||||
gpio_func_data_t *i2c_gpio;
|
||||
} i2c_cfg_t;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IPQ40XX_PCI
|
||||
#define PCI_MAX_DEVICES 1
|
||||
|
||||
typedef struct {
|
||||
gpio_func_data_t *pci_gpio;
|
||||
uint32_t pci_gpio_count;
|
||||
uint32_t parf;
|
||||
uint32_t elbi;
|
||||
uint32_t pcie20;
|
||||
uint32_t axi_bar_start;
|
||||
uint32_t axi_bar_size;
|
||||
uint32_t pcie_rst;
|
||||
uint32_t axi_conf;
|
||||
int linkup;
|
||||
} pcie_params_t;
|
||||
|
||||
void board_pci_init(void);
|
||||
#endif /* CONFIG_IPQ40XX_PCI */
|
||||
|
||||
/* Board specific parameters */
|
||||
typedef struct {
|
||||
unsigned int machid;
|
||||
unsigned int ddr_size;
|
||||
const char *mtdids;
|
||||
gpio_func_data_t *spi_nor_gpio;
|
||||
unsigned int spi_nor_gpio_count;
|
||||
gpio_func_data_t *nand_gpio;
|
||||
unsigned int nand_gpio_count;
|
||||
gpio_func_data_t *sw_gpio;
|
||||
unsigned int sw_gpio_count;
|
||||
gpio_func_data_t *rgmii_gpio;
|
||||
unsigned int rgmii_gpio_count;
|
||||
ipq40xx_edma_board_cfg_t edma_cfg[IPQ40XX_EDMA_DEV];
|
||||
uart_cfg_t *uart_cfg;
|
||||
uart_cfg_t *console_uart_cfg;
|
||||
#ifdef CONFIG_IPQ40XX_I2C
|
||||
i2c_cfg_t *i2c_cfg;
|
||||
#endif
|
||||
gpio_func_data_t *mmc_gpio;
|
||||
unsigned int mmc_gpio_count;
|
||||
unsigned int spi_nand_available;
|
||||
unsigned int nor_nand_available;
|
||||
unsigned int nor_emmc_available;
|
||||
#ifdef CONFIG_IPQ40XX_PCI
|
||||
pcie_params_t pcie_cfg[PCI_MAX_DEVICES];
|
||||
#endif
|
||||
const char *dtb_config_name[MAX_CONF_NAME];
|
||||
} __attribute__ ((__packed__)) board_ipq40xx_params_t;
|
||||
|
||||
extern board_ipq40xx_params_t *gboard_param;
|
||||
unsigned int get_board_index(unsigned int machid);
|
||||
|
||||
#endif
|
||||
1215
board/qca/ipq40xx/ipq40xx_board_param.h
Normal file
1215
board/qca/ipq40xx/ipq40xx_board_param.h
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue