mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-03 07:54:24 +01:00
ipq807x: Added clock support
The clock routines specific to ipq807x will live in clock.c. Change-Id: I4bb0b5a28ff95d08fab7913ca89ffbe1882ba72f Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
This commit is contained in:
Ajay Kishore
parent
37ddd8e488
commit
ba15b4493a
4 changed files with 13 additions and 267 deletions
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@ -1,3 +1,3 @@
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obj-y := ipq807x.o
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obj-y += clock.o
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@ -14,87 +14,9 @@
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#ifndef QCA_CLK_H
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#define QCA_CLK_H
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#define MMC_IDENTIFY_MODE 0
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#define MMC_DATA_TRANSFER_MODE 1
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#define GCC_BLSP1_UART2_APPS_CFG_RCGR 0x01803038
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#define GCC_BLSP1_UART2_APPS_M 0x0180303C
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#define GCC_BLSP1_UART2_APPS_N 0x01803040
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#define GCC_BLSP1_UART2_APPS_D 0x01803044
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#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x01803034
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#define GCC_BLSP1_UART2_APPS_CBCR 0x0180302C
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define UART2_RCGR_SRC_SEL 0x0
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#define UART2_RCGR_SRC_DIV 0x0
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#define UART2_RCGR_MODE 0x2
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#define UART2_CMD_RCGR_UPDATE 0x1
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#define UART2_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#ifdef CONFIG_IPQ40XX_I2C
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR 0x01802010
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#define GCC_BLSP1_QUP1_I2C_APPS_M 0x0180303C
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#define GCC_BLSP1_QUP1_I2C_APPS_N 0x01803040
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#define GCC_BLSP1_QUP1_I2C_APPS_D 0x01803044
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#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x0180200C
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#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x01802008
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#define GCC_I2C_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_I2C_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_I2C_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_I2C_CFG_RCGR_SRCDIV_SHIFT 0
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#define I2C0_RCGR_SRC_SEL 1
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#define I2C0_RCGR_SRC_DIV 20
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#define I2C0_CMD_RCGR_UPDATE 0x1
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#define I2C0_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#endif
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#define GCC_PCIE_SLEEP_CBCR 0x0181D014
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#define GCC_PCIE_AXI_M_CBCR 0x0181D004
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#define GCC_PCIE_AXI_S_CBCR 0x0181D008
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#define GCC_PCIE_AHB_CBCR 0x0181D00C
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#define PCIE_TIMEOUT_CNT 100
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#define ENABLE 0x1
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#define DISABLE 0x0
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#define BIT(s) (1<<s)
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void emmc_clock_config(int mode);
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void emmc_clock_disable(void);
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/* UART clocks configuration */
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void uart2_clock_config(unsigned int m,
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unsigned int n, unsigned int two_d);
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void uart2_toggle_clock(void);
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int uart2_trigger_update(void);
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void uart2_set_rate_mnd(unsigned int m,
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unsigned int n, unsigned int two_d);
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void uart2_configure_mux(void);
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/* I2C clocks configuration */
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#ifdef CONFIG_IPQ40XX_I2C
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#ifdef CONFIG_IPQ807x_I2C
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void i2c_clock_config(void);
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void i2c0_toggle_clock(void);
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int i2c0_trigger_update(void);
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void i2c0_configure_mux(void);
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#endif
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int pcie_clock_enable(int clk_addr);
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void pcie_clock_disable(int clk_addr);
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#endif /*QCA_CLK_H*/
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@ -12,196 +12,12 @@
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*/
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#include <common.h>
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#include <asm/arch-qcom-common/clk.h>
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#include <asm/arch-ipq40xx/iomap.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#define GCC_SDCC1_MISC 0x1818014
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#define GCC_SDCC1_APPS_CBCR 0x181800C
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#define GCC_SDCC1_APPS_RCGR 0x1818008
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#define GCC_SDCC1_APPS_CMD_RCGR 0x1818004
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void emmc_clock_config(int mode)
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{
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/* Select SDCC clock source as DDR_PLL_SDCC1_CLK 192MHz */
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writel(0x100, GCC_SDCC1_APPS_RCGR);
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/* Update APPS_CMD_RCGR to reflect source selection */
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writel(0x1, GCC_SDCC1_APPS_CMD_RCGR);
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udelay(10);
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if (mode == MMC_IDENTIFY_MODE) {
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/* Set root clock generator to bypass mode */
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writel(0x0, GCC_SDCC1_APPS_CBCR);
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udelay(10);
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/* Choose divider for 400KHz */
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writel(0x1e4 , GCC_SDCC1_MISC);
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/* Enable root clock generator */
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writel(0x1, GCC_SDCC1_APPS_CBCR);
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udelay(10);
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}
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if (mode == MMC_DATA_TRANSFER_MODE) {
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/* Set root clock generator to bypass mode */
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writel(0x0, GCC_SDCC1_APPS_CBCR);
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udelay(10);
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/* Choose divider for 48MHz */
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writel(0x3, GCC_SDCC1_MISC);
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/* Enable root clock generator */
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writel(0x1, GCC_SDCC1_APPS_CBCR);
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udelay(10);
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}
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}
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void emmc_clock_disable(void)
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{
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/* Clear divider */
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writel(0x0, GCC_SDCC1_MISC);
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}
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void uart2_configure_mux(void)
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{
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unsigned long cfg_rcgr;
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cfg_rcgr = readl(GCC_BLSP1_UART2_APPS_CFG_RCGR);
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/* Clear mode, src sel, src div */
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cfg_rcgr &= ~(GCC_UART_CFG_RCGR_MODE_MASK |
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GCC_UART_CFG_RCGR_SRCSEL_MASK |
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GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART2_RCGR_SRC_SEL << GCC_UART_CFG_RCGR_SRCSEL_SHIFT)
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& GCC_UART_CFG_RCGR_SRCSEL_MASK);
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cfg_rcgr |= ((UART2_RCGR_SRC_DIV << GCC_UART_CFG_RCGR_SRCDIV_SHIFT)
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& GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART2_RCGR_MODE << GCC_UART_CFG_RCGR_MODE_SHIFT)
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& GCC_UART_CFG_RCGR_MODE_MASK);
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writel(cfg_rcgr, GCC_BLSP1_UART2_APPS_CFG_RCGR);
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}
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void uart2_set_rate_mnd(unsigned int m,
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unsigned int n, unsigned int two_d)
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{
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writel(m, GCC_BLSP1_UART2_APPS_M);
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writel(NOT_N_MINUS_M(n, m), GCC_BLSP1_UART2_APPS_N);
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writel(NOT_2D(two_d), GCC_BLSP1_UART2_APPS_D);
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}
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int uart2_trigger_update(void)
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{
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unsigned long cmd_rcgr;
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int timeout = 0;
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cmd_rcgr = readl(GCC_BLSP1_UART2_APPS_CMD_RCGR);
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cmd_rcgr |= UART2_CMD_RCGR_UPDATE;
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writel(cmd_rcgr, GCC_BLSP1_UART2_APPS_CMD_RCGR);
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while (readl(GCC_BLSP1_UART2_APPS_CMD_RCGR) & UART2_CMD_RCGR_UPDATE) {
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if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) {
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printf("Timeout waiting for UART2 clock update\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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cmd_rcgr = readl(GCC_BLSP1_UART2_APPS_CMD_RCGR);
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return 0;
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}
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void uart2_toggle_clock(void)
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{
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unsigned long cbcr_val;
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cbcr_val = readl(GCC_BLSP1_UART2_APPS_CBCR);
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cbcr_val |= UART2_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART2_APPS_CBCR);
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}
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void uart2_clock_config(unsigned int m,
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unsigned int n, unsigned int two_d)
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{
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uart2_configure_mux();
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uart2_set_rate_mnd(m, n, two_d);
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uart2_trigger_update();
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uart2_toggle_clock();
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}
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#ifdef CONFIG_IPQ40XX_I2C
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void i2c0_configure_mux(void)
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{
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unsigned long cfg_rcgr;
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cfg_rcgr = readl(GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR);
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/* Clear mode, src sel, src div */
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cfg_rcgr &= ~(GCC_I2C_CFG_RCGR_SRCSEL_MASK |
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GCC_I2C_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((I2C0_RCGR_SRC_SEL << GCC_I2C_CFG_RCGR_SRCSEL_SHIFT)
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& GCC_UART_CFG_RCGR_SRCSEL_MASK);
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cfg_rcgr |= ((I2C0_RCGR_SRC_DIV << GCC_I2C_CFG_RCGR_SRCDIV_SHIFT)
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& GCC_UART_CFG_RCGR_SRCDIV_MASK);
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writel(cfg_rcgr, GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR);
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}
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int i2c0_trigger_update(void)
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{
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unsigned long cmd_rcgr;
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int timeout = 0;
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cmd_rcgr = readl(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR);
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cmd_rcgr |= I2C0_CMD_RCGR_UPDATE;
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writel(cmd_rcgr, GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR);
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while (readl(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR) & I2C0_CMD_RCGR_UPDATE) {
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if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) {
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printf("Timeout waiting for I2C0 clock update\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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cmd_rcgr = readl(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR);
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return 0;
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}
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void i2c0_toggle_clock(void)
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{
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unsigned long cbcr_val;
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cbcr_val = readl(GCC_BLSP1_QUP1_I2C_APPS_CBCR);
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cbcr_val |= I2C0_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_QUP1_I2C_APPS_CBCR);
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}
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#include "clk.h"
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#ifdef CONFIG_IPQ807x_I2C
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void i2c_clock_config(void)
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{
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i2c0_configure_mux();
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i2c0_trigger_update();
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i2c0_toggle_clock();
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return;
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}
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#endif
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int pcie_clock_enable(int clk_addr)
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{
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unsigned int count = PCIE_TIMEOUT_CNT;
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int state, val;
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writel(ENABLE, clk_addr);
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do {
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val = readl(clk_addr);
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count--;
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if (count == 0) {
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printf("Timeout waiting for %d enable \n", clk_addr);
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return -ETIMEDOUT;
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}
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state = (val & BIT(31));
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udelay(10);
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} while (state);
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return 0;
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}
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void pcie_clock_disable(int clk_addr)
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{
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writel(0, clk_addr);
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}
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@ -22,6 +22,14 @@
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#include <mapmem.h>
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#include <dm.h>
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#ifdef CONFIG_IPQ807x_I2C
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#include "../../board/qca/ipq807x/clk.h"
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#endif
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#ifdef CONFIG_IPQ40XX_I2C
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#include "../../board/qca/ipq40xx/clk.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static int i2c_base_addr;
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