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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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ipq40x: Added multicore support
-Device IO commands are not supported -CPU down is supported by waiting in loop -Need reboot to execute bootipq command Change-Id: Id10eef0c8e5feb636716461c58ba1640dfe46658 Signed-off-by: Santan Kumar <santank@codeaurora.org>
This commit is contained in:
Santan Kumar
Gerrit - the friendly Code Review server
parent
8d9a453c47
commit
b7af9b06d2
4 changed files with 181 additions and 2 deletions
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@ -13,9 +13,61 @@
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#include <asm/system.h>
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#include <linux/linkage.h>
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ENTRY(ak_secondary_cpu_reinit)
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ENTRY(dk_secondary_cpu_reinit)
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mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
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and r1, r0, #0xf /* return CPU ID in cluster */
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sub r0, r1, #1
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/* Now r1 has the cpu number,
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* this will serve as index to "struct cpu_entry_arg"
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* struct cpu_entry_arg {
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* void *stack_ptr; +0 1c 38 54
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* volatile void *gd_ptr; +4 20 3c
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* void *arg_ptr; +8 24 40
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* int cpu_up; +0xc 28 44
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* int cmd_complete; +0x10 2c 48
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* int cmd_result; +0x14 30 4c
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* void *stack_top_ptr; +0x18 34 50
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* +0x1c (next entry in core[])
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* };
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*/
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ldr r4, =globl_core_array
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mov r3, #0x1c
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mul r2, r0, r3
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ldr r0, [r4]
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add r0, r0, r2
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/* For us r0 has the arg structure pointer
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struct cpu_entry_arg {
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void *stack_ptr;
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void *gd_ptr;
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void *arg_ptr;
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int cpu_up;
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int cmd_complete;
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int cmd_result;
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};
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*/
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ldr sp, [r0] /* stack_ptr */
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bic sp, sp, #7 /* 8-byte alignment required for stack */
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/* gd address is always in r9, but if u-boot changes Tomorrow,
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* we have to change here. Note :- --> ARM: use r9 for gd
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*/
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ldr r9, [r0, #0x4]
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/* store success in cpu_up */
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mov r3, #1
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str r3, [r0, #0xc]
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add r1, r0, #0x10
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add r2, r0, #0x14
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ldr r0, [r0, #0x8]
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bl secondary_core_entry
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self_reloop:
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b self_reloop
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ENDPROC(ak_secondary_cpu_reinit)
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ENDPROC(dk_secondary_cpu_reinit)
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ENTRY(dk_secondary_cpu_init)
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ENTRY(ak_secondary_cpu_init)
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mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
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and r1, r0, #0xf /* return CPU ID in cluster */
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and r1, r0, #0xf /* return CPU ID in cluster */
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sub r0, r1, #1
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/* Now r1 has the cpu number,
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* this will serve as index to "struct cpu_entry_arg"
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@ -93,6 +145,7 @@ self_loop:
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b self_loop
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ENDPROC(secondary_cpu_init)
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ENDPROC(ak_secondary_cpu_init)
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ENDPROC(dk_secondary_cpu_init)
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ENTRY(send_event)
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dsb
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@ -107,6 +160,12 @@ ENTRY(wait_event)
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bx r0
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ENDPROC(wait_event)
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ENTRY(get_cpu_id)
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mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
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and r0, r0, #0xf /* return CPU ID in cluster */
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bx lr
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ENDPROC(get_cpu_id)
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.globl globl_core_array
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globl_core_array:
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.word 0
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@ -39,6 +39,12 @@
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#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E70
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DECLARE_GLOBAL_DATA_PTR;
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#define CPU0_APCS_SAW2_VCTL 0x0b089014
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#define CPU0_APCS_CPU_PWR_CTL 0x0b088004
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#define CPU_APCS_SAW2_VCTL(cpuid) (CPU0_APCS_SAW2_VCTL + (cpuid * 0x10000))
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#define CPU_APCS_CPU_PWR_CTL(cpuid) (CPU0_APCS_CPU_PWR_CTL + (cpuid * 0x10000))
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#ifndef CONFIG_SDHCI_SUPPORT
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qca_mmc mmc_host;
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#else
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@ -508,5 +514,112 @@ unsigned int get_dts_machid(unsigned int machid)
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*/
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int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_flag)
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{
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return 0;
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}
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extern void dk_secondary_cpu_init(void);
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extern void dk_secondary_cpu_reinit(void);
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/*
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* Set the cold/warm boot address for one of the CPU cores.
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*/
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int scm_set_boot_addr(bool enable_sec_core)
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{
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int ret;
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struct {
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unsigned int flags;
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unsigned long addr;
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} cmd;
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if (!enable_sec_core)
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return -1;
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cmd.addr = (unsigned long)dk_secondary_cpu_init;
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cmd.flags = 0xff;
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ret = scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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if (ret) {
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printf("--- %s: scm_call failed ret = %d\n", __func__, ret);
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}
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return ret;
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}
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int is_secondary_core_off(unsigned int cpuid)
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{
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return 1;
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}
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static int secondary_core_already_reset[NR_CPUS];
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static int scm_boot_addr_already_set;
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extern int get_cpu_id(void);
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static volatile int core_var;
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volatile void bring_secondary_core_down(unsigned int state)
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{
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int current_cpu_id;
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current_cpu_id = (1 << get_cpu_id());
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core_var &= (~current_cpu_id);
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while (!(core_var & current_cpu_id)) {
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cp_delay();
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}
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dk_secondary_cpu_reinit();
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}
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static int kpssv1_release_secondary(unsigned int cpuid)
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{
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dcache_enable();
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writel(0xa4, CPU_APCS_SAW2_VCTL(cpuid));
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barrier();
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udelay(512);
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writel(0x109, CPU_APCS_CPU_PWR_CTL(cpuid));
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writel(0x101, CPU_APCS_CPU_PWR_CTL(cpuid));
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barrier();
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udelay(1);
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writel(0x121, CPU_APCS_CPU_PWR_CTL(cpuid));
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barrier();
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udelay(2);
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writel(0x120, CPU_APCS_CPU_PWR_CTL(cpuid));
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barrier();
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udelay(2);
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writel(0x100, CPU_APCS_CPU_PWR_CTL(cpuid));
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barrier();
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udelay(100);
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writel(0x180, CPU_APCS_CPU_PWR_CTL(cpuid));
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barrier();
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dcache_disable();
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return 0;
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}
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int bring_sec_core_up(unsigned int cpuid, unsigned int entry, unsigned int arg)
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{
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int err = 0;
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if (!secondary_core_already_reset[cpuid]) {
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if (!scm_boot_addr_already_set) {
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err = scm_set_boot_addr(true);
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core_var = 0;
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if (!err) {
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scm_boot_addr_already_set = 1;
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kpssv1_release_secondary(cpuid);
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secondary_core_already_reset[cpuid] = 1;
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} else
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return err;
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} else {
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kpssv1_release_secondary(cpuid);
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secondary_core_already_reset[cpuid] = 1;
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}
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} else {
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core_var |= (1 << cpuid);
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}
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return 0;
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}
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@ -924,6 +924,7 @@ int ipq_get_tz_version(char *version_name, int buf_size)
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void forever(void) { while (1); }
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extern void ak_secondary_cpu_init(void);
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extern void ak_secondary_cpu_reinit(void);
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extern void send_event(void);
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/*
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* Set the cold/warm boot address for one of the CPU cores.
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@ -1001,7 +1002,7 @@ extern void wait_event(void (*)(void));
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void bring_secondary_core_down(unsigned int state)
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{
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wait_event(ak_secondary_cpu_init);
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wait_event(ak_secondary_cpu_reinit);
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}
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static int krait_release_secondary(void)
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@ -277,6 +277,12 @@ typedef struct {
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#define CONFIG_LIB_UUID
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#define CONFIG_SMP_CMD_SUPPORT
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#ifdef CONFIG_SMP_CMD_SUPPORT
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#define NR_CPUS 4
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#endif
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/*
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* CRASH DUMP ENABLE
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*/
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