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ipq5018: block_drvr const declared only on HAVE_BLOCK_DEVICE

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1. Modified to the declare block_drvr struct and const variable
only on HAVE_BLOCK_DEVICE config enabled.
2. Removed unused const training_block_128

Signed-off-by: Karthick Shanmugham <kartshan@codeaurora.org>
Change-Id: Icfe05aec82a124429443aadf735767366b168d6b
This commit is contained in:
Karthick Shanmugham 2020-10-07 12:56:47 +05:30
parent ac3c252cf1
commit b6d6a4aa72
2 changed files with 3 additions and 14 deletions
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6
disk/part.c
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@ -20,6 +20,9 @@
#define PRINTF(fmt,args...) #define PRINTF(fmt,args...)
#endif #endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
struct block_drvr { struct block_drvr {
char *name; char *name;
block_dev_desc_t* (*get_dev)(int dev); block_dev_desc_t* (*get_dev)(int dev);
@ -55,9 +58,6 @@ static const struct block_drvr block_drvr[] = {
{ }, { },
}; };
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{ {
const struct block_drvr *drvr = block_drvr; const struct block_drvr *drvr = block_drvr;

11
drivers/mtd/nand/qpic_nand.c
View file

@ -128,17 +128,6 @@ static const unsigned int training_block_64[] = {
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
}; };
static const unsigned int training_block_128[] = {
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,
};
#define TRAINING_PART_OFFSET 0x3c00000 #define TRAINING_PART_OFFSET 0x3c00000
#define MAXIMUM_ALLOCATED_TRAINING_BLOCK 4 #define MAXIMUM_ALLOCATED_TRAINING_BLOCK 4
#define TOTAL_NUM_PHASE 7 #define TOTAL_NUM_PHASE 7