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ipq8064: Enabled u-boot reset by enabling watchdog

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On applying 'reset' command on u-boot, it enables the watchdog
with a default reset value. CPU will reset after the set value.

Change-Id: Idee257e6fcdf576e5209066fabeb76340465c25e
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
This commit is contained in:
Gokul Sriram Palanisamy 2016-10-21 14:12:04 +05:30
parent f62b258e04
commit b429ae2267
2 changed files with 28 additions and 0 deletions
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10
board/qca/ipq806x/ipq806x.c
View file

@ -78,8 +78,18 @@ void reset_crashdump(void)
void reset_cpu(unsigned long a)
{
printf("\nResetting with watch dog!\n");
writel(0, APCS_WDT0_EN);
writel(1, APCS_WDT0_RST);
writel(RESET_WDT_BARK_TIME, APCS_WDT0_BARK_TIME);
writel(RESET_WDT_BITE_TIME, APCS_WDT0_BITE_TIME);
writel(1, APCS_WDT0_EN);
writel(1, APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE);
while(1);
}
void emmc_clock_config(int mode)
{
/* TODO: To be filled */

18
board/qca/ipq806x/ipq806x.h
View file

@ -16,6 +16,7 @@
#include <configs/ipq806x.h>
#include <asm/u-boot.h>
#include <asm/arch-ipq806x/clk.h>
#include <asm/arch-qcom-common/qca_common.h>
#include "phy.h"
@ -24,6 +25,23 @@
#define KERNEL_AUTH_CMD 0x7
#define MSM_TMR_BASE 0x0200A000
#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)
#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
/* Watchdog bite time set to default reset value */
#define RESET_WDT_BITE_TIME 0x31F3
/* Watchdog bark time value is kept larger than the watchdog timeout
* of 0x31F3, effectively disabling the watchdog bark interrupt
*/
#define RESET_WDT_BARK_TIME (5 * RESET_WDT_BITE_TIME)
typedef struct {
uint count;
u8 addr[7];