mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-05 00:41:17 +01:00
board: arm: devsoc: update USB PHY & Clk config
Change-Id: Ie1216d3b191aef1f221df91ec254e162e57e099a Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This commit is contained in:
Vandhiadevan Karunamoorthy
parent
335ae409fb
commit
b2da1813de
4 changed files with 265 additions and 36 deletions
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@ -129,6 +129,74 @@
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#define NSS_CC_PORT1_RX_CBCR 0x39B00480
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#define NSS_CC_UNIPHY_PORT1_RX_CBCR 0x39B004B4
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#define GCC_USB_BCR 0x182C000
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#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
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#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
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#define GCC_USB0_MASTER_M 0x182C00C
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#define GCC_USB0_MASTER_N 0x182C010
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#define GCC_USB0_MASTER_D 0x182C014
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#define GCC_USB0_AUX_CMD_RCGR 0x182C018
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#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
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#define GCC_USB0_AUX_M 0x182C020
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#define GCC_USB0_AUX_N 0x182C024
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#define GCC_USB0_AUX_D 0x182C028
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#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
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#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
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#define GCC_USB0_MOCK_UTMI_M 0x182C034
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#define GCC_USB0_MOCK_UTMI_N 0x182C038
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#define GCC_USB0_MOCK_UTMI_D 0x182C03C
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#define GCC_USB0_MOCK_UTMI_DIV_CDIVR 0x182C040
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#define GCC_USB0_MASTER_CBCR 0x182C048
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#define GCC_USB0_MASTER_SREGR 0x182C04C
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#define GCC_USB0_AUX_CBCR 0x182C050
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#define GCC_USB0_MOCK_UTMI_CBCR 0x182C054
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#define GCC_USB0_SLEEP_CBCR 0x182C058
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#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
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#define GCC_USB0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_USB0_PHY_BCR 0x182C06C
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#define GCC_USB3PHY_0_PHY_BCR 0x182C070
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#define GCC_USB0_PHY_PIPE_MISC 0x182C074
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#define GCC_USB0_PIPE_CBCR 0x182C078
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#define GCC_USB0_LFPS_CMD_RCGR 0x182C07C
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#define GCC_USB0_LFPS_CFG_RCGR 0x182C080
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#define GCC_USB0_LFPS_M 0x182C084
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#define GCC_USB0_LFPS_N 0x182C088
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#define GCC_USB0_LFPS_D 0x182C08C
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#define GCC_USB0_LFPS_CBCR 0x182C090
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#define GCC_USB0_EUD_AT_CBCR 0x1830004
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#define GCC_USB0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_QUSB2_0_PHY_BCR 0x182C068
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#define GCC_USB0_LFPS_CFG_SRC_SEL (0x1 << 8)
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#define GCC_USB0_LFPS_CFG_SRC_DIV (0x1F << 0)
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#define LFPS_M 0x1
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#define LFPS_N 0xFE
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#define LFPS_D 0xFD
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#define GCC_USB0_LFPS_MODE (0x2 << 12)
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#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
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#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0x3 << 0)
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#define AUX_M 0x0
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#define AUX_N 0x0
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#define AUX_D 0x0
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0x7 << 0)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (1 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (0x13 << 0)
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#define MOCK_UTMI_M 0x1
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#define MOCK_UTMI_N 0xFE
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#define MOCK_UTMI_D 0xFD
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#define PIPE_UTMI_CLK_SEL 0x1
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#define PIPE3_PHYSTATUS_SW (0x1 << 3)
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#define PIPE_UTMI_CLK_DIS (0x1 << 8)
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void);
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void emmc_clock_reset(void);
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@ -139,7 +207,7 @@ void pcie_v2_clock_deinit(int pcie_id);
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#endif
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id, int ssphy);
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void usb_clock_init(void);
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void usb_clock_deinit(void);
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#endif
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@ -234,15 +234,11 @@ void pcie_v2_clock_deinit(int pcie_id)
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}
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id, int ssphy)
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void usb_clock_init(void)
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{
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#ifdef QCA_CLOCK_ENABLE
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int cfg;
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/* select usb phy mux */
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if (ssphy)
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writel(0x1, TCSR_USB_PCIE_SEL);
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/* Configure usb0_master_clk_src */
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cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL |
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GCC_USB0_MASTER_CFG_RCGR_SRC_DIV);
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@ -255,7 +251,9 @@ void usb_clock_init(int id, int ssphy)
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cfg = (GCC_USB_MOCK_UTMI_SRC_SEL |
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GCC_USB_MOCK_UTMI_SRC_DIV);
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writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR);
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writel(GCC_USB_MOCK_UTMI_CLK_DIV, GCC_USB0_MOCK_UTMI_CBCR);
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writel(MOCK_UTMI_M, GCC_USB0_MOCK_UTMI_M);
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writel(MOCK_UTMI_N, GCC_USB0_MOCK_UTMI_N);
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writel(MOCK_UTMI_D, GCC_USB0_MOCK_UTMI_D);
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writel(CMD_UPDATE, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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@ -282,8 +280,6 @@ void usb_clock_init(int id, int ssphy)
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writel(ROOT_EN, GCC_USB0_LFPS_CMD_RCGR);
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/* Configure CBCRs */
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writel(CLK_DISABLE, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(CLK_ENABLE, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel((readl(GCC_USB0_MASTER_CBCR) | CLK_ENABLE),
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GCC_USB0_MASTER_CBCR);
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writel(CLK_ENABLE, GCC_USB0_SLEEP_CBCR);
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@ -300,16 +296,13 @@ void usb_clock_init(int id, int ssphy)
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void usb_clock_deinit(void)
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{
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#ifdef QCA_CLOCK_ENABLE
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/* Disable clocks */
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB0_MASTER_CBCR);
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writel(0, GCC_USB0_SLEEP_CBCR);
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writel(0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0, GCC_USB0_AUX_CBCR);
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writel(0, GCC_ANOC_USB_AXI_CBCR);
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writel(0, GCC_SNOC_USB_CBCR);
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writel(0x0, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0x4220, GCC_USB0_MASTER_CBCR);
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writel(0x0, GCC_USB0_SLEEP_CBCR);
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writel(0x0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0x0, GCC_USB0_AUX_CBCR);
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writel(0x0, GCC_USB0_LFPS_CBCR);
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#else
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return;
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#endif
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@ -355,36 +355,147 @@ void board_pci_deinit()
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#ifdef CONFIG_USB_XHCI_IPQ
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void board_usb_deinit(int id)
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{
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int nodeoff;
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int nodeoff, ssphy;
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char node_name[8];
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snprintf(node_name, sizeof(node_name), "usb%d", id);
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nodeoff = fdt_path_offset(gd->fdt_blob, node_name);
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if (fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0))
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return;
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ssphy = fdtdec_get_int(gd->fdt_blob, nodeoff, "ssphy", 0);
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/* Enable USB PHY Power down */
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setbits_le32(QUSB2PHY_BASE + 0xA4, 0x0);
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/* Disable clocks */
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usb_clock_deinit();
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/* GCC_QUSB2_0_PHY_BCR */
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set_mdelay_clearbits_le32(GCC_QUSB2_0_PHY_BCR, 0x1, 10);
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/* GCC_USB0_PHY_BCR */
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if (ssphy)
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set_mdelay_clearbits_le32(GCC_USB0_PHY_BCR, 0x1, 10);
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/* GCC Reset USB BCR */
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set_mdelay_clearbits_le32(GCC_USB_BCR, 0x1, 10);
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/* Deselect the usb phy mux */
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if (ssphy)
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writel(TCSR_USB_PCIE_SEL_PCI, TCSR_USB_PCIE_SEL);
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}
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static void usb_init_hsphy(void __iomem *phybase, int ssphy)
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{
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if (!ssphy) {
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/*Enable utmi instead of pipe*/
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writel((readl(USB30_GENERAL_CFG) |
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PIPE_UTMI_CLK_DIS), USB30_GENERAL_CFG);
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udelay(100);
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writel((readl(USB30_GENERAL_CFG) |
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PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW),
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USB30_GENERAL_CFG);
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udelay(100);
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writel((readl(USB30_GENERAL_CFG) &
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~PIPE_UTMI_CLK_DIS), USB30_GENERAL_CFG);
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}
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/* Disable USB PHY Power down */
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setbits_le32(phybase + 0xA4, 0x1);
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/* Enable override ctrl */
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writel(UTMI_PHY_OVERRIDE_EN, phybase + USB_PHY_CFG0);
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/* Enable POR*/
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writel(POR_EN, phybase + USB_PHY_UTMI_CTRL5);
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udelay(15);
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/* Configure frequency select value*/
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writel(FREQ_SEL, phybase + USB_PHY_FSEL_SEL);
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/* Configure refclk frequency */
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writel(FSEL_VALUE << FSEL, phybase + USB_PHY_HS_PHY_CTRL_COMMON0);
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writel(readl(phybase + USB_PHY_UTMI_CTRL5) & ATERESET,
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phybase + USB_PHY_UTMI_CTRL5);
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writel(USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
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phybase + USB_PHY_HS_PHY_CTRL2);
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writel(SLEEPM, phybase + USB_PHY_UTMI_CTRL0);
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writel(XCFG_COARSE_TUNE_NUM | XCFG_COARSE_TUNE_NUM,
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phybase + USB2PHY_USB_PHY_M31_XCFGI_11);
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udelay(100);
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writel(readl(phybase + USB_PHY_UTMI_CTRL5) & ~POR_EN,
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phybase + USB_PHY_UTMI_CTRL5);
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writel(readl(phybase + USB_PHY_HS_PHY_CTRL2) & USB2_SUSPEND_N_SEL,
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phybase + USB_PHY_HS_PHY_CTRL2);
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}
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static void usb_init_ssphy(void __iomem *phybase)
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{
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writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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udelay(100);
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/*set frequency initial value*/
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writel(0x1cb9, phybase + SSCG_CTRL_REG_4);
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writel(0x023a, phybase + SSCG_CTRL_REG_5);
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/*set spectrum spread count*/
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writel(0xd360, phybase + SSCG_CTRL_REG_3);
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/*set fstep*/
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writel(0x1, phybase + SSCG_CTRL_REG_1);
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writel(0xeb, phybase + SSCG_CTRL_REG_2);
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return;
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}
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static void usb_init_phy(int ssphy)
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{
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void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
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boot_clk_ctl = (u32 *)GCC_USB0_BOOT_CLOCK_CTL;
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usb_bcr = (u32 *)GCC_USB_BCR;
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qusb2_phy_bcr = (u32 *)GCC_QUSB2_0_PHY_BCR;
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/* Disable USB Boot Clock */
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clrbits_le32(boot_clk_ctl, 0x0);
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/* GCC Reset USB BCR */
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set_mdelay_clearbits_le32(usb_bcr, 0x1, 10);
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if (ssphy)
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setbits_le32(GCC_USB0_PHY_BCR, 0x1);
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setbits_le32(qusb2_phy_bcr, 0x1);
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udelay(1);
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/* Config user control register */
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writel(0x4004010, USB30_GUCTL);
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writel(0x4945920, USB30_FLADJ);
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if (ssphy)
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clrbits_le32(GCC_USB0_PHY_BCR, 0x1);
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clrbits_le32(qusb2_phy_bcr, 0x1);
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udelay(30);
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if (ssphy)
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usb_init_ssphy((u32 *)USB3PHY_APB_BASE);
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usb_init_hsphy((u32 *)QUSB2PHY_BASE, ssphy);
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}
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int ipq_board_usb_init(void)
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{
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int i, nodeoff, ssphy;
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char node_name[8];
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int nodeoff, ssphy;
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for (i=0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
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snprintf(node_name, sizeof(node_name), "usb%d", i);
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nodeoff = fdt_path_offset(gd->fdt_blob, node_name);
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if (nodeoff < 0){
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printf("USB: Node Not found, skipping initialization\n");
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return 0;
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}
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nodeoff = fdt_path_offset(gd->fdt_blob, "usb0");
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if (nodeoff < 0){
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printf("USB: Node Not found,skipping initialization\n");
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return 0;
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}
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ssphy = fdtdec_get_int(gd->fdt_blob, nodeoff, "ssphy", 0);
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if (!fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0)) {
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usb_clock_init(i, ssphy);
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}else {
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/* Config user control register */
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writel(0x0C804010, USB30_GUCTL);
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}
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ssphy = fdtdec_get_int(gd->fdt_blob, nodeoff, "ssphy", 0);
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if (!fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0)) {
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/* select usb phy mux */
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if (ssphy)
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writel(TCSR_USB_PCIE_SEL_USB,
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TCSR_USB_PCIE_SEL);
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usb_clock_init();
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usb_init_phy(ssphy);
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} else {
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/* Config user control register */
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writel(0x0C804010, USB30_GUCTL);
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}
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return 0;
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@ -39,6 +39,63 @@ extern const add_node_t add_fdt_node[];
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#define TCSR_MODE_CTRL_2PORT_2LANE 0x1947544
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#define USB30_GUCTL 0x8A0C12C
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/* USB Registers */
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#define TCSR_USB_PCIE_SEL 0x01947540
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#define TCSR_USB_PCIE_SEL_USB 0x1
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#define TCSR_USB_PCIE_SEL_PCI 0x0
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#define USB30_GENERAL_CFG 0x8AF8808
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#define USB30_GUCTL 0x8A0C12C
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#define USB30_FLADJ 0x8A0C630
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#define GUCTL 0x700C12C
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#define FLADJ 0x700C630
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#define SW_COLLAPSE_ENABLE (1 << 0)
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#define SW_OVERRIDE_ENABLE (1 << 2)
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#define XCFG_COARSE_TUNE_NUM (2 << 0)
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#define XCFG_FINE_TUNE_NUM (1 << 3)
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#define FSEL_VALUE (5 << 4)
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#define QUSB2PHY_BASE 0x7B000
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#define USB3PHY_APB_BASE 0x4B0000
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#define SSCG_CTRL_REG_1 0x9c
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#define SSCG_CTRL_REG_2 0xa0
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#define SSCG_CTRL_REG_3 0xa4
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#define SSCG_CTRL_REG_4 0xa8
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#define SSCG_CTRL_REG_5 0xac
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#define SSCG_CTRL_REG_6 0xb0
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#define CDR_CTRL_REG_1 0x80
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#define CDR_CTRL_REG_2 0x84
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#define CDR_CTRL_REG_3 0x88
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#define CDR_CTRL_REG_4 0x8C
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#define CDR_CTRL_REG_5 0x90
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#define CDR_CTRL_REG_6 0x94
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#define CDR_CTRL_REG_7 0x98
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#define USB_PHY_CFG0 0x94
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#define USB_PHY_UTMI_CTRL0 0x3C
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#define USB_PHY_UTMI_CTRL5 0x50
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#define USB_PHY_FSEL_SEL 0xB8
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#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
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#define USB_PHY_REFCLK_CTRL 0xA0
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#define USB_PHY_HS_PHY_CTRL2 0x64
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#define USB2PHY_USB_PHY_M31_XCFGI_11 0xE4
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#define UTMI_PHY_OVERRIDE_EN BIT(1)
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#define SLEEPM BIT(1)
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#define POR_EN BIT(1)
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#define FREQ_SEL BIT(0)
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#define COMMONONN BIT(7)
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#define FSEL BIT(4)
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#define RETENABLEN BIT(3)
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#define USB2_SUSPEND_N_SEL BIT(3)
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#define USB2_SUSPEND_N BIT(2)
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#define USB2_UTMI_CLK_EN BIT(1)
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#define CLKCORE BIT(1)
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#define ATERESET ~BIT(0)
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/*
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* weak function
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*/
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