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Merge "pci: ipq: Add sec.dat fusing support for qcn9224"
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2 changed files with 192 additions and 0 deletions
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@ -397,6 +397,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PARF_BLOCK_SLV_AXI_WR_LIMIT_2 0x3A0
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#define PARF_BLOCK_SLV_AXI_RD_BASE_2 0x3A8
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#define PARF_BLOCK_SLV_AXI_RD_LIMIT_2 0x3B0
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#define PARF_BDF_TO_SID_TABLE 0x2000
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#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
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#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)
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@ -418,6 +419,26 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QCN9224_TCSR_SOC_HW_VERSION 0x1B00000
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#define QCN9224_TCSR_SOC_HW_VERSION_MASK GENMASK(11,8)
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#define QCN9224_TCSR_SOC_HW_VERSION_SHIFT 8
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#define QCN9224_TCSR_PBL_LOGGING_REG 0x1B00094
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#define BHI_STATUS (0x12C)
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#define BHI_IMGADDR_LOW (0x108)
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#define BHI_IMGADDR_HIGH (0x10C)
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#define BHI_IMGSIZE (0x110)
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#define BHI_ERRCODE (0x130)
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#define BHI_ERRDBG1 (0x134)
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#define BHI_ERRDBG2 (0x138)
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#define BHI_ERRDBG3 (0x13C)
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#define BHI_IMGTXDB (0x118)
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#define BHI_EXECENV (0x128)
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#define BHI_STATUS_MASK (0xC0000000)
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#define BHI_STATUS_SHIFT (30)
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#define BHI_STATUS_SUCCESS (2)
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#define NO_MASK (0xFFFFFFFF)
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#endif
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static unsigned int local_buses[] = { 0, 0 };
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@ -1356,6 +1377,8 @@ void pcie_linkup(struct ipq_pcie *pcie)
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writel((pcie->pci_dbi.start + 0x200000), pcie->parf.start + PARF_BLOCK_SLV_AXI_WR_LIMIT_2);
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writel((pcie->pci_dbi.start + 0x108000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_BASE_2);
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writel((pcie->pci_dbi.start + 0x200000), pcie->parf.start + PARF_BLOCK_SLV_AXI_RD_LIMIT_2);
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for (j = 0; j < 255; j++)
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writel(0, pcie->parf.start + PARF_BDF_TO_SID_TABLE + (4 * j));
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ipq_pcie_prog_outbound_atu(pcie);
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} else {
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ipq_pcie_config_controller(pcie);
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@ -1913,4 +1936,172 @@ out:
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U_BOOT_CMD(detect_qcn9224, 1, 1, do_detect_qcn9224,
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"Detect qcn9224 version and populate it on qcn9224_version Env",
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"qcn9224_version will be zero if not attached else one / two");
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pci_dev_t pci_find_ipq_devices(struct pci_device_id *ids, int device_id)
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{
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struct pci_controller * hose;
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pci_dev_t bdf;
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int bus, index;
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hose = pci_get_hose_head();
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while(hose && device_id && device_id < 4) {
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hose = hose->next;
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device_id--;
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}
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for (;hose; hose = hose->next) {
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for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
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bdf = pci_hose_find_devices(hose, bus, ids, &index);
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if (bdf != -1)
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return bdf;
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}
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}
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return -1;
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}
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static int poll_reg_field(pci_addr_t addr, u32 *val, u32 mask, u32 shift, u32 compare)
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{
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u32 time_out_ms = 12500;
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u32 delay = 250;
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u32 retry = time_out_ms / delay; /*50 retries*/
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while(retry--) {
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*val = readl(addr);
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if ((*val & mask) >> shift == compare)
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return 0;
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mdelay(delay);
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}
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return -ETIMEDOUT;
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}
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static void print_error_code(pci_addr_t addr, bool pbl_log)
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{
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int i;
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u32 val;
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struct {
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char *name;
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u32 offset;
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} error_reg[] = {
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{ "ERROR_CODE", BHI_ERRCODE },
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{ "ERROR_DBG1", BHI_ERRDBG1 },
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{ "ERROR_DBG2", BHI_ERRDBG2 },
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{ "ERROR_DBG3", BHI_ERRDBG3 },
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{ NULL },
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};
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for (i = 0; error_reg[i].name; i++) {
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val = readl(addr + error_reg[i].offset);
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printf("Reg: %s value: 0x%x\n", error_reg[i].name, val);
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}
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if (pbl_log) {
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pci_select_window(addr, QCN9224_TCSR_PBL_LOGGING_REG);
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val = readl(addr + WINDOW_START + (QCN9224_TCSR_PBL_LOGGING_REG & WINDOW_RANGE_MASK));
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printf("Reg: TCSR_PBL_LOGGING: 0x%x\n", val);
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}
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}
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static int do_fuse_qcn9224(cmd_tbl_t *cmdtp, int flag,
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int argc, char * const argv[])
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{
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pci_dev_t devbusfn;
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int device_id = 0, ret;
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struct pci_controller *hose;
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pci_addr_t pci_mem_base, bar0_base;
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u16 vendor, device;
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uint32_t load_addr, file_size;
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u32 val = 0, version;
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if (argc != 2)
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return CMD_RET_USAGE;
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device_id = simple_strtoul(argv[1], NULL, 16);
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if (device_id > 3) {
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printf("Supported PCIe instances 0 to 3\n");
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return CMD_RET_USAGE;
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}
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devbusfn = pci_find_ipq_devices(supported_device, device_id);
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if (devbusfn == -1) {
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printf("PCIe %d not enabled\n",device_id);
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return CMD_RET_FAILURE;
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}
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hose = pci_bus_to_hose(PCI_BUS(devbusfn));
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if(hose == NULL) {
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printf("PCI controller hose is NULL\n");
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return CMD_RET_FAILURE;
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}
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pci_mem_base = hose->regions[0].bus_start;
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bar0_base = pci_mem_base + 0x400000;
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pci_read_config_word(devbusfn, PCI_VENDOR_ID, &vendor);
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pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
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printf("Fusing on Vendor ID:0x%x device ID:0x%x devbusfn:0x%x\n",
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vendor, device, devbusfn);
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pci_write_config_dword (devbusfn, PCI_COMMAND,
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(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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pci_write_config_dword (devbusfn, PCI_BASE_ADDRESS_0, bar0_base);
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/* Read QCN9224 version */
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pci_select_window(bar0_base, QCN9224_TCSR_SOC_HW_VERSION);
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version = readl(bar0_base + WINDOW_START +
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(QCN9224_TCSR_SOC_HW_VERSION & WINDOW_RANGE_MASK));
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version = (version & QCN9224_TCSR_SOC_HW_VERSION_MASK) >>
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QCN9224_TCSR_SOC_HW_VERSION_SHIFT;
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if (version == 1) {
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printk("Fusing not supported in QCN9224 V1\n");
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return CMD_RET_FAILURE;
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}
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load_addr = getenv_ulong("fileaddr", 16, 0);
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file_size = getenv_ulong("filesize", 16, 0);
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writel(0, bar0_base + BHI_STATUS);
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writel(upper_32_bits(load_addr), bar0_base + BHI_IMGADDR_HIGH);
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writel(lower_32_bits(load_addr), bar0_base + BHI_IMGADDR_LOW);
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writel(file_size, bar0_base + BHI_IMGSIZE);
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writel(1, bar0_base + BHI_IMGTXDB);
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printf("Waiting for fuse blower bin download...\n");
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ret = poll_reg_field(bar0_base + BHI_STATUS, &val, BHI_STATUS_MASK, BHI_STATUS_SHIFT, BHI_STATUS_SUCCESS);
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if (ret) {
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printf("Fuse blower bin Download failed, BHI_STATUS 0x%x, ret %d\n", val, ret);
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print_error_code(bar0_base, true);
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return CMD_RET_FAILURE;
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}
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ret = poll_reg_field(bar0_base + BHI_EXECENV, &val, NO_MASK, 0, 1);
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if (ret) {
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printf("EXECENV is not correct, BHI_EXECENV 0x%x, ret %d\n",val, ret);
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print_error_code(bar0_base, true);
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return CMD_RET_FAILURE;
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}
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printf("Fuse blower bin loaded sucessfully\n");
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ret = poll_reg_field(bar0_base + BHI_ERRCODE, &val, NO_MASK, 0, 0xCAFECACE);
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if (ret) {
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printf("Fusing failed, ret %d\n",ret);
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print_error_code(bar0_base, false);
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return CMD_RET_FAILURE;
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}
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printf("Fusing completed sucessfully\n");
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(fuse_qcn9224, 2, 1, do_fuse_qcn9224,
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"Fuse QCN9224 V2 fuses and argument is PCIe device ID",
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"If not QCN9224 V2, then fuse blow will be skipped");
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#endif
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@ -699,6 +699,7 @@ extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
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extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
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extern void pci_register_hose(struct pci_controller* hose);
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extern struct pci_controller* pci_bus_to_hose(int bus);
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extern struct pci_controller *pci_get_hose_head(void);
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extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
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extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
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