mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
MIPS: qca953x: Enable Support for AP147 Target
this change enables the support for the AP147 target Change-Id: Ia9dd0f63578107eb127410d752598081e9be2d85 Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
This commit is contained in:
Prabhu Jayakumar
Gerrit - the friendly Code Review server
parent
44bdfc09e8
commit
a700195ae9
15 changed files with 7043 additions and 0 deletions
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@ -56,6 +56,12 @@ config TARGET_QCA955X
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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config TARGET_QCA953X
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bool "Support QCA953X"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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config TARGET_PB1X00
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bool "Support pb1x00"
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select SUPPORTS_LITTLE_ENDIAN
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@ -73,6 +79,7 @@ source "board/pb1x00/Kconfig"
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source "board/qemu-mips/Kconfig"
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source "board/qca/mips32/qca956x/Kconfig"
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source "board/qca/mips32/qca955x/Kconfig"
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source "board/qca/mips32/qca953x/Kconfig"
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if MIPS
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165
board/qca/mips32/qca953x/953x.S
Normal file
165
board/qca/mips32/qca953x/953x.S
Normal file
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@ -0,0 +1,165 @@
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <atheros.h>
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/*
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* Helper macros.
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* These Clobber t7, t8 and t9
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*/
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#define reg_write(_reg, _val) \
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li t7, KSEG1ADDR(_reg); \
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li t8, _val; \
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sw t8, 0(t7);
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#define reg_rmw_set(_reg, _mask, _val) \
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li t7, KSEG1ADDR(_reg); \
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lw t8, 0(t7); \
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li t9, ~(_mask); \
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and t8, t8, t9; \
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li t9, _val; \
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or t8, t8, t9; \
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sw t8, 0(t7)
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#define cpu_pll_set(_mask, _val) \
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reg_rmw_set(CPU_PLL_CONFIG_ADDRESS, _mask, _val)
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#define ddr_pll_set(_mask, _val) \
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reg_rmw_set(DDR_PLL_CONFIG_ADDRESS, _mask, _val)
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#define cpu_ddr_control_set(_mask, _val) \
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reg_rmw_set(CPU_DDR_CLOCK_CONTROL_ADDRESS, _mask, _val)
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/******************************************************************************
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* first level initialization:
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*
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* 0) If clock cntrl reset switch is already set, we're recovering from
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* "divider reset"; goto 3.
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* 1) Setup divide ratios.
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* 2) Reset.
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* 3) Setup pll's, wait for lock.
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*
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*****************************************************************************/
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.globl lowlevel_init
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.type lowlevel_init, @function
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.text
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.align 4
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lowlevel_init:
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#if !defined(CONFIG_ATH_EMULATION)
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reg_write(BB_DPLL2_ADDRESS, BB_DPLL2_KI_SET(2) | \
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BB_DPLL2_KD_SET(0x10) | \
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BB_DPLL2_PLL_PWD_SET(1));
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reg_write(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(2) | \
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PCIe_DPLL2_KD_SET(0x10) | \
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PCIe_DPLL2_PLL_PWD_SET(1));
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reg_write(DDR_DPLL2_ADDRESS, DDR_DPLL2_KI_SET(2) | \
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DDR_DPLL2_KD_SET(0x10) | \
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DDR_DPLL2_PLL_PWD_SET(1));
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reg_write(CPU_DPLL2_ADDRESS, CPU_DPLL2_KI_SET(2) | \
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CPU_DPLL2_KD_SET(0x10) | \
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CPU_DPLL2_PLL_PWD_SET(1));
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li t5, CPU_PLL_CONFIG_NINT_VAL
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li t6, DDR_PLL_CONFIG_NINT_VAL
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li t4, CPU_PLL_DITHER_VAL
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li t3, DDR_PLL_DITHER_VAL
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li t7, PLL_CONFIG_VAL_F
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lw t8, 0(t7)
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li t7, PLL_MAGIC
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beq t7, t8, read_from_flash
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nop
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j pll_bypass_set
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nop
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read_from_flash:
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li t7, PLL_CONFIG_VAL_F + 4
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lw t5, 0(t7)
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lw t4, 4(t7)
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lw t6, 8(t7)
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lw t3, 12(t7)
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pll_bypass_set:
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
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cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
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init_cpu_pll:
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li t7, KSEG1ADDR(CPU_PLL_CONFIG_ADDRESS);
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li t8, (CPU_PLL_CONFIG_PLLPWD_SET(1) | \
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CPU_PLL_CONFIG_REF_DIV_VAL | \
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CPU_PLL_CONFIG_RANGE_VAL | \
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CPU_PLL_CONFIG_OUT_DIV_VAL1);
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or t8, t8, t5
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sw t8, 0(t7);
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init_ddr_pll:
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li t7, KSEG1ADDR(DDR_PLL_CONFIG_ADDRESS);
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li t8, (DDR_PLL_CONFIG_PLLPWD_SET(1) | \
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DDR_PLL_CONFIG_REF_DIV_VAL | \
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DDR_PLL_CONFIG_RANGE_VAL | \
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DDR_PLL_CONFIG_OUT_DIV_VAL1);
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or t8, t8, t6
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sw t8, 0(t7);
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init_ahb_pll:
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reg_write(CPU_DDR_CLOCK_CONTROL_ADDRESS,
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CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL |
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AHB_CLK_FROM_DDR |
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CLK_SRC_CONTROL |
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CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV |
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CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV |
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CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) |
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CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) |
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CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
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pll_pwd_unset:
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cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0));
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ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0));
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outdiv_unset:
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cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2);
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ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2);
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pll_bypass_unset:
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
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cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
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ddr_pll_dither_unset:
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li t7, KSEG1ADDR(DDR_PLL_DITHER_ADDRESS);
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sw t3, 0(t7);
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cpu_pll_dither_unset:
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li t7, KSEG1ADDR(CPU_PLL_DITHER_ADDRESS);
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sw t4, 0(t7);
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lui t7, 47110;
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lui t8, 1020;
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sw t8, 0xb4(t7);
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#endif /* !defined(CONFIG_ATH_EMULATION) */
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jr ra
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nop
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15
board/qca/mips32/qca953x/Kconfig
Normal file
15
board/qca/mips32/qca953x/Kconfig
Normal file
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@ -0,0 +1,15 @@
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if TARGET_QCA953X
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config SYS_CPU
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default "qca953x"
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config SYS_BOARD
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default "mips32/qca953x"
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config SYS_VENDOR
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default "qca"
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config SYS_CONFIG_NAME
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default "qca953x"
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endif
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49
board/qca/mips32/qca953x/Makefile
Normal file
49
board/qca/mips32/qca953x/Makefile
Normal file
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@ -0,0 +1,49 @@
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BOARD=board953x
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COMPRESSED_UBOOT=0
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ETH_CONFIG=_s27
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obj-y = \
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$(BOARD).o \
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flash.o \
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extra.o \
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init-953x.o \
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qca-eth-953x.o \
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../common/ath_serial.o \
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../common/ath_pci.o \
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../common/qca-mach-common.o
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ifeq ($(ATH_DUAL_FLASH),1)
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OBJS += ../../../drivers/nand/nand_ids.o
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ifeq ($(ATH_SPI_NAND),1)
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OBJS += ../common/ath_spi_nand.o
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else
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OBJS += ../common/ath_nand.o
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endif
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endif
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ifndef BOOT_FROM_NAND
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obj-y += ../common/ath_flash.o
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endif
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ifeq ($(ATH_RGMII_CAL),1)
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OBJS += ../common/rgmii-cal-953x.o
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OBJS += ../common/athrs17_lpbk.o
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endif
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ifeq ($(ETH_CONFIG), _f1e)
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OBJS += ../common/athrsf1_phy.o
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endif
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ifeq ($(ETH_CONFIG), _vir)
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OBJS += ../common/athrs_vir_phy.o
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endif
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ifeq ($(ETH_CONFIG2), _vir)
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OBJS += ../common/athrs_vir_phy.o
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endif
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ifeq ($(ETH_CONFIG), _s27)
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obj-y += ../common/athr_s27_phy.o
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endif
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obj-y += 953x.o tap-953x.o
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149
board/qca/mips32/qca953x/board953x.c
Normal file
149
board/qca/mips32/qca953x/board953x.c
Normal file
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@ -0,0 +1,149 @@
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <config.h>
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#include <version.h>
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#include <atheros.h>
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extern int ath_ddr_initial_config(uint32_t refresh);
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extern int ath_ddr_find_size(void);
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#ifdef COMPRESSED_UBOOT
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# define prmsg(...)
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# define args char *s
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# define board_str(a) do { \
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char ver[] = "0"; \
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uint32_t revid; \
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \
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strcpy(s, a " - Honey Bee 1."); \
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else \
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strcpy(s, a " - Honey Bee 2."); \
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ver[0] += (revid & 0xf) ; \
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strcat(s, ver); \
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} while (0)
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#else
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# define prmsg printf
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# define args void
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# define board_str(a) \
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uint32_t revid; \
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \
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printf(a " - Honey Bee 1.%d", revid & 0xf); \
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else \
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printf(a " - Honey Bee 2.%d", revid & 0xf);
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#endif
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void
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ath_usb_initial_config(void)
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{
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#define unset(a) (~(a))
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if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
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ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1));
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udelay(1000);
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ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1));
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udelay(1000);
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ath_reg_wr(PHY_CTRL5_ADDRESS, PHY_CTRL5_RESET_1);
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udelay(1000);
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ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1));
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udelay(1000);
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ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1));
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udelay(1000);
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ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_USB1_SET(1));
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return;
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}
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ath_reg_wr_nf(SWITCH_CLOCK_SPARE_ADDRESS,
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ath_reg_rd(SWITCH_CLOCK_SPARE_ADDRESS) |
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SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(2));
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udelay(1000);
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ath_reg_rmw_set(RST_RESET_ADDRESS,
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RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1));
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udelay(1000);
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ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1));
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udelay(1000);
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ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1));
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udelay(1000);
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ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1));
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udelay(1000);
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ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1));
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udelay(10);
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}
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void ath_gpio_config(void)
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{
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/* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */
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ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 4));
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ath_reg_rmw_clear(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80));
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ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 4));
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/* Set GPIO 13 as input for LED functionality to be OFF during bootup */
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ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 13));
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/* Turn off JUMPST_LED and 5Gz LED during bootup */
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ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 15));
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ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 12));
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}
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int
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ath_mem_config(void)
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{
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unsigned int type, reg32, *tap;
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extern uint32_t *ath_ddr_tap_cal(void);
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#if !defined(CONFIG_ATH_EMULATION)
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type = ath_ddr_initial_config(CFG_DDR_REFRESH_VAL);
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tap = ath_ddr_tap_cal();
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prmsg("tap = 0x%p\n", tap);
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tap = (uint32_t *)0xbd001f10;
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prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]);
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tap = (uint32_t *)TAP_CONTROL_0_ADDRESS;
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prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
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tap[0], tap[2], tap[2], tap[3]);
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/* Take WMAC out of reset */
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reg32 = ath_reg_rd(RST_RESET_ADDRESS);
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reg32 = reg32 & ~RST_RESET_RTC_RESET_SET(1);
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ath_reg_wr_nf(RST_RESET_ADDRESS, reg32);
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ath_usb_initial_config();
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ath_gpio_config();
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#endif /* !defined(CONFIG_ATH_EMULATION) */
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return ath_ddr_find_size();
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}
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phys_size_t initdram(int board_type)
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{
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return (ath_mem_config());
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}
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int checkboard(args)
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{
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board_str(CONFIG_BOARD_NAME);
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return 0;
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}
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77
board/qca/mips32/qca953x/extra.c
Normal file
77
board/qca/mips32/qca953x/extra.c
Normal file
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@ -0,0 +1,77 @@
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
/*#include <config.h>*/
|
||||
#include <version.h>
|
||||
#include <atheros.h>
|
||||
|
||||
int ath_set_tuning_caps(void)
|
||||
{
|
||||
typedef struct {
|
||||
u_int8_t pad[0x28],
|
||||
params_for_tuning_caps[2],
|
||||
featureEnable;
|
||||
} __attribute__((__packed__)) ar9300_eeprom_t;
|
||||
|
||||
ar9300_eeprom_t *eep;
|
||||
uint32_t val;
|
||||
|
||||
eep = (ar9300_eeprom_t *)WLANCAL;
|
||||
|
||||
val = XTAL_TCXODET_SET(0x0) |
|
||||
XTAL_XTAL_CAPINDAC_SET(0x4b) |
|
||||
XTAL_XTAL_CAPOUTDAC_SET(0x4b) |
|
||||
XTAL_XTAL_DRVSTR_SET(0x3) |
|
||||
XTAL_XTAL_SHORTXIN_SET(0x0) |
|
||||
XTAL_XTAL_LOCALBIAS_SET(0x1) |
|
||||
XTAL_XTAL_PWDCLKD_SET(0x0) |
|
||||
XTAL_XTAL_BIAS2X_SET(0x0) |
|
||||
XTAL_XTAL_LBIAS2X_SET(0x0) |
|
||||
XTAL_XTAL_OSCON_SET(0x1) |
|
||||
XTAL_XTAL_PWDCLKIN_SET(0x0) |
|
||||
XTAL_LOCAL_XTAL_SET(0x0) |
|
||||
XTAL_PWD_SWREGCLK_SET(0x0) |
|
||||
XTAL_SPARE_SET(0x0);
|
||||
|
||||
/* checking feature enable bit 6 and caldata is valid */
|
||||
if ((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)) {
|
||||
val &= ~(XTAL_XTAL_CAPINDAC_MASK | XTAL_XTAL_CAPOUTDAC_MASK);
|
||||
val |= XTAL_XTAL_CAPINDAC_SET(eep->params_for_tuning_caps[0]) |
|
||||
XTAL_XTAL_CAPOUTDAC_SET(eep->params_for_tuning_caps[0]);
|
||||
}
|
||||
|
||||
ath_reg_wr(XTAL_ADDRESS, val);
|
||||
ath_reg_wr(XTAL2_ADDRESS, XTAL2_DCA_BYPASS_SET(0x1) |
|
||||
XTAL2_FSM_START_L_SET(0x1));
|
||||
ath_reg_wr(XTAL3_ADDRESS, XTAL3_EVAL_LENGTH_SET(0x400) |
|
||||
XTAL3_HARMONIC_NUMBER_SET(0x51));
|
||||
|
||||
#define __str(x) # x
|
||||
#define str(x) __str(x)
|
||||
|
||||
printf("Setting " str(XTAL_ADDRESS) " to 0x%x\n", val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LAST_STAGE_INIT
|
||||
int last_stage_init(void)
|
||||
{
|
||||
ath_set_tuning_caps();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
44
board/qca/mips32/qca953x/flash.c
Normal file
44
board/qca/mips32/qca953x/flash.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/types.h>
|
||||
#include <flash.h>
|
||||
|
||||
/*
|
||||
* sets up flash_info and returns size of FLASH (bytes)
|
||||
*/
|
||||
unsigned long
|
||||
flash_get_geom (flash_info_t *flash_info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* XXX this is hardcoded until we figure out how to read flash id */
|
||||
|
||||
flash_info->flash_id = FLASH_M25P64;
|
||||
flash_info->size = CFG_FLASH_SIZE; /* bytes */
|
||||
flash_info->sector_count = flash_info->size / CFG_FLASH_SECTOR_SIZE;
|
||||
|
||||
for (i = 0; i < flash_info->sector_count; i++) {
|
||||
flash_info->start[i] = CFG_FLASH_BASE +
|
||||
(i * CFG_FLASH_SECTOR_SIZE);
|
||||
flash_info->protect[i] = 0;
|
||||
}
|
||||
|
||||
printf ("flash size %dMB, sector count = %d\n",
|
||||
FLASH_SIZE, flash_info->sector_count);
|
||||
|
||||
return (flash_info->size);
|
||||
}
|
||||
389
board/qca/mips32/qca953x/init-953x.c
Normal file
389
board/qca/mips32/qca953x/init-953x.c
Normal file
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <atheros.h>
|
||||
|
||||
#define ATH_MAX_DDR_SIZE (256 * 1024 * 1024)
|
||||
#define ATH_DDR_SIZE_INCR (4 * 1024 * 1024)
|
||||
|
||||
int
|
||||
ath_ddr_find_size(void)
|
||||
{
|
||||
uint8_t *p = (uint8_t *)KSEG1, pat = 0x77;
|
||||
int i;
|
||||
|
||||
#define max_i (ATH_MAX_DDR_SIZE / ATH_DDR_SIZE_INCR)
|
||||
|
||||
*p = pat;
|
||||
|
||||
/*
|
||||
* DDR wraps around. Write a pattern to 0x0000_0000. Write an
|
||||
* address pattern at 4M, 8M, 16M etc. and check when
|
||||
* 0x0000_0000 gets overwritten.
|
||||
*/
|
||||
for(i = 1; (i < max_i); i++) {
|
||||
*(p + i * ATH_DDR_SIZE_INCR) = (uint8_t)(i);
|
||||
if (*p != pat) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ((i < max_i) ? (i * ATH_DDR_SIZE_INCR) : ATH_MAX_DDR_SIZE);
|
||||
}
|
||||
|
||||
inline int
|
||||
ath_ram_type(uint32_t bs)
|
||||
{
|
||||
if (RST_BOOTSTRAP_DDR_SELECT_GET(bs)) {
|
||||
return ATH_MEM_DDR1;
|
||||
} else {
|
||||
return ATH_MEM_DDR2;
|
||||
}
|
||||
}
|
||||
|
||||
#define CFG_DDR2_SCORPION_CAS_LATENCY 4
|
||||
|
||||
#ifdef CONFIG_TB614
|
||||
# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x1)
|
||||
#else
|
||||
# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x0)
|
||||
#endif
|
||||
|
||||
#if CFG_DDR2_SCORPION_CAS_LATENCY == 4
|
||||
#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
|
||||
DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
|
||||
DDR_CONFIG_CAS_LATENCY_SET(0x1) | \
|
||||
DDR_CONFIG_TMRD_SET(0xf) | \
|
||||
DDR_CONFIG_TRFC_SET(0x15) | \
|
||||
DDR_CONFIG_TRRD_SET(0x7) | \
|
||||
DDR_CONFIG_TRP_SET(0x9) | \
|
||||
DDR_CONFIG_TRCD_SET(0x9) | \
|
||||
DDR_CONFIG_TRAS_SET(0x1b)
|
||||
|
||||
#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
|
||||
DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \
|
||||
DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x8) | \
|
||||
DDR_CONFIG2_TWTR_SET(0x15) | \
|
||||
DDR_CONFIG2_TRTP_SET(0x9) | \
|
||||
DDR_CONFIG2_TRTW_SET(0xe) | \
|
||||
DDR_CONFIG2_TWR_SET(0x1) | \
|
||||
DDR_CONFIG2_CKE_SET(0x1) | \
|
||||
DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
|
||||
DDR_CONFIG2_BURST_LENGTH_SET(0x8)
|
||||
|
||||
#define CFG_DDR2_CONFIG3_VAL 0x0000000a
|
||||
#define CFG_DDR2_EXT_MODE_VAL 0x402
|
||||
#define CFG_DDR2_MODE_VAL_INIT 0x143
|
||||
#define CFG_DDR2_MODE_VAL 0x43
|
||||
#define CFG_DDR2_TAP_VAL 0x10
|
||||
#define CFG_DDR2_EN_TWL_VAL 0x0000167d
|
||||
#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
|
||||
#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
|
||||
|
||||
#elif CFG_DDR2_SCORPION_CAS_LATENCY == 5
|
||||
|
||||
#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
|
||||
DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
|
||||
DDR_CONFIG_CAS_LATENCY_SET(0x4) | \
|
||||
DDR_CONFIG_TMRD_SET(0xf) | \
|
||||
DDR_CONFIG_TRFC_SET(0x15) | \
|
||||
DDR_CONFIG_TRRD_SET(0x7) | \
|
||||
DDR_CONFIG_TRP_SET(0x9) | \
|
||||
DDR_CONFIG_TRCD_SET(0x9) | \
|
||||
DDR_CONFIG_TRAS_SET(0x1b)
|
||||
|
||||
#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
|
||||
DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \
|
||||
DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xb) | \
|
||||
DDR_CONFIG2_TWTR_SET(0x15) | \
|
||||
DDR_CONFIG2_TRTP_SET(0x9) | \
|
||||
DDR_CONFIG2_TRTW_SET(0xe) | \
|
||||
DDR_CONFIG2_TWR_SET(0x1) | \
|
||||
DDR_CONFIG2_CKE_SET(0x1) | \
|
||||
DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
|
||||
DDR_CONFIG2_BURST_LENGTH_SET(0x8)
|
||||
|
||||
#define CFG_DDR2_CONFIG3_VAL 0x0000000a
|
||||
#define CFG_DDR2_EXT_MODE_VAL 0x402
|
||||
#define CFG_DDR2_MODE_VAL_INIT 0x153
|
||||
#define CFG_DDR2_MODE_VAL 0x53
|
||||
#define CFG_DDR2_TAP_VAL 0x10
|
||||
#define CFG_DDR2_EN_TWL_VAL 0x00001e7d
|
||||
#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
|
||||
#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
|
||||
#endif
|
||||
|
||||
#define CFG_DDR1_CONFIG_VAL DDR_CONFIG_OPEN_PAGE_SET(0x1) | \
|
||||
DDR_CONFIG_CAS_LATENCY_SET(0x7) | \
|
||||
DDR_CONFIG_TMRD_SET(0x5) | \
|
||||
DDR_CONFIG_TRFC_SET(0x7) | \
|
||||
DDR_CONFIG_TRRD_SET(0x4) | \
|
||||
DDR_CONFIG_TRP_SET(0x6) | \
|
||||
DDR_CONFIG_TRCD_SET(0x6) | \
|
||||
DDR_CONFIG_TRAS_SET(0x10)
|
||||
|
||||
#define CFG_DDR1_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
|
||||
DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x6) | \
|
||||
DDR_CONFIG2_TWTR_SET(0xe) | \
|
||||
DDR_CONFIG2_TRTP_SET(0x8) | \
|
||||
DDR_CONFIG2_TRTW_SET(0xe) | \
|
||||
DDR_CONFIG2_TWR_SET(0xd) | \
|
||||
DDR_CONFIG2_CKE_SET(0x1) | \
|
||||
DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
|
||||
DDR_CONFIG2_BURST_LENGTH_SET(0x8)
|
||||
#define CFG_DDR1_CONFIG3_VAL 0x0
|
||||
#define CFG_DDR1_EXT_MODE_VAL 0x0
|
||||
#define CFG_DDR1_MODE_VAL_INIT 0x133
|
||||
#define CFG_DDR1_MODE_VAL 0x33
|
||||
#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16 0xffff
|
||||
#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_32 0xff
|
||||
#define CFG_DDR1_TAP_VAL 0x20
|
||||
|
||||
#define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \
|
||||
DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \
|
||||
DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \
|
||||
DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \
|
||||
DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \
|
||||
DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1)
|
||||
|
||||
int /* ram type */
|
||||
ath_ddr_initial_config(uint32_t refresh)
|
||||
{
|
||||
#if !defined(CONFIG_ATH_EMULATION)
|
||||
int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
|
||||
mod_val_init, cycle_val, tap_val, type, ctl_config;
|
||||
uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
|
||||
uint32_t bootstrap,revid;
|
||||
|
||||
prmsg("\nsri\n");
|
||||
if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140)
|
||||
prmsg("Honey Bee 1.%d\n", revid & 0xf);
|
||||
else
|
||||
prmsg("Honey Bee 2.%d\n", revid & 0xf);
|
||||
|
||||
bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
|
||||
|
||||
switch(type = ath_ram_type(bootstrap)) {
|
||||
case ATH_MEM_DDR2:
|
||||
ddr_config = CFG_DDR2_CONFIG_VAL;
|
||||
ddr_config2 = CFG_DDR2_CONFIG2_VAL;
|
||||
ddr_config3 = CFG_DDR2_CONFIG3_VAL;
|
||||
ext_mod = CFG_DDR2_EXT_MODE_VAL;
|
||||
mod_val_init = CFG_DDR2_MODE_VAL_INIT;
|
||||
mod_val = CFG_DDR2_MODE_VAL;
|
||||
tap_val = CFG_DDR2_TAP_VAL;
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10);
|
||||
udelay(10);
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20);
|
||||
udelay(10);
|
||||
prmsg("%s(%d): (", __func__, __LINE__);
|
||||
|
||||
prmsg("16");
|
||||
ctl_config = CFG_DDR_CTL_CONFIG |
|
||||
CPU_DDR_SYNC_MODE |
|
||||
DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) |
|
||||
DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1);
|
||||
|
||||
cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
|
||||
|
||||
ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config);
|
||||
|
||||
prmsg("bit) ddr2 init\n");
|
||||
udelay(10);
|
||||
break;
|
||||
case ATH_MEM_DDR1:
|
||||
ddr_config = CFG_DDR1_CONFIG_VAL;
|
||||
ddr_config2 = CFG_DDR1_CONFIG2_VAL;
|
||||
ddr_config3 = CFG_DDR1_CONFIG3_VAL;
|
||||
ext_mod = CFG_DDR1_EXT_MODE_VAL;
|
||||
mod_val_init = CFG_DDR1_MODE_VAL_INIT;
|
||||
mod_val = CFG_DDR1_MODE_VAL;
|
||||
tap_val = CFG_DDR1_TAP_VAL;
|
||||
|
||||
prmsg("%s(%d): (", __func__, __LINE__);
|
||||
prmsg("16");
|
||||
cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16;
|
||||
|
||||
ctl_config = CFG_DDR_CTL_CONFIG |
|
||||
CPU_DDR_SYNC_MODE |
|
||||
DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1);
|
||||
|
||||
ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config);
|
||||
udelay(10);
|
||||
prmsg("bit) ddr1 init\n");
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
ath_reg_wr_nf(DDR_RD_DATA_THIS_CYCLE_ADDRESS, cycle_val);
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_BURST_ADDRESS, 0x74444444);
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_BURST2_ADDRESS, 0x4);
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS, 0xfffff);
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_CONFIG_ADDRESS, ddr_config);
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2);
|
||||
udelay(100);
|
||||
ath_reg_wr(DDR_CONFIG_3_ADDRESS, ddr_config3);
|
||||
udelay(100);
|
||||
|
||||
if (type == ATH_MEM_DDR2) {
|
||||
ath_reg_wr_nf(DDR2_CONFIG_ADDRESS, CFG_DDR2_EN_TWL_VAL);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2 | 0x80); // CKE Enable
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge
|
||||
udelay(10);
|
||||
|
||||
if (type == ATH_MEM_DDR2) {
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10); // EMR2
|
||||
udelay(10);
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20); // EMR3
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
if (type == ATH_MEM_DDR1 || type == ATH_MEM_DDR2) {
|
||||
ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL); // EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled
|
||||
udelay(100);
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val_init);
|
||||
udelay(1000);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR Write
|
||||
udelay(10);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge
|
||||
udelay(10);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh
|
||||
udelay(10);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh
|
||||
udelay(10);
|
||||
|
||||
// Issue MRS to remove DLL out-of-reset
|
||||
ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val);
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR write
|
||||
udelay(100);
|
||||
|
||||
if (type == ATH_MEM_DDR2) {
|
||||
ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, 0x782);
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL);
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
ath_reg_wr_nf(DDR_REFRESH_ADDRESS, refresh);
|
||||
udelay(100);
|
||||
|
||||
ath_reg_wr(TAP_CONTROL_0_ADDRESS, tap_val);
|
||||
ath_reg_wr(TAP_CONTROL_1_ADDRESS, tap_val);
|
||||
|
||||
ath_reg_wr(PMU1_ADDRESS, 0x633c8178);
|
||||
// Set DDR2 Voltage to 1.8 volts
|
||||
ath_reg_wr(PMU2_ADDRESS, PMU2_SWREGMSB_SET(0x40) | PMU2_PGM_SET(0x1) | PMU2_LDO_TUNE_SET(0x0));
|
||||
|
||||
ath_sys_frequency();
|
||||
|
||||
return type;
|
||||
#else // !emulation
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int
|
||||
ath_uart_freq(void)
|
||||
{
|
||||
//if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_REF_CLK_MASK) {
|
||||
// return 40 * 1000 * 1000;
|
||||
//} else {
|
||||
return 25 * 1000 * 1000;
|
||||
//}
|
||||
}
|
||||
|
||||
void ath_sys_frequency()
|
||||
{
|
||||
#if !defined(CONFIG_ATH_EMULATION)
|
||||
uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl;
|
||||
#endif
|
||||
uint32_t ref = ath_uart_freq();
|
||||
uint32_t ath_cpu_freq = 0, ath_ddr_freq = 0, ath_ahb_freq = 0;
|
||||
|
||||
if (ath_cpu_freq)
|
||||
goto done;
|
||||
|
||||
#ifdef CONFIG_ATH_EMULATION
|
||||
ath_cpu_freq = 80000000;
|
||||
ath_ddr_freq = 80000000;
|
||||
ath_ahb_freq = 40000000;
|
||||
#else
|
||||
prmsg("%s: ", __func__);
|
||||
|
||||
clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
|
||||
|
||||
pll = ath_reg_rd(ATH_PLL_CONFIG);
|
||||
out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll);
|
||||
ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll);
|
||||
nint = CPU_PLL_CONFIG_NINT_GET(pll);
|
||||
frac = CPU_PLL_CONFIG_NFRAC_GET(pll);
|
||||
pll = ref >> 6;
|
||||
frac = frac * pll / ref_div;
|
||||
ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
|
||||
(CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1);
|
||||
|
||||
pll = ath_reg_rd(ATH_DDR_PLL_CONFIG);
|
||||
out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll);
|
||||
ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll);
|
||||
nint = DDR_PLL_CONFIG_NINT_GET(pll);
|
||||
frac = DDR_PLL_CONFIG_NFRAC_GET(pll);
|
||||
pll = ref >> 10;
|
||||
frac = frac * pll / ref_div;
|
||||
ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
|
||||
(CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1);
|
||||
|
||||
if (CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
|
||||
ath_ahb_freq = ath_ddr_freq /
|
||||
(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1);
|
||||
} else {
|
||||
ath_ahb_freq = ath_cpu_freq /
|
||||
(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1);
|
||||
}
|
||||
#endif
|
||||
done:
|
||||
prmsg("cpu %u ddr %u ahb %u\n",
|
||||
ath_cpu_freq / 1000000,
|
||||
ath_ddr_freq / 1000000,
|
||||
ath_ahb_freq / 1000000);
|
||||
}
|
||||
711
board/qca/mips32/qca953x/qca-eth-953x.c
Normal file
711
board/qca/mips32/qca953x/qca-eth-953x.c
Normal file
|
|
@ -0,0 +1,711 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
#include <atheros.h>
|
||||
#include "qca-eth-953x.h"
|
||||
#include "qca-eth-953x_phy.h"
|
||||
#define SGMII_LINK_WAR_MAX_TRY 10
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
#endif
|
||||
#define ath_gmac_unit2mac(_unit) ath_gmac_macs[(_unit)]
|
||||
#define ath_gmac_name2mac(name) is_drqfn() ? ath_gmac_unit2mac(1):strcmp(name,"eth0") ? ath_gmac_unit2mac(1) : ath_gmac_unit2mac(0)
|
||||
|
||||
int ath_gmac_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg, uint16_t *data);
|
||||
int ath_gmac_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data);
|
||||
|
||||
#ifndef CFG_ATH_GMAC_NMACS
|
||||
#define CFG_ATH_GMAC_NMACS 1
|
||||
#endif /* CFG_ATH_GMAC_NMACS */
|
||||
|
||||
ath_gmac_mac_t *ath_gmac_macs[CFG_ATH_GMAC_NMACS];
|
||||
|
||||
|
||||
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
#define is_s27() 1
|
||||
|
||||
#else
|
||||
#define is_s27() 0
|
||||
|
||||
#endif
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
extern void athrs27_reg_init(void);
|
||||
extern void athrs27_reg_init_wan(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
extern int athr_vir_phy_setup(int unit);
|
||||
extern int athr_vir_phy_is_up(int unit);
|
||||
extern int athr_vir_phy_is_fdx(int unit);
|
||||
extern int athr_vir_phy_speed(int unit);
|
||||
extern void athr_vir_reg_init(void);
|
||||
#endif
|
||||
|
||||
static int
|
||||
ath_gmac_send(struct eth_device *dev, volatile void *packet, int length)
|
||||
{
|
||||
int i;
|
||||
|
||||
ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv;
|
||||
|
||||
ath_gmac_desc_t *f = mac->fifo_tx[mac->next_tx];
|
||||
|
||||
f->pkt_size = length;
|
||||
f->res1 = 0;
|
||||
f->pkt_start_addr = virt_to_phys(packet);
|
||||
|
||||
ath_gmac_tx_give_to_dma(f);
|
||||
flush_cache((u32) packet, length);
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_TX_DESC, virt_to_phys(f));
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_TX_CTRL, ATH_TXE);
|
||||
|
||||
for (i = 0; i < MAX_WAIT; i++) {
|
||||
udelay(10);
|
||||
if (!ath_gmac_tx_owned_by_dma(f))
|
||||
break;
|
||||
}
|
||||
if (i == MAX_WAIT)
|
||||
printf("Tx Timed out\n");
|
||||
|
||||
f->pkt_start_addr = 0;
|
||||
f->pkt_size = 0;
|
||||
|
||||
if (++mac->next_tx >= NO_OF_TX_FIFOS)
|
||||
mac->next_tx = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int ath_gmac_recv(struct eth_device *dev)
|
||||
{
|
||||
int length;
|
||||
ath_gmac_desc_t *f;
|
||||
ath_gmac_mac_t *mac;
|
||||
volatile int dmaed_pkt=0;
|
||||
int count = 0;
|
||||
|
||||
mac = (ath_gmac_mac_t *)dev->priv;
|
||||
|
||||
for (;;) {
|
||||
f = mac->fifo_rx[mac->next_rx];
|
||||
if (ath_gmac_rx_owned_by_dma(f)) {
|
||||
/* check if the current Descriptor is_empty is 1,But the DMAed count is not-zero
|
||||
then move to desciprot where the packet is available */
|
||||
dmaed_pkt = (ath_gmac_reg_rd(mac, 0x194) >> 16);
|
||||
if (!dmaed_pkt) {
|
||||
break ;
|
||||
} else {
|
||||
if (f->is_empty == 1) {
|
||||
while (count < NO_OF_RX_FIFOS) {
|
||||
if (++mac->next_rx >= NO_OF_RX_FIFOS) {
|
||||
mac->next_rx = 0;
|
||||
}
|
||||
f = mac->fifo_rx[mac->next_rx];
|
||||
/*
|
||||
* Break on valid data in the desc by checking
|
||||
* empty bit.
|
||||
*/
|
||||
if (!f->is_empty) {
|
||||
count = 0;
|
||||
break;
|
||||
}
|
||||
count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
length = f->pkt_size;
|
||||
|
||||
net_process_received_packet(net_rx_packets[mac->next_rx] , length - 4);
|
||||
flush_cache((u32) net_rx_packets[mac->next_rx] , PKTSIZE_ALIGN);
|
||||
|
||||
ath_gmac_reg_wr(mac,0x194,1);
|
||||
ath_gmac_rx_give_to_dma(f);
|
||||
|
||||
if (++mac->next_rx >= NO_OF_RX_FIFOS)
|
||||
mac->next_rx = 0;
|
||||
}
|
||||
|
||||
if (!(ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL))) {
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(f));
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, 1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void ath_gmac_mii_setup(ath_gmac_mac_t *mac)
|
||||
{
|
||||
u32 mgmt_cfg_val;
|
||||
|
||||
ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x231);
|
||||
//ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x520);
|
||||
if ((mac->mac_unit == 1)) {
|
||||
printf("Honey Bee ----> MAC 1 S27 PHY *\n");
|
||||
ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
|
||||
ETH_CFG_ETH_RXD_DELAY_SET(3)|
|
||||
ETH_CFG_RGMII_GE0_SET(1));
|
||||
|
||||
ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) |
|
||||
ETH_XMII_RX_DELAY_SET(2) |
|
||||
ETH_XMII_TX_DELAY_SET(1) |
|
||||
ETH_XMII_GIGE_SET(1));
|
||||
mgmt_cfg_val = 2;
|
||||
udelay(1000);
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
|
||||
return;
|
||||
}
|
||||
|
||||
if (is_vir_phy()) {
|
||||
printf("Honey Bee ---->VIR PHY*\n");
|
||||
|
||||
ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
|
||||
ETH_CFG_ETH_RXD_DELAY_SET(3)|
|
||||
ETH_CFG_RGMII_GE0_SET(1));
|
||||
ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) |
|
||||
ETH_XMII_RX_DELAY_SET(2) |
|
||||
ETH_XMII_TX_DELAY_SET(1) |
|
||||
ETH_XMII_GIGE_SET(1));
|
||||
udelay(1000);
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
|
||||
|
||||
return;
|
||||
}
|
||||
if (is_s27()) {
|
||||
mgmt_cfg_val = 2;
|
||||
printf("Honey Bee ---->S27 PHY*\n");
|
||||
ath_reg_wr(ETH_CFG_ADDRESS, ETH_CFG_MII_GE0_SET(1)|
|
||||
ETH_CFG_MII_GE0_SLAVE_SET(1));
|
||||
udelay(1000);
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void ath_gmac_hw_start(ath_gmac_mac_t *mac)
|
||||
{
|
||||
|
||||
|
||||
if(mac->mac_unit)
|
||||
{
|
||||
ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN |
|
||||
ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_1000));
|
||||
} else {
|
||||
|
||||
|
||||
ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN |
|
||||
ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_10_100));
|
||||
}
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00);
|
||||
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_1, 0x10ffff);
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_2, 0xAAA0555);
|
||||
|
||||
ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_4, 0x3ffff);
|
||||
/*
|
||||
* Setting Drop CRC Errors, Pause Frames,Length Error frames
|
||||
* and Multi/Broad cast frames.
|
||||
*/
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_5, 0x7eccf);
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_3, 0x1f00140);
|
||||
|
||||
printf(": cfg1 %#x cfg2 %#x\n", ath_gmac_reg_rd(mac, ATH_MAC_CFG1),
|
||||
ath_gmac_reg_rd(mac, ATH_MAC_CFG2));
|
||||
|
||||
|
||||
}
|
||||
|
||||
static int ath_gmac_check_link(ath_gmac_mac_t *mac)
|
||||
{
|
||||
int link, duplex, speed;
|
||||
|
||||
ath_gmac_phy_link(mac->mac_unit, &link);
|
||||
ath_gmac_phy_duplex(mac->mac_unit, &duplex);
|
||||
ath_gmac_phy_speed(mac->mac_unit, &speed);
|
||||
|
||||
mac->link = link;
|
||||
|
||||
if(!mac->link) {
|
||||
printf("%s link down\n",mac->dev->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (speed)
|
||||
{
|
||||
case _1000BASET:
|
||||
ath_gmac_set_mac_if(mac, 1);
|
||||
ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
|
||||
break;
|
||||
|
||||
case _100BASET:
|
||||
ath_gmac_set_mac_if(mac, 0);
|
||||
ath_gmac_set_mac_speed(mac, 1);
|
||||
ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
|
||||
break;
|
||||
|
||||
case _10BASET:
|
||||
ath_gmac_set_mac_if(mac, 0);
|
||||
ath_gmac_set_mac_speed(mac, 0);
|
||||
ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19));
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Invalid speed detected\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
|
||||
return 1;
|
||||
|
||||
mac->duplex = duplex;
|
||||
mac->speed = speed;
|
||||
|
||||
printf("dup %d speed %d\n", duplex, speed);
|
||||
|
||||
ath_gmac_set_mac_duplex(mac,duplex);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* For every command we re-setup the ring and start with clean h/w rx state
|
||||
*/
|
||||
static int ath_gmac_clean_rx(struct eth_device *dev, bd_t * bd)
|
||||
{
|
||||
|
||||
int i;
|
||||
ath_gmac_desc_t *fr;
|
||||
ath_gmac_mac_t *mac = (ath_gmac_mac_t*)dev->priv;
|
||||
|
||||
if (!ath_gmac_check_link(mac)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mac->next_rx = 0;
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00);
|
||||
ath_gmac_reg_wr(mac, ATH_MAC_CFG1, (ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
|
||||
|
||||
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
|
||||
fr = mac->fifo_rx[i];
|
||||
fr->pkt_start_addr = virt_to_phys(net_rx_packets[i]);
|
||||
flush_cache((u32) net_rx_packets[i], PKTSIZE_ALIGN);
|
||||
ath_gmac_rx_give_to_dma(fr);
|
||||
}
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
|
||||
ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, ATH_RXE); /* rx start */
|
||||
udelay(1000 * 1000);
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
static int ath_gmac_alloc_fifo(int ndesc, ath_gmac_desc_t ** fifo)
|
||||
{
|
||||
int i;
|
||||
u32 size;
|
||||
uchar *p = NULL;
|
||||
|
||||
size = sizeof(ath_gmac_desc_t) * ndesc;
|
||||
size += CONFIG_SYS_CACHELINE_SIZE - 1;
|
||||
|
||||
if ((p = malloc(size)) == NULL) {
|
||||
printf("Cant allocate fifos\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
p = (uchar *) (((u32) p + CONFIG_SYS_CACHELINE_SIZE - 1) &
|
||||
~(CONFIG_SYS_CACHELINE_SIZE - 1));
|
||||
|
||||
/* gmac descriptors got overwritten due to cache invalidation issue. So , flush_cache is needed here*/
|
||||
flush_cache((u32)p, (sizeof(ath_gmac_desc_t) * ndesc));
|
||||
|
||||
p = UNCACHED_SDRAM(p);
|
||||
|
||||
for (i = 0; i < ndesc; i++)
|
||||
{
|
||||
fifo[i] = (ath_gmac_desc_t *) p + i;
|
||||
memset(fifo[i], 0, sizeof (ath_gmac_desc_t));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath_gmac_setup_fifos(ath_gmac_mac_t *mac)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (ath_gmac_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx))
|
||||
return 1;
|
||||
|
||||
for (i = 0; i < NO_OF_TX_FIFOS; i++) {
|
||||
mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ?
|
||||
virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);
|
||||
ath_gmac_tx_own(mac->fifo_tx[i]);
|
||||
}
|
||||
|
||||
if (ath_gmac_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx))
|
||||
return 1;
|
||||
|
||||
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
|
||||
mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ?
|
||||
virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);
|
||||
}
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
static void ath_gmac_halt(struct eth_device *dev)
|
||||
{
|
||||
ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv;
|
||||
ath_gmac_reg_rmw_clear(mac, ATH_MAC_CFG1,(ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
|
||||
ath_gmac_reg_wr(mac,ATH_MAC_FIFO_CFG_0,0x1f1f);
|
||||
ath_gmac_reg_wr(mac,ATH_DMA_RX_CTRL, 0);
|
||||
while (ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL));
|
||||
}
|
||||
|
||||
unsigned char *
|
||||
ath_gmac_mac_addr_loc(void)
|
||||
{
|
||||
#ifdef BOARDCAL
|
||||
/*
|
||||
** BOARDCAL environmental variable has the address of the cal sector
|
||||
*/
|
||||
|
||||
return ((unsigned char *)BOARDCAL);
|
||||
|
||||
#else
|
||||
/* MAC address is store in the 2nd 4k of last sector */
|
||||
return ((unsigned char *)
|
||||
(KSEG1ADDR(ATH_SPI_BASE) + (4 * 1024) +
|
||||
flash_info[0].size - (64 * 1024) /* sector_size */ ));
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ath_gmac_get_ethaddr(struct eth_device *dev)
|
||||
{
|
||||
unsigned char *eeprom;
|
||||
unsigned char *mac = dev->enetaddr;
|
||||
#ifndef CONFIG_ATH_EMULATION
|
||||
|
||||
eeprom = ath_gmac_mac_addr_loc();
|
||||
|
||||
if (strcmp(dev->name, "eth0") == 0) {
|
||||
memcpy(mac, eeprom, 6);
|
||||
} else if (strcmp(dev->name, "eth1") == 0) {
|
||||
eeprom += 6;
|
||||
memcpy(mac, eeprom, 6);
|
||||
} else {
|
||||
printf("%s: unknown ethernet device %s\n", __func__, dev->name);
|
||||
return;
|
||||
}
|
||||
/* Use fixed address if the above address is invalid */
|
||||
if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff))
|
||||
#else
|
||||
if (1)
|
||||
#endif
|
||||
{
|
||||
mac[0] = 0x00;
|
||||
mac[1] = 0x03;
|
||||
mac[2] = 0x7f;
|
||||
mac[3] = 0x09;
|
||||
mac[4] = 0x0b;
|
||||
mac[5] = 0xad;
|
||||
printf("No valid address in Flash. Using fixed address\n");
|
||||
} else {
|
||||
printf("Fetching MAC Address from 0x%p\n", __func__, eeprom);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
athr_mgmt_init(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_MGMT_INIT
|
||||
uint32_t rddata;
|
||||
|
||||
rddata = ath_reg_rd(GPIO_IN_ENABLE3_ADDRESS)&
|
||||
~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
|
||||
rddata |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
|
||||
ath_reg_wr(GPIO_IN_ENABLE3_ADDRESS, rddata);
|
||||
|
||||
ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 19));
|
||||
|
||||
ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 17));
|
||||
|
||||
|
||||
rddata = ath_reg_rd(GPIO_OUT_FUNCTION4_ADDRESS) &
|
||||
~ (GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK |
|
||||
GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
|
||||
|
||||
rddata |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) |
|
||||
GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
|
||||
|
||||
ath_reg_wr(GPIO_OUT_FUNCTION4_ADDRESS, rddata);
|
||||
#endif
|
||||
printf ("%s ::done\n",__func__);
|
||||
}
|
||||
|
||||
int ath_gmac_enet_initialize(bd_t * bis)
|
||||
{
|
||||
struct eth_device *dev[CFG_ATH_GMAC_NMACS];
|
||||
u32 mask, mac_h, mac_l;
|
||||
int i;
|
||||
|
||||
printf("%s...\n", __func__);
|
||||
|
||||
/* Switch Analog and digital reset seq */
|
||||
mask = ATH_RESET_GE1_PHY | ATH_RESET_GE0_PHY;
|
||||
ath_reg_rmw_set(RST_RESET_ADDRESS, mask);
|
||||
|
||||
udelay(1000 * 100);
|
||||
mask = ATH_RESET_GE1_PHY ;
|
||||
ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
|
||||
|
||||
udelay(1000 * 100);
|
||||
mask = ATH_RESET_GE0_PHY ;
|
||||
ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
|
||||
udelay(100);
|
||||
|
||||
|
||||
for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) {
|
||||
|
||||
if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
|
||||
puts("malloc failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((ath_gmac_macs[i] = (ath_gmac_mac_t *) malloc(sizeof (ath_gmac_mac_t))) == NULL) {
|
||||
puts("malloc failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
memset(ath_gmac_macs[i], 0, sizeof(ath_gmac_mac_t));
|
||||
memset(dev[i], 0, sizeof(struct eth_device));
|
||||
|
||||
sprintf(dev[i]->name, "eth%d", i);
|
||||
ath_gmac_get_ethaddr(dev[i]);
|
||||
|
||||
ath_gmac_macs[i]->mac_unit = i;
|
||||
ath_gmac_macs[i]->mac_base = i ? ATH_GE1_BASE : ATH_GE0_BASE ;
|
||||
ath_gmac_macs[i]->dev = dev[i];
|
||||
|
||||
dev[i]->iobase = 0;
|
||||
dev[i]->init = ath_gmac_clean_rx;
|
||||
dev[i]->halt = ath_gmac_halt;
|
||||
dev[i]->send = ath_gmac_send;
|
||||
dev[i]->recv = ath_gmac_recv;
|
||||
dev[i]->priv = (void *)ath_gmac_macs[i];
|
||||
}
|
||||
|
||||
for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) {
|
||||
|
||||
if(!i) {
|
||||
mask = (ATH_RESET_GE0_MAC | ATH_RESET_GE1_MAC | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO);
|
||||
|
||||
|
||||
printf("%s: reset mask:%x \n", __func__, mask);
|
||||
|
||||
ath_reg_rmw_set(RST_RESET_ADDRESS, mask);
|
||||
udelay(1000 * 100);
|
||||
|
||||
mask = mask | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO;
|
||||
ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
|
||||
udelay(1000 * 100);
|
||||
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
#if defined(CONFIG_MGMT_INIT) && defined (CONFIG_ATHR_SWITCH_ONLY_MODE) || defined ATH_MDC_GPIO
|
||||
if (!i)
|
||||
athr_mgmt_init();
|
||||
|
||||
if (ath_gmac_macs[i]->mac_unit == 0)
|
||||
continue;
|
||||
#endif
|
||||
eth_register(dev[i]);
|
||||
#if(CONFIG_COMMANDS & CFG_CMD_MII)
|
||||
miiphy_register(dev[i]->name, ath_gmac_miiphy_read, ath_gmac_miiphy_write);
|
||||
#endif
|
||||
ath_gmac_mii_setup(ath_gmac_macs[i]);
|
||||
|
||||
/* if using header for register configuration, we have to */
|
||||
/* configure s26 register after frame transmission is enabled */
|
||||
|
||||
if (ath_gmac_macs[i]->mac_unit == 0) { /* WAN Phy */
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
printf("S27 reg init\n");
|
||||
athrs27_reg_init();
|
||||
mask = ATH_RESET_GE0_MAC;
|
||||
ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
printf("VIRPhy reg init \n");
|
||||
athr_vir_reg_init();
|
||||
#endif
|
||||
} else {
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
printf("S27 reg init\n");
|
||||
athrs27_reg_init_lan();
|
||||
mask = ATH_RESET_GE1_MAC;
|
||||
ath_reg_rmw_clear(RST_RESET_ADDRESS, mask);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
ath_gmac_reg_rmw_set(ath_gmac_macs[i], ATH_MAC_CFG1, ATH_MAC_CFG1_SOFT_RST
|
||||
| ATH_MAC_CFG1_RX_RST | ATH_MAC_CFG1_TX_RST);
|
||||
|
||||
|
||||
ath_gmac_hw_start(ath_gmac_macs[i]);
|
||||
ath_gmac_setup_fifos(ath_gmac_macs[i]);
|
||||
|
||||
|
||||
|
||||
udelay(100 * 1000);
|
||||
|
||||
{
|
||||
unsigned char *mac = dev[i]->enetaddr;
|
||||
|
||||
printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
|
||||
mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
|
||||
mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
|
||||
}
|
||||
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
|
||||
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
|
||||
(dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
|
||||
|
||||
ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR1, mac_l);
|
||||
ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR2, mac_h);
|
||||
|
||||
|
||||
ath_gmac_phy_setup(ath_gmac_macs[i]->mac_unit);
|
||||
printf("%s up\n",dev[i]->name);
|
||||
}
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
||||
int
|
||||
ath_gmac_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
|
||||
{
|
||||
ath_gmac_mac_t *mac = ath_gmac_name2mac(devname);
|
||||
uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
|
||||
volatile int rddata;
|
||||
uint16_t ii = 0xFFFF;
|
||||
|
||||
|
||||
/*
|
||||
* Check for previous transactions are complete. Added to avoid
|
||||
* race condition while running at higher frequencies.
|
||||
*/
|
||||
do
|
||||
{
|
||||
udelay(5);
|
||||
rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
|
||||
}while(rddata && --ii);
|
||||
|
||||
if (ii == 0)
|
||||
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
|
||||
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0);
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr);
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
|
||||
|
||||
do
|
||||
{
|
||||
udelay(5);
|
||||
rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
|
||||
}while(rddata && --ii);
|
||||
|
||||
if(ii==0)
|
||||
printf("Error!!! Leave ath_gmac_miiphy_read without polling correct status!\n");
|
||||
|
||||
val = ath_gmac_reg_rd(mac, ATH_MII_MGMT_STATUS);
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0);
|
||||
|
||||
if (data != NULL)
|
||||
*data = val;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
int
|
||||
ath_gmac_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data)
|
||||
{
|
||||
ath_gmac_mac_t *mac = ath_gmac_name2mac(devname);
|
||||
uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
|
||||
volatile int rddata;
|
||||
uint16_t ii = 0xFFFF;
|
||||
|
||||
|
||||
/*
|
||||
* Check for previous transactions are complete. Added to avoid
|
||||
* race condition while running at higher frequencies.
|
||||
*/
|
||||
do {
|
||||
udelay(5);
|
||||
rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
|
||||
} while (rddata && --ii);
|
||||
|
||||
if (ii == 0)
|
||||
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
|
||||
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr);
|
||||
ath_gmac_reg_wr(mac, ATH_MII_MGMT_CTRL, data);
|
||||
|
||||
do {
|
||||
rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1;
|
||||
} while (rddata && --ii);
|
||||
|
||||
if (ii == 0)
|
||||
printf("Error!!! Leave ath_gmac_miiphy_write without polling correct status!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
|
||||
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
ath_gmac_enet_initialize(bis);
|
||||
return 0;
|
||||
}
|
||||
|
||||
363
board/qca/mips32/qca953x/qca-eth-953x.h
Normal file
363
board/qca/mips32/qca953x/qca-eth-953x.h
Normal file
|
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __QCA_ETH_953X_H
|
||||
#define __QCA_ETH_953X_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifdef ATH_RGMII_CAL
|
||||
#define rgmii_cal_alg() rgmii_calib(mac);
|
||||
#else
|
||||
#define rgmii_cal_alg()
|
||||
#endif
|
||||
|
||||
/*
|
||||
* h/w descriptor
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t pkt_start_addr,
|
||||
is_empty : 1,
|
||||
res1 : 10,
|
||||
ftpp_override : 5,
|
||||
res2 : 4,
|
||||
pkt_size : 12,
|
||||
next_desc;
|
||||
} ath_gmac_desc_t;
|
||||
|
||||
#define NO_OF_TX_FIFOS 8
|
||||
#define NO_OF_RX_FIFOS 8
|
||||
|
||||
typedef struct {
|
||||
ath_gmac_desc_t *fifo_tx[NO_OF_TX_FIFOS],
|
||||
*fifo_rx[NO_OF_RX_FIFOS];
|
||||
struct eth_device *dev;
|
||||
uint32_t next_tx,
|
||||
next_rx,
|
||||
link,
|
||||
duplex,
|
||||
speed,
|
||||
mac_unit,
|
||||
mac_base;
|
||||
} ath_gmac_mac_t;
|
||||
|
||||
#define ath_gmac_reg_wr(_mac, _x, _y) ath_reg_wr(((_x) + _mac->mac_base), (_y))
|
||||
#define ath_gmac_reg_rd(_mac, _x) ath_reg_rd(((_x) + _mac->mac_base))
|
||||
|
||||
#define ath_gmac_reg_rmw_set(_mac, _x, _y) \
|
||||
ath_reg_rmw_set(((_x) + _mac->mac_base ), (_y))
|
||||
#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \
|
||||
ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y))
|
||||
|
||||
#ifdef COMPRESSED_UBOOT
|
||||
#define _1000BASET 1000
|
||||
#define _100BASET 100
|
||||
#define _10BASET 10
|
||||
#endif /* #ifdef COMPRESSED_UBOOT */
|
||||
|
||||
/*
|
||||
* spd is _1000BASET, _100BASET etc. defined in include/miiphy.h
|
||||
*/
|
||||
#define mii_reg(_mac) (ATH_MII0_CTRL + ((_mac)->mac_unit * 4))
|
||||
#define mii_if(_mac) (((_mac)->mac_unit == 0) ? mii0_if : mii1_if)
|
||||
|
||||
#define ath_gmac_set_mii_ctrl_speed(_mac, _spd) do { \
|
||||
ath_reg_rmw_clear(mii_reg(_mac), (3 << 4)); \
|
||||
ath_reg_rmw_set(mii_reg(_mac), ((_spd) << 4)); \
|
||||
} while (0)
|
||||
|
||||
#if defined (CFG_MII0_GMII)
|
||||
# define ath_gmac_get_mii_if() 0
|
||||
#elif defined (CFG_MII0_MII)
|
||||
# define ath_gmac_get_mii_if() 0
|
||||
#elif defined (CFG_MII0_RGMII)
|
||||
# define ath_gmac_get_mii_if() 0
|
||||
#elif defined (CFG_MII0_RMII)
|
||||
# define ath_gmac_get_mii_if() 0
|
||||
#endif
|
||||
|
||||
#define MAX_WAIT 1000
|
||||
|
||||
/*
|
||||
* Config/Mac Register definitions
|
||||
*/
|
||||
#define ATH_MAC_CFG1 0x00
|
||||
#define ATH_MAC_CFG2 0x04
|
||||
#define ATH_MAC_IFCTL 0x38
|
||||
|
||||
/*
|
||||
* fifo control registers
|
||||
*/
|
||||
#define ATH_MAC_FIFO_CFG_0 0x48
|
||||
#define ATH_MAC_FIFO_CFG_1 0x4c
|
||||
#define ATH_MAC_FIFO_CFG_2 0x50
|
||||
#define ATH_MAC_FIFO_CFG_3 0x54
|
||||
#define ATH_MAC_FIFO_CFG_4 0x58
|
||||
|
||||
#define ATH_MAC_FIFO_CFG_5 0x5c
|
||||
#define ATH_BYTE_PER_CLK_EN (1 << 19)
|
||||
|
||||
#define ATH_MAC_FIFO_RAM_0 0x60
|
||||
#define ATH_MAC_FIFO_RAM_1 0x64
|
||||
#define ATH_MAC_FIFO_RAM_2 0x68
|
||||
#define ATH_MAC_FIFO_RAM_3 0x6c
|
||||
#define ATH_MAC_FIFO_RAM_4 0x70
|
||||
#define ATH_MAC_FIFO_RAM_5 0x74
|
||||
#define ATH_MAC_FIFO_RAM_6 0x78
|
||||
#define ATH_MAC_FIFO_RAM_7 0x7c
|
||||
|
||||
/*
|
||||
* fields
|
||||
*/
|
||||
#define ATH_MAC_CFG1_SOFT_RST (1 << 31)
|
||||
#define ATH_MAC_CFG1_RX_RST (1 << 19)
|
||||
#define ATH_MAC_CFG1_TX_RST (1 << 18)
|
||||
#define ATH_MAC_CFG1_LOOPBACK (1 << 8)
|
||||
#define ATH_MAC_CFG1_RX_EN (1 << 2)
|
||||
#define ATH_MAC_CFG1_TX_EN (1 << 0)
|
||||
|
||||
#define ATH_MAC_CFG2_FDX (1 << 0)
|
||||
#define ATH_MAC_CFG2_PAD_CRC_EN (1 << 2)
|
||||
#define ATH_MAC_CFG2_LEN_CHECK (1 << 4)
|
||||
#define ATH_MAC_CFG2_HUGE_FRAME_EN (1 << 5)
|
||||
#define ATH_MAC_CFG2_IF_1000 (1 << 9)
|
||||
#define ATH_MAC_CFG2_IF_10_100 (1 << 8)
|
||||
|
||||
#define ATH_MAC_IFCTL_SPEED (1 << 16)
|
||||
|
||||
/*
|
||||
* DMA (tx/rx) register defines
|
||||
*/
|
||||
#define ATH_DMA_TX_CTRL 0x180
|
||||
#define ATH_DMA_TX_DESC 0x184
|
||||
#define ATH_DMA_TX_STATUS 0x188
|
||||
#define ATH_DMA_RX_CTRL 0x18c
|
||||
#define ATH_DMA_RX_DESC 0x190
|
||||
#define ATH_DMA_RX_STATUS 0x194
|
||||
#define ATH_DMA_INTR_MASK 0x198
|
||||
#define ATH_DMA_INTR 0x19c
|
||||
|
||||
/*
|
||||
* tx/rx ctrl and status bits
|
||||
*/
|
||||
#define ATH_TXE (1 << 0)
|
||||
#define ATH_TX_STATUS_PKTCNT_SHIFT 16
|
||||
#define ATH_TX_STATUS_PKT_SENT 0x1
|
||||
#define ATH_TX_STATUS_URN 0x2
|
||||
#define ATH_TX_STATUS_BUS_ERROR 0x8
|
||||
|
||||
#define ATH_RXE (1 << 0)
|
||||
|
||||
#define ATH_RX_STATUS_PKTCNT_MASK 0xff0000
|
||||
#define ATH_RX_STATUS_PKT_RCVD (1 << 0)
|
||||
#define ATH_RX_STATUS_OVF (1 << 2)
|
||||
#define ATH_RX_STATUS_BUS_ERROR (1 << 3)
|
||||
|
||||
/*
|
||||
* Int and int mask
|
||||
*/
|
||||
#define ATH_INTR_TX (1 << 0)
|
||||
#define ATH_INTR_TX_URN (1 << 1)
|
||||
#define ATH_INTR_TX_BUS_ERROR (1 << 3)
|
||||
#define ATH_INTR_RX (1 << 4)
|
||||
#define ATH_INTR_RX_OVF (1 << 6)
|
||||
#define ATH_INTR_RX_BUS_ERROR (1 << 7)
|
||||
|
||||
/*
|
||||
* MII registers
|
||||
*/
|
||||
#define ATH_MAC_MII_MGMT_CFG 0x20
|
||||
#define ATH_MGMT_CFG_CLK_DIV_20 0x07
|
||||
|
||||
#define ATH_MII_MGMT_CMD 0x24
|
||||
#define ATH_MGMT_CMD_READ 0x1
|
||||
|
||||
#define ATH_MII_MGMT_ADDRESS 0x28
|
||||
#define ATH_ADDR_SHIFT 8
|
||||
|
||||
#define ATH_MII_MGMT_CTRL 0x2c
|
||||
#define ATH_MII_MGMT_STATUS 0x30
|
||||
|
||||
#define ATH_MII_MGMT_IND 0x34
|
||||
#define ATH_MGMT_IND_BUSY (1 << 0)
|
||||
#define ATH_MGMT_IND_INVALID (1 << 2)
|
||||
|
||||
#define ATH_GE_MAC_ADDR1 0x40
|
||||
#define ATH_GE_MAC_ADDR2 0x44
|
||||
|
||||
/*
|
||||
* Ethernet config registers
|
||||
*/
|
||||
#define ATH_ETH_CFG 0x18070000
|
||||
#define ATH_ETH_CFG_RGMII_GE0 (1<<0)
|
||||
#define ATH_ETH_CFG_MII_GE0 (1<<1)
|
||||
#define ATH_ETH_CFG_GMII_GE0 (1<<2)
|
||||
#define ATH_ETH_CFG_RMII_GE0 (1<<10)
|
||||
#define ATH_ETH_CFG_RMII_HISPD_GE0 (1<<11)
|
||||
#define ATH_ETH_CFG_RMII_MASTER_MODE (1<<12)
|
||||
#define ATH_ETH_CFG_MII_GE0_MASTER (1<<3)
|
||||
#define ATH_ETH_CFG_MII_GE0_SLAVE (1<<4)
|
||||
#define ATH_ETH_CFG_GE0_ERR_EN (1<<5)
|
||||
#define ATH_ETH_CFG_SW_ONLY_MODE (1<<6)
|
||||
#define ATH_ETH_CFG_SW_PHY_SWAP (1<<7)
|
||||
#define ATH_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8)
|
||||
#define ATH_ETH_CFG_RXD_DELAY (1 << 14)
|
||||
#define ATH_ETH_CFG_RDV_DELAY (1 << 16)
|
||||
#define ATH_ETH_SWITCH_CLK_SPARE 0x18050024
|
||||
|
||||
#define ETH_CFG_ETH_SPARE_MSB 31
|
||||
#define ETH_CFG_ETH_SPARE_LSB 22
|
||||
#define ETH_CFG_ETH_SPARE_MASK 0xffc00000
|
||||
#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)
|
||||
#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)
|
||||
#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_MSB 21
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_LSB 20
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_MASK 0x00300000
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB)
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK)
|
||||
#define ETH_CFG_ETH_TXEN_DELAY_RESET 0x0 // 0
|
||||
#define ETH_CFG_ETH_TXD_DELAY_MSB 19
|
||||
#define ETH_CFG_ETH_TXD_DELAY_LSB 18
|
||||
#define ETH_CFG_ETH_TXD_DELAY_MASK 0x000c0000
|
||||
#define ETH_CFG_ETH_TXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB)
|
||||
#define ETH_CFG_ETH_TXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK)
|
||||
#define ETH_CFG_ETH_TXD_DELAY_RESET 0x0 // 0
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_MSB 17
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_LSB 16
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_MASK 0x00030000
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB)
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK)
|
||||
#define ETH_CFG_ETH_RXDV_DELAY_RESET 0x0 // 0
|
||||
#define ETH_CFG_ETH_RXD_DELAY_MSB 15
|
||||
#define ETH_CFG_ETH_RXD_DELAY_LSB 14
|
||||
#define ETH_CFG_ETH_RXD_DELAY_MASK 0x0000c000
|
||||
#define ETH_CFG_ETH_RXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB)
|
||||
#define ETH_CFG_ETH_RXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK)
|
||||
#define ETH_CFG_ETH_RXD_DELAY_RESET 0x0 // 0
|
||||
#define ETH_CFG_RMII_GE0_MASTER_MSB 12
|
||||
#define ETH_CFG_RMII_GE0_MASTER_LSB 12
|
||||
#define ETH_CFG_RMII_GE0_MASTER_MASK 0x00001000
|
||||
#define ETH_CFG_RMII_GE0_MASTER_GET(x) (((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB)
|
||||
#define ETH_CFG_RMII_GE0_MASTER_SET(x) (((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK)
|
||||
#define ETH_CFG_RMII_GE0_MASTER_RESET 0x1 // 1
|
||||
#define ETH_CFG_MII_CNTL_SPEED_MSB 11
|
||||
#define ETH_CFG_MII_CNTL_SPEED_LSB 11
|
||||
#define ETH_CFG_MII_CNTL_SPEED_MASK 0x00000800
|
||||
#define ETH_CFG_MII_CNTL_SPEED_GET(x) (((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB)
|
||||
#define ETH_CFG_MII_CNTL_SPEED_SET(x) (((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK)
|
||||
#define ETH_CFG_MII_CNTL_SPEED_RESET 0x0 // 0
|
||||
#define ETH_CFG_RMII_GE0_MSB 10
|
||||
#define ETH_CFG_RMII_GE0_LSB 10
|
||||
#define ETH_CFG_RMII_GE0_MASK 0x00000400
|
||||
#define ETH_CFG_RMII_GE0_GET(x) (((x) & ETH_CFG_RMII_GE0_MASK) >> ETH_CFG_RMII_GE0_LSB)
|
||||
#define ETH_CFG_RMII_GE0_SET(x) (((x) << ETH_CFG_RMII_GE0_LSB) & ETH_CFG_RMII_GE0_MASK)
|
||||
#define ETH_CFG_RMII_GE0_RESET 0x0 // 0
|
||||
#define ETH_CFG_GE0_SGMII_MSB 6
|
||||
#define ETH_CFG_GE0_SGMII_LSB 6
|
||||
#define ETH_CFG_GE0_SGMII_MASK 0x00000040
|
||||
#define ETH_CFG_GE0_SGMII_GET(x) (((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB)
|
||||
#define ETH_CFG_GE0_SGMII_SET(x) (((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK)
|
||||
#define ETH_CFG_GE0_SGMII_RESET 0x0 // 0
|
||||
#define ETH_CFG_GE0_ERR_EN_MSB 5
|
||||
#define ETH_CFG_GE0_ERR_EN_LSB 5
|
||||
#define ETH_CFG_GE0_ERR_EN_MASK 0x00000020
|
||||
#define ETH_CFG_GE0_ERR_EN_GET(x) (((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB)
|
||||
#define ETH_CFG_GE0_ERR_EN_SET(x) (((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK)
|
||||
#define ETH_CFG_GE0_ERR_EN_RESET 0x0 // 0
|
||||
#define ETH_CFG_MII_GE0_SLAVE_MSB 4
|
||||
#define ETH_CFG_MII_GE0_SLAVE_LSB 4
|
||||
#define ETH_CFG_MII_GE0_SLAVE_MASK 0x00000010
|
||||
#define ETH_CFG_MII_GE0_SLAVE_GET(x) (((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB)
|
||||
#define ETH_CFG_MII_GE0_SLAVE_SET(x) (((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK)
|
||||
#define ETH_CFG_MII_GE0_SLAVE_RESET 0x0 // 0
|
||||
#define ETH_CFG_MII_GE0_MASTER_MSB 3
|
||||
#define ETH_CFG_MII_GE0_MASTER_LSB 3
|
||||
#define ETH_CFG_MII_GE0_MASTER_MASK 0x00000008
|
||||
#define ETH_CFG_MII_GE0_MASTER_GET(x) (((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB)
|
||||
#define ETH_CFG_MII_GE0_MASTER_SET(x) (((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK)
|
||||
#define ETH_CFG_MII_GE0_MASTER_RESET 0x0 // 0
|
||||
#define ETH_CFG_GMII_GE0_MSB 2
|
||||
#define ETH_CFG_GMII_GE0_LSB 2
|
||||
#define ETH_CFG_GMII_GE0_MASK 0x00000004
|
||||
#define ETH_CFG_GMII_GE0_GET(x) (((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB)
|
||||
#define ETH_CFG_GMII_GE0_SET(x) (((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK)
|
||||
#define ETH_CFG_GMII_GE0_RESET 0x0 // 0
|
||||
#define ETH_CFG_MII_GE0_MSB 1
|
||||
#define ETH_CFG_MII_GE0_LSB 1
|
||||
#define ETH_CFG_MII_GE0_MASK 0x00000002
|
||||
#define ETH_CFG_MII_GE0_GET(x) (((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB)
|
||||
#define ETH_CFG_MII_GE0_SET(x) (((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK)
|
||||
#define ETH_CFG_MII_GE0_RESET 0x0 // 0
|
||||
#define ETH_CFG_RGMII_GE0_MSB 0
|
||||
#define ETH_CFG_RGMII_GE0_LSB 0
|
||||
#define ETH_CFG_RGMII_GE0_MASK 0x00000001
|
||||
#define ETH_CFG_RGMII_GE0_GET(x) (((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB)
|
||||
#define ETH_CFG_RGMII_GE0_SET(x) (((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK)
|
||||
#define ETH_CFG_RGMII_GE0_RESET 0x0 // 0
|
||||
#define ETH_CFG_ADDRESS 0x18070000
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ownership of descriptors between DMA and cpu
|
||||
*/
|
||||
#define ath_gmac_rx_owned_by_dma(_ds) ((_ds)->is_empty == 1)
|
||||
#define ath_gmac_rx_give_to_dma(_ds) ((_ds)->is_empty = 1)
|
||||
#define ath_gmac_tx_owned_by_dma(_ds) ((_ds)->is_empty == 0)
|
||||
#define ath_gmac_tx_give_to_dma(_ds) ((_ds)->is_empty = 0)
|
||||
#define ath_gmac_tx_own(_ds) ((_ds)->is_empty = 1)
|
||||
|
||||
/*
|
||||
* link settings
|
||||
*/
|
||||
#define ath_gmac_set_mac_duplex(_mac, _fdx) do { \
|
||||
if ((_fdx)) { \
|
||||
ath_gmac_reg_rmw_set(_mac, \
|
||||
ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\
|
||||
} else { \
|
||||
ath_gmac_reg_rmw_clear(_mac, \
|
||||
ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ath_gmac_set_mac_if(_mac, _isXGMII) do { \
|
||||
ath_gmac_reg_rmw_clear(_mac, ATH_MAC_CFG2, \
|
||||
ATH_MAC_CFG2_IF_1000 | \
|
||||
ATH_MAC_CFG2_IF_10_100); \
|
||||
if ((_isXGMII)) { \
|
||||
ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \
|
||||
ATH_MAC_CFG2_IF_1000); \
|
||||
ath_gmac_reg_rmw_set(_mac, ATH_MAC_FIFO_CFG_5, \
|
||||
ATH_BYTE_PER_CLK_EN); \
|
||||
} else { \
|
||||
ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \
|
||||
ATH_MAC_CFG2_IF_10_100); \
|
||||
ath_gmac_reg_rmw_clear(_mac, ATH_MAC_FIFO_CFG_5,\
|
||||
ATH_BYTE_PER_CLK_EN); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ath_gmac_set_mac_speed(_mac, _is100) do { \
|
||||
if ((_is100)) { \
|
||||
ath_gmac_reg_rmw_set(_mac, ATH_MAC_IFCTL, \
|
||||
ATH_MAC_IFCTL_SPEED); \
|
||||
} else { \
|
||||
ath_gmac_reg_rmw_clear(_mac, ATH_MAC_IFCTL, \
|
||||
ATH_MAC_IFCTL_SPEED); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#endif /* __QCA_ETH_953X_H */
|
||||
87
board/qca/mips32/qca953x/qca-eth-953x_phy.h
Normal file
87
board/qca/mips32/qca953x/qca-eth-953x_phy.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _QCA_ETH_953x_PHY_H
|
||||
#define _QCA_ETH_953x_PHY_H
|
||||
#include <miiphy.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_ATHR_8033_PHY
|
||||
extern int athrs_ar8033_reg_init(void *arg);
|
||||
extern int athrs_ar8033_phy_setup(void *arg);
|
||||
extern int athrs_ar8033_phy_is_fdx(int ethUnit);
|
||||
extern int athrs_ar8033_phy_is_link_alive(int phyUnit);
|
||||
extern int athrs_ar8033_phy_is_up(int ethUnit);
|
||||
extern int athrs_ar8033_phy_speed(int ethUnit,int phyUnit);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
extern int athrs27_phy_setup(int ethUnit);
|
||||
extern int athrs27_phy_is_up(int ethUnit);
|
||||
extern int athrs27_phy_is_fdx(int ethUnit);
|
||||
extern int athrs27_phy_speed(int ethUnit);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ATHRS17_PHY
|
||||
extern int athrs17_phy_setup(int ethUnit);
|
||||
extern int athrs17_phy_is_up(int ethUnit);
|
||||
extern int athrs17_phy_is_fdx(int ethUnit);
|
||||
extern int athrs17_phy_speed(int ethUnit);
|
||||
#endif
|
||||
|
||||
static inline void ath_gmac_phy_setup(int unit)
|
||||
{
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
athrs27_phy_setup(unit);
|
||||
#endif
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
athr_vir_phy_setup(unit);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ath_gmac_phy_link(int unit, int *link)
|
||||
{
|
||||
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
*link = athrs27_phy_is_up(unit);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
*link = athr_vir_phy_is_up(unit);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ath_gmac_phy_duplex(int unit, int *duplex)
|
||||
{
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
*duplex = athrs27_phy_is_fdx(unit);
|
||||
#endif
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
*duplex = athr_vir_phy_is_fdx(unit);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ath_gmac_phy_speed(int unit, int *speed)
|
||||
{
|
||||
#ifdef CFG_ATHRS27_PHY
|
||||
*speed = athrs27_phy_speed(unit);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIR_PHY
|
||||
*speed = athr_vir_phy_speed(unit);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* _QCA_ETH_953x_PHY_H */
|
||||
196
board/qca/mips32/qca953x/tap-953x.S
Normal file
196
board/qca/mips32/qca953x/tap-953x.S
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <atheros.h>
|
||||
|
||||
.globl ath_ddr_tap_cal
|
||||
.type ath_ddr_tap_cal, @function
|
||||
.text
|
||||
.align 4
|
||||
ath_ddr_tap_cal:
|
||||
li a0, 0xbd001f00
|
||||
sw zero, 0x0(a0) // Place where the tap values are saved and used for SWEEP
|
||||
sw zero, 0x4(a0) // Place where the number of passing taps are saved.
|
||||
sw zero, 0x14(a0) // Place where the last pass tap value is stored
|
||||
li a1, 0xaa55aa55 // Indicates that the First pass tap value is not found
|
||||
sw a1, 0x10(a0) // Place where the First pass tap value is stored
|
||||
nop
|
||||
|
||||
li a0, 0xb8060000 // RESET_BASE_ADDRESS
|
||||
lw a1, 0x1c(a0) // Reading the RST_RESET_ADDRESS
|
||||
li a2, 0x08000000 // Setting the RST_RESET_RTC_RESET
|
||||
or a1, a1, a2
|
||||
sw a1, 0x1c(a0)
|
||||
|
||||
li a3, 0xffffffff
|
||||
xor a2, a2, a3
|
||||
and a1, a1, a2
|
||||
sw a1, 0x1c(a0) // Taking the RTC out of RESET
|
||||
nop
|
||||
|
||||
li a0, 0xb8107000 // RTC_BASE_ADDRESS
|
||||
li a1, 0x1
|
||||
sw a1, 0x0040(a0) // RTC_SYNC_RESET_ADDRESS
|
||||
|
||||
li a2, 0x2
|
||||
|
||||
_poll_for_RTC_ON:
|
||||
lw a1, 0x0044(a0) // RTC_SYNC_STATUS_ADDRESS
|
||||
and a1, a2, a1
|
||||
bne a1, a2, _poll_for_RTC_ON
|
||||
|
||||
|
||||
_CHANGE_TAPS:
|
||||
|
||||
li t0, 0xbd001f00 // Read the current value of the TAP for programming
|
||||
lw t1, 0x0(t0)
|
||||
li t2, 0x00000000
|
||||
or t3, t1, t2
|
||||
|
||||
|
||||
li t0, 0xb8000000 // DDR_BASE_ADDRESS
|
||||
|
||||
sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS
|
||||
sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS
|
||||
sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS
|
||||
sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS
|
||||
|
||||
li t1, 0x00000010 // Running the test 8 times
|
||||
sw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS
|
||||
|
||||
li t1, 0xfa5de83f // 4 Row Address Bits, 4 Column Address Bits, 2 BA bits
|
||||
sw t1, 0x002c(t0) // PERF_MASK_ADDR_0_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0070(t0) // PERF_COMP_AHB_GE0_1_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0040(t0) // PERF_COMP_AHB_GE1_0_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0078(t0) // PERF_COMP_AHB_GE1_1_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0034(t0) // PERF_MASK_AHB_GE0_0_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x006c(t0) // PERF_MASK_AHB_GE0_1_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x003c(t0) // PERF_MASK_AHB_GE1_0_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0074(t0) // PERF_MASK_AHB_GE1_1_ADDRESS
|
||||
|
||||
li t1, 0x0000ffff
|
||||
sw t1, 0x0038(t0) // PERF_COMP_AHB_GE0_0_ADDRESS
|
||||
|
||||
li t1, 0x00000001
|
||||
sw t1, 0x011c(t0) // DDR_BIST_ADDRESS
|
||||
|
||||
li t2, 0x1
|
||||
_bist_done_poll:
|
||||
lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS
|
||||
and t1, t1, t2
|
||||
bne t1, t2, _bist_done_poll
|
||||
|
||||
lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS
|
||||
li t4, 0x000001fe
|
||||
and t2, t1, t4
|
||||
srl t2, t2, 0x1 // no. of Pass Runs
|
||||
|
||||
li t5, 0x00000000
|
||||
sw t5, 0x011c(t0) //DDR_BIST_ADDRESS - Stop the DDR BIST test
|
||||
|
||||
li t5, 0x0001fe00
|
||||
and t5, t5, t1
|
||||
bnez t5, _iterate_tap // This is a redundant compare but nevertheless - Comparing the FAILS
|
||||
|
||||
lw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS
|
||||
li t3, 0x000001fe
|
||||
and t3, t3, t1
|
||||
srl t3, t3, 0x1 // No. of runs in the config register.
|
||||
|
||||
bne t3, t2, _iterate_tap
|
||||
|
||||
pass_tap:
|
||||
li t0, 0xbd001f00
|
||||
lw t1, 0x4(t0)
|
||||
addiu t1, t1, 0x1
|
||||
sw t1, 0x4(t0)
|
||||
|
||||
li t0, 0xbd001f10
|
||||
lw t1, 0x0(t0)
|
||||
li t2, 0xaa55aa55
|
||||
beq t1, t2, _first_pass
|
||||
nop
|
||||
li t0, 0xbd001f00
|
||||
lw t1, 0x0(t0)
|
||||
li t0, 0xbd001f10
|
||||
sw t1, 0x4(t0)
|
||||
nop
|
||||
b _iterate_tap
|
||||
nop
|
||||
|
||||
_first_pass:
|
||||
li t0, 0xbd001f00
|
||||
lw t1, 0x0(t0)
|
||||
li t0, 0xbd001f10
|
||||
sw t1, 0x0(t0)
|
||||
sw t1, 0x4(t0)
|
||||
nop
|
||||
|
||||
_iterate_tap:
|
||||
|
||||
li t0, 0xbd001f00
|
||||
lw t1, 0x0(t0)
|
||||
li t2, 0x3f
|
||||
beq t1, t2, _STOP_TEST
|
||||
nop
|
||||
addiu t1, t1, 0x1
|
||||
sw t1, 0x0(t0)
|
||||
nop
|
||||
b _CHANGE_TAPS
|
||||
|
||||
_STOP_TEST:
|
||||
li t0, 0xbd001f00
|
||||
lw t1, 0x4(t0)
|
||||
bnez t1, _load_center_tap
|
||||
nop
|
||||
li t3, 0x8 // Default Tap to be used
|
||||
b _load_tap_into_reg
|
||||
|
||||
_load_center_tap:
|
||||
li t0, 0xbd001f10
|
||||
lw t1, 0x0(t0)
|
||||
lw t2, 0x4(t0)
|
||||
add t3, t1, t2
|
||||
srl t3, t3, 0x1
|
||||
li t4, 0x3f
|
||||
and t3, t3, t4
|
||||
_load_tap_into_reg:
|
||||
li t0, 0xb8000000
|
||||
sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS
|
||||
sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS
|
||||
sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS
|
||||
sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
17
configs/qca953x_defconfig
Normal file
17
configs/qca953x_defconfig
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
CONFIG_MIPS=y
|
||||
CONFIG_TARGET_QCA953X=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QCA953X"
|
||||
CONFIG_SYS_PROMPT="QCA953X# "
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
CONFIG_CMD_RUN=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_FLASH=y
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x200
|
||||
CONFIG_SYS_MALLOC_F=y
|
||||
4579
include/953x.h
Normal file
4579
include/953x.h
Normal file
File diff suppressed because it is too large
Load diff
195
include/configs/qca953x.h
Normal file
195
include/configs/qca953x.h
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
/*
|
||||
* Console I/O configuration
|
||||
*/
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200}
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 512
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "hush>"
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#ifndef FLASH_SIZE
|
||||
#define FLASH_SIZE 16
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#if (FLASH_SIZE == 32)
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define ATH_MTDPARTS_MIB0 "64k(mib0)"
|
||||
#define ATH_ROOTFS_SIZE "14528k(rootfs)"
|
||||
#elif (FLASH_SIZE == 16)
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
#define ATH_MTDPARTS_MIB0 "64k(mib0)"
|
||||
#define ATH_ROOTFS_SIZE "14528k(rootfs)"
|
||||
#elif (FLASH_SIZE == 8)
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define ATH_MTDPARTS_MIB0 "64k(mib0)"
|
||||
#define ATH_ROOTFS_SIZE "6336k(rootfs)"
|
||||
#elif (FLASH_SIZE == 1/2)
|
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
|
||||
#else
|
||||
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
|
||||
#define ATH_MTDPARTS_MIB0 "64k(mib0)"
|
||||
#define ATH_ROOTFS_SIZE "6336k(rootfs)"
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_SECTOR_SIZE (64*1024)
|
||||
#if (FLASH_SIZE == 32)
|
||||
#define CFG_FLASH_SIZE 0x02000000 /* Total flash size */
|
||||
#elif (FLASH_SIZE == 16)
|
||||
#define CFG_FLASH_SIZE 0x01000000 /* Total flash size */
|
||||
#elif (FLASH_SIZE == 8)
|
||||
#define CFG_FLASH_SIZE 0x00800000 /* max number of sectors on one chip */
|
||||
#elif (FLASH_SIZE == 1/2)
|
||||
#define CFG_FLASH_SIZE 0x00080000 /* Total flash size */
|
||||
#else
|
||||
#define CFG_FLASH_SIZE 0x00400000 /* Total flash size */
|
||||
#endif
|
||||
|
||||
#ifndef COMPRESSED_UBOOT
|
||||
#define ENABLE_DYNAMIC_CONF 1
|
||||
#endif
|
||||
|
||||
#undef CFG_ATHRS26_PHY
|
||||
|
||||
#if (CFG_MAX_FLASH_SECT * CFG_FLASH_SECTOR_SIZE) != CFG_FLASH_SIZE
|
||||
# error "Invalid flash configuration"
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
#if defined(CONFIG_ATH_NAND_BR) && defined(COMPRESSED_UBOOT)
|
||||
#define CFG_FLASH_BASE 0xa0100000
|
||||
#else
|
||||
/* NOR Flash start address */
|
||||
#define CFG_FLASH_BASE 0x9f000000
|
||||
#endif
|
||||
|
||||
#ifdef COMPRESSED_UBOOT
|
||||
#define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
|
||||
#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_CONFIG_DATA_IN_OTP
|
||||
|
||||
/*
|
||||
* Defines to change flash size on reboot
|
||||
*/
|
||||
#ifdef ENABLE_DYNAMIC_CONF
|
||||
#define CFG_DDR_MAGIC 0xaabacada
|
||||
#define CFG_DDR_MAGIC_F (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x30)
|
||||
#define CFG_DDR_CONFIG_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 4)
|
||||
#define CFG_DDR_CONFIG2_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 8)
|
||||
#define CFG_DDR_EXT_MODE_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 12)
|
||||
#endif
|
||||
|
||||
/*
|
||||
** Parameters defining the location of the calibration/initialization
|
||||
** information for the two Merlin devices.
|
||||
** NOTE: **This will change with different flash configurations**
|
||||
*/
|
||||
|
||||
#define BOARDCAL (CFG_FLASH_BASE + CFG_FLASH_SIZE - 0x10000)
|
||||
#define WLANCAL (BOARDCAL + 0x1000)
|
||||
#define ATHEROS_PRODUCT_ID 137
|
||||
#define CAL_SECTOR (CFG_MAX_FLASH_SECT - 1)
|
||||
|
||||
/* For Merlin, both PCI, PCI-E interfaces are valid */
|
||||
#define ATH_ART_PCICFG_OFFSET 12
|
||||
|
||||
/*
|
||||
* The following for ENV settings
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_FLASH_BASE 0x9f000000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE CFG_FLASH_SECTOR_SIZE //CFG_ENV_SIZE
|
||||
#define CONFIG_ENV_ADDR 0x9f040000
|
||||
|
||||
/* Timer Specific */
|
||||
#define CONFIG_SYS_MHZ 550
|
||||
/* Since the count is incremented every other tick, divide by 2 -- CFG_HZ*/
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ ((CONFIG_SYS_MHZ * 1000000)/2)
|
||||
|
||||
|
||||
#define CFG_DDR_REFRESH_VAL 0x4138
|
||||
|
||||
/*
|
||||
* The following #defines are needed to get flash environment right
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x9f000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128*1024)
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_SYS_ICACHE_SIZE 65536
|
||||
#define CONFIG_SYS_DCACHE_SIZE 32768
|
||||
|
||||
#define CONFIG_PCI 1
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
|
||||
/*#define CONFIG_USB 1*/
|
||||
|
||||
#define CONFIG_ATH_SOC 1
|
||||
#define CONFIG_ATHEROS 1
|
||||
#define CONFIG_MACH_QCA953x 1
|
||||
#define CFG_INIT_STACK_IN_SRAM 1
|
||||
#define CONFIG_AP147 1
|
||||
#define __CONFIG_BOARD_NAME ap147
|
||||
#define CONFIG_BOARD_NAME "ap147"
|
||||
#define BUILD_VERSION "g36c341f-dirty-1"
|
||||
#define CFG_PLL_FREQ CFG_PLL_650_600_200
|
||||
#define CFG_ATHRS27_PHY 1
|
||||
#define CFG_ATH_GMAC_NMACS 2
|
||||
#define BOARD_NAME "AP147"
|
||||
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
#define CONFIG_SYS_TEXT_BASE 0x9f000000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x81000000
|
||||
|
||||
/*
|
||||
* Cache lock for stack
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x1000
|
||||
#define CFG_INIT_SRAM_SP_OFFSET 0xbd001800
|
||||
|
||||
/*
|
||||
* Image type
|
||||
*/
|
||||
#define CONFIG_LZMA 1
|
||||
#define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
|
||||
/*
|
||||
* ethernet environment
|
||||
*/
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
#define CONFIG_TFTP_BLOCKSIZE 512
|
||||
#define CONFIG_MII 1
|
||||
#define CFG_CMD_MII 1
|
||||
#define CONFIG_COMMANDS 1
|
||||
|
||||
Loading…
Add table
Reference in a new issue