From a3303e7b231ca0601cad9c6c6380dffa97fbbfd6 Mon Sep 17 00:00:00 2001
From: Antony Arun T <antothom@codeaurora.org>
Date: Thu, 1 Mar 2018 10:23:15 +0530
Subject: [PATCH] ipq806x: Dump CPU1 register contents as part of crash dump

Invokes TZ (via scm call) to pull Core-1 out of reset if
crash magic is set. TZ saves the register contents in the
NSS TCM, which is saved from U-Boot as CPU1_REG.BIN as part
of the crash dump saving procedure.

Change-Id: I8e1404fb354a47ae69d70d13a79f45bd4eb1c450
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
---
 arch/arm/include/asm/arch-qca-common/iomap.h |  3 ++
 arch/arm/include/asm/arch-qca-common/scm.h   |  2 +
 board/qca/arm/common/cmd_bootqca.c           | 41 ++++++++++++++++++++
 board/qca/arm/ipq806x/ipq806x.c              | 24 ++++++++++++
 4 files changed, 70 insertions(+)

diff --git a/arch/arm/include/asm/arch-qca-common/iomap.h b/arch/arm/include/asm/arch-qca-common/iomap.h
index bfd35c6f75..49be52bfb8 100644
--- a/arch/arm/include/asm/arch-qca-common/iomap.h
+++ b/arch/arm/include/asm/arch-qca-common/iomap.h
@@ -26,4 +26,7 @@
 
 #define GCNT_PSHOLD		0x004AB000
 
+#define CPU1_APCS_SAW2_VCTL	0x02099014
+#define CPU1_APCS_CPU_PWR_CTL	0x02098004
+
 #endif /* _PLATFORM_IPQ40XX_IOMAP_H_ */
diff --git a/arch/arm/include/asm/arch-qca-common/scm.h b/arch/arm/include/asm/arch-qca-common/scm.h
index e57cfaa10b..5cc670518c 100644
--- a/arch/arm/include/asm/arch-qca-common/scm.h
+++ b/arch/arm/include/asm/arch-qca-common/scm.h
@@ -28,6 +28,8 @@
 #define SCM_SVC_RD			0x12
 #define QFPROM_IS_AUTHENTICATE_CMD	0x7
 #define TZBSP_BUILD_VER_QUERY_CMD	0x4
+#define SCM_BOOT_ADDR			0x1
+#define SCM_FLAG_COLDBOOT_CPU1		0x1
 
 /* scm_v8 */
 #define SCM_VAL				0x0
diff --git a/board/qca/arm/common/cmd_bootqca.c b/board/qca/arm/common/cmd_bootqca.c
index 252b7fb7ec..15cc6918b1 100644
--- a/board/qca/arm/common/cmd_bootqca.c
+++ b/board/qca/arm/common/cmd_bootqca.c
@@ -28,6 +28,8 @@
 #include <nand.h>
 #include <spi_flash.h>
 #include <spi.h>
+#include <asm/arch-qca-common/iomap.h>
+#include <asm/io.h>
 
 #define DLOAD_MAGIC_COOKIE 0x10
 #define XMK_STR(x)#x
@@ -106,6 +108,40 @@ static int tftpdump (int is_aligned_access, uint32_t memaddr, uint32_t size, cha
 
 }
 
+__weak int scm_set_boot_addr(void)
+{
+	return -1;
+}
+
+static int krait_release_secondary(void)
+{
+	writel(0xa4, CPU1_APCS_SAW2_VCTL);
+	barrier();
+	udelay(512);
+
+	writel(0x109, CPU1_APCS_CPU_PWR_CTL);
+	writel(0x101, CPU1_APCS_CPU_PWR_CTL);
+	barrier();
+	udelay(1);
+
+	writel(0x121, CPU1_APCS_CPU_PWR_CTL);
+	barrier();
+	udelay(2);
+
+	writel(0x120, CPU1_APCS_CPU_PWR_CTL);
+	barrier();
+	udelay(2);
+
+	writel(0x100, CPU1_APCS_CPU_PWR_CTL);
+	barrier();
+	udelay(100);
+
+	writel(0x180, CPU1_APCS_CPU_PWR_CTL);
+	barrier();
+
+	return 0;
+}
+
 static int do_dumpqca_data(void)
 {
 	char *serverip = NULL;
@@ -134,6 +170,11 @@ static int do_dumpqca_data(void)
 		dump_entries = dump_entries_s;
 	}
 
+	if (scm_set_boot_addr() == 0) {
+		/* Pull Core-1 out of reset, iff scm call succeeds */
+		krait_release_secondary();
+	}
+
 	for (indx = 0; indx < dump_entries; indx++) {
 		printf("\nProcessing %s:", dumpinfo[indx].name);
 
diff --git a/board/qca/arm/ipq806x/ipq806x.c b/board/qca/arm/ipq806x/ipq806x.c
index c96a7557d9..f2f2211416 100644
--- a/board/qca/arm/ipq806x/ipq806x.c
+++ b/board/qca/arm/ipq806x/ipq806x.c
@@ -927,6 +927,30 @@ int ipq_get_tz_version(char *version_name, int buf_size)
 	return 0;
 }
 
+void forever(void) { while (1); }
+/*
+ * Set the cold/warm boot address for one of the CPU cores.
+ */
+int scm_set_boot_addr(void)
+{
+	int ret;
+	struct {
+		unsigned int flags;
+		unsigned long addr;
+	} cmd;
+
+	cmd.addr = (unsigned long)forever;
+	cmd.flags = SCM_FLAG_COLDBOOT_CPU1;
+
+	ret = scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
+				&cmd, sizeof(cmd), NULL, 0);
+	if (ret) {
+		printf("--- %s: scm_call failed ret = %d\n", __func__, ret);
+	}
+
+	return ret;
+}
+
 void clear_l2cache_err(void)
 {
         unsigned int val;