From f98c229172fb3703a18ddbab0b451359cb67a4d9 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 17 May 2018 17:40:30 +0530 Subject: [PATCH 1/3] Revert "Revert "qca: Disabling dcache before scheduling secondary cores"" This reverts commit 4bc21f97960f016dc64f735dcbf4f2996d9c88e9. --- board/qca/arm/common/cmd_runmulticore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/qca/arm/common/cmd_runmulticore.c b/board/qca/arm/common/cmd_runmulticore.c index ef19ea4217..95bd090824 100644 --- a/board/qca/arm/common/cmd_runmulticore.c +++ b/board/qca/arm/common/cmd_runmulticore.c @@ -69,6 +69,8 @@ int do_runmulticore(cmd_tbl_t *cmdtp, if ((argc <= 1) || (argc > 4)) return CMD_RET_USAGE; + dcache_disable(); + /* Setting up stack for secondary cores */ memset(core, 0, sizeof(core)); @@ -167,6 +169,8 @@ int do_runmulticore(cmd_tbl_t *cmdtp, free(core[i - 1].stack_top_ptr); } + dcache_enable(); + return CMD_RET_SUCCESS; } From 4f3e17a9b35a34f523b2be7f6a7f8a76883b83c5 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 17 May 2018 17:40:56 +0530 Subject: [PATCH 2/3] Revert "Revert "runmulticore: Added cache flush before enabling"" This reverts commit 58a2a17f7b07754caf816674140d38892127ab72. --- board/qca/arm/common/cmd_runmulticore.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/qca/arm/common/cmd_runmulticore.c b/board/qca/arm/common/cmd_runmulticore.c index 95bd090824..bb9abe3147 100644 --- a/board/qca/arm/common/cmd_runmulticore.c +++ b/board/qca/arm/common/cmd_runmulticore.c @@ -169,6 +169,7 @@ int do_runmulticore(cmd_tbl_t *cmdtp, free(core[i - 1].stack_top_ptr); } + invalidate_dcache_all(); dcache_enable(); return CMD_RET_SUCCESS; From 98fb19b4167b731e730e703db1573337be207a76 Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Thu, 17 May 2018 17:59:51 +0530 Subject: [PATCH 3/3] Revert "Revert "qca: cache: Enabled dcache on board initialization"" This reverts commit 37a47837a46a61c0ff9f90a34f953a6b4c728aae. Change-Id: I6be9a84f1c00d8576bb2a288caa8513697a17062 --- board/qca/arm/ipq807x/ipq807x.c | 11 +++++++++++ include/configs/ipq807x.h | 1 + 2 files changed, 12 insertions(+) diff --git a/board/qca/arm/ipq807x/ipq807x.c b/board/qca/arm/ipq807x/ipq807x.c index f7e9b76af0..a6e669155c 100644 --- a/board/qca/arm/ipq807x/ipq807x.c +++ b/board/qca/arm/ipq807x/ipq807x.c @@ -1003,12 +1003,23 @@ void set_flash_secondary_type(qca_smem_flash_info_t *smem) void enable_caches(void) { + qca_smem_flash_info_t *sfi = &qca_smem_flash_info; + + smem_get_boot_flash(&sfi->flash_type, + &sfi->flash_index, + &sfi->flash_chip_select, + &sfi->flash_block_size, + &sfi->flash_density); icache_enable(); + /*Skips dcache_enable during JTAG recovery */ + if (sfi->flash_type) + dcache_enable(); } void disable_caches(void) { icache_disable(); + dcache_disable(); } /* diff --git a/include/configs/ipq807x.h b/include/configs/ipq807x.h index dcb10d77af..ed6d3e5c02 100644 --- a/include/configs/ipq807x.h +++ b/include/configs/ipq807x.h @@ -328,6 +328,7 @@ extern loff_t board_env_size; * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE /* Enabling this flag will report any L2 errors. * By default we are disabling it */