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ipq5018: spi-nor: Add offset 0x0 erase support for S25FL128S_64K

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Note : This S25FL128S_64K chip has Hybrid sector's
First 64Kb (4Kb * 8 + 32Kb) and rest all 64Kb sectors

Change-Id: Ibac9bd9dbd7b5a4eb1c31427b4d315fc5353ec62
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This commit is contained in:
Vandhiadevan Karunamoorthy 2019-11-01 11:03:00 +05:30
parent 4cd1329204
commit a13842f5cf
3 changed files with 26 additions and 1 deletions
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23
drivers/mtd/spi/spi_flash.c
View file

@ -24,6 +24,11 @@
#define CMD_S25FSXX_BE 0x60
#endif
#if defined CONFIG_SPI_FLASH_CYPRESS
#define CYPRESS_JEDEC_ID 0x012018
#define CYPRESS_EXT_JEDEC_ID 0x4d01
#endif
DECLARE_GLOBAL_DATA_PTR;
static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd)
@ -380,6 +385,22 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
while (len) {
erase_addr = offset;
#ifdef CONFIG_SPI_FLASH_CYPRESS
if ((flash->jedec == CYPRESS_JEDEC_ID) &&
(flash->ext_jedec == CYPRESS_EXT_JEDEC_ID)){
if (offset <= (SZ_32K - SZ_4K)){
cmd[0] = CMD_ERASE_4K;
erase_size = SZ_4K;
}else {
cmd[0] = CMD_ERASE_64K;
if (offset < SZ_64K){
erase_size = SZ_32K;
}else {
erase_size = SZ_64K;
}
}
}
#endif
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual(flash, &erase_addr);
@ -1120,6 +1141,8 @@ try_with_dummy_byte:
/* Assign spi data */
flash->name = params->name;
flash->jedec = params->jedec;
flash->ext_jedec = params->ext_jedec;
flash->memory_map = spi->memory_map;
flash->dual_flash = flash->spi->option;

2
include/configs/ipq5018.h
View file

@ -19,7 +19,7 @@
#endif
#define CONFIG_IPQ5018
#define IPQ5018_EMULATION
#define CONFIG_SPI_FLASH_CYPRESS
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_CMD_CACHE

2
include/spi_flash.h
View file

@ -73,6 +73,8 @@ struct spi_flash {
struct udevice *dev;
#endif
const char *name;
u32 jedec;
u16 ext_jedec;
u8 dual_flash;
u8 shift;
u8 addr_width;