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ipq50xx: net: Update UNIPHY_MISC register address

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This changes enable proper uniphy soft reset for mode setting.

Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Iebafa56ec4aecee98ba2f124d6140ee15083d317
This commit is contained in:
Vandhiadevan Karunamoorthy 2020-12-24 16:27:31 +05:30
parent 05a60f1d5a
commit a08592083b
2 changed files with 12 additions and 2 deletions
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11
drivers/net/ipq5018/ipq5018_uniphy.c
View file

@ -22,6 +22,8 @@
#include "ipq5018_uniphy.h"
#include "ipq_phy.h"
static uint32_t cur_mode;
static int ppe_uniphy_calibration(void)
{
int retries = 100, calibration_done = 0;
@ -59,6 +61,7 @@ static void ppe_gcc_uniphy_soft_reset(void)
static void ppe_uniphy_sgmii_mode_set(uint32_t mode)
{
uint32_t phy_mode = 0x70;
writel(UNIPHY_MISC2_REG_SGMII_MODE,
PPE_UNIPHY_BASE + UNIPHY_MISC2_REG_OFFSET);
@ -93,14 +96,20 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t mode)
case PORT_WRAPPER_SGMII_PLUS:
writel((UNIPHY_SG_PLUS_MODE | UNIPHY_PSGMII_MAC_MODE),
PPE_UNIPHY_BASE + PPE_UNIPHY_MODE_CONTROL);
phy_mode = 0x30;
break;
default:
printf("SGMII Config. wrongly");
break;
}
if ((cur_mode == PORT_WRAPPER_SGMII_PLUS) ||
(mode == PORT_WRAPPER_SGMII_PLUS)){
cur_mode = mode;
ppe_gcc_uniphy_soft_reset();
}
writel(phy_mode, PPE_UNIPHY_BASE + PPE_UNIPHY_ALLREG_DEC_MISC2);
writel(0x1, GCC_UNIPHY_RX_CBCR);
udelay(500);

3
drivers/net/ipq5018/ipq5018_uniphy.h
View file

@ -23,7 +23,7 @@
#define GCC_GMAC1_RX_CBCR 0x01868248
#define GCC_GMAC1_TX_CBCR 0x0186824C
#define GCC_UNIPHY0_MISC 0x01856004
#define GCC_UNIPHY0_MISC 0x01856104
#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0
#define UNIPHY_CALIBRATION_DONE 0x1
@ -33,6 +33,7 @@
#define PPE_UNIPHY_BASE 0x00098000
#define PPE_UNIPHY_MODE_CONTROL 0x46C
#define PPE_UNIPHY_ALLREG_DEC_MISC2 0x218
#define UNIPHY_XPCS_MODE (1 << 12)
#define UNIPHY_SG_PLUS_MODE (1 << 11)
#define UNIPHY_SG_MODE (1 << 10)