From 9f81944daa67f360c5c12fcdfdf13978528da751 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Thu, 21 Apr 2022 15:28:06 +0530 Subject: [PATCH] board: devsoc: enable QSPI NAND Change-Id: Ibfaea936f2e611b31f3fa0946b8fc0fac08cb1be Signed-off-by: Vandhiadevan Karunamoorthy --- arch/arm/dts/devsoc-emulation.dts | 47 +++++++++++++++++++ arch/arm/dts/devsoc-soc.dtsi | 8 ++++ arch/arm/include/asm/arch-devsoc/clk.h | 26 ++++++++++ .../include/asm/arch-qca-common/qpic_nand.h | 2 +- board/devsoc/Kconfig | 5 ++ board/qca/arm/devsoc/clock.c | 8 ++++ board/qca/arm/devsoc/devsoc.c | 27 ++++++++++- board/qca/arm/devsoc/devsoc.h | 23 +++++---- configs/devsoc_defconfig | 4 +- include/configs/devsoc.h | 46 ++++++++++++------ 10 files changed, 166 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/devsoc-emulation.dts b/arch/arm/dts/devsoc-emulation.dts index 9ec88fd85d..cd0ac1d020 100644 --- a/arch/arm/dts/devsoc-emulation.dts +++ b/arch/arm/dts/devsoc-emulation.dts @@ -23,6 +23,7 @@ aliases { console = "/serial@78AF000"; + nand = "/nand-controller@79B0000"; }; console: serial@78AF000 { @@ -50,4 +51,50 @@ timer { gpt_freq_hz = <240000>; }; + + nand: nand-controller@79B0000 { + status = "okay"; + nand_gpio { + qspi_dat3 { + gpio = <8>; + func = <2>; + pull = ; + od_en = ; + drvstr = ; + }; + qspi_dat2 { + gpio = <9>; + func = <2>; + pull = ; + od_en = ; + drvstr = ; + }; + qspi_dat1 { + gpio = <10>; + func = <2>; + pull = ; + od_en = ; + drvstr = ; + }; + qspi_dat0 { + gpio = <11>; + func = <2>; + pull = ; + od_en = ; + drvstr = ; + }; + qspi_cs_n { + gpio = <12>; + func = <2>; + od_en = ; + drvstr = ; + }; + qspi_clk { + gpio = <13>; + func = <2>; + od_en = ; + drvstr = ; + }; + }; + }; }; diff --git a/arch/arm/dts/devsoc-soc.dtsi b/arch/arm/dts/devsoc-soc.dtsi index b3a72d995f..645ebe0f72 100644 --- a/arch/arm/dts/devsoc-soc.dtsi +++ b/arch/arm/dts/devsoc-soc.dtsi @@ -72,4 +72,12 @@ }; }; }; + + nand: nand-controller@79B0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qpic-nand-v2.1.1"; + reg = <0x79B0000 0x10000>; + status = "disabled"; + }; }; diff --git a/arch/arm/include/asm/arch-devsoc/clk.h b/arch/arm/include/asm/arch-devsoc/clk.h index 7cedd7582e..33a4c89905 100644 --- a/arch/arm/include/asm/arch-devsoc/clk.h +++ b/arch/arm/include/asm/arch-devsoc/clk.h @@ -59,6 +59,32 @@ #define ROOT_EN 0x2 #define CLK_ENABLE 0x1 +/* + * Qpic SPI Nand clock + */ + +#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004 +#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008 +#define GCC_QPIC_IO_MACRO_CBCR 0x183200C +#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010 +#define GCC_QPIC_CBCR_ADDR 0x1832014 +#define GCC_QPIC_SREGR 0x1832018 +#define GCC_QPIC_SLEEP_CBCR 0x183201C + +#define IO_MACRO_CLK_320_MHZ 320000000 +#define IO_MACRO_CLK_266_MHZ 266000000 +#define IO_MACRO_CLK_228_MHZ 228000000 +#define IO_MACRO_CLK_200_MHZ 200000000 +#define IO_MACRO_CLK_100_MHZ 100000000 +#define IO_MACRO_CLK_24MHZ 24000000 + +#define QPIC_IO_MACRO_CLK 0 +#define QPIC_CORE_CLK 1 +#define XO_CLK_SRC 2 +#define GPLL0_CLK_SRC 3 +#define FB_CLK_BIT (1 << 4) +#define UPDATE_EN 0x1 + int uart_clock_config(struct ipq_serial_platdata *plat); #endif /*IPQ9574_CLK_H*/ diff --git a/arch/arm/include/asm/arch-qca-common/qpic_nand.h b/arch/arm/include/asm/arch-qca-common/qpic_nand.h index 8c96f18c6f..fe86206cd0 100644 --- a/arch/arm/include/asm/arch-qca-common/qpic_nand.h +++ b/arch/arm/include/asm/arch-qca-common/qpic_nand.h @@ -32,7 +32,7 @@ #if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI) \ || defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ5018) \ - || defined(CONFIG_IPQ9574) + || defined(CONFIG_DEVSOC) || defined(CONFIG_IPQ9574) #define QPIC_EBI2ND_BASE (0x079b0000) #else #error "QPIC NAND not supported" diff --git a/board/devsoc/Kconfig b/board/devsoc/Kconfig index d54fa8bb75..c8d8651471 100644 --- a/board/devsoc/Kconfig +++ b/board/devsoc/Kconfig @@ -12,4 +12,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "devsoc" +config NAND_FLASH + bool "Enable NAND Framework" + +config QPIC_SERIAL + bool "Enable QPIC serial NAND" endif diff --git a/board/qca/arm/devsoc/clock.c b/board/qca/arm/devsoc/clock.c index 2962d9abe7..99399367c9 100644 --- a/board/qca/arm/devsoc/clock.c +++ b/board/qca/arm/devsoc/clock.c @@ -80,3 +80,11 @@ int uart_clock_config(struct ipq_serial_platdata *plat) writel(cbcr_val, GCC_BLSP1_UART_APPS_CBCR(plat->port_id)); return 0; } + +#ifdef CONFIG_QPIC_NAND +void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, + int req_clk_src_type) +{ + return; +} +#endif diff --git a/board/qca/arm/devsoc/devsoc.c b/board/qca/arm/devsoc/devsoc.c index 112ef42343..7293cbdada 100644 --- a/board/qca/arm/devsoc/devsoc.c +++ b/board/qca/arm/devsoc/devsoc.c @@ -24,6 +24,10 @@ #include #include #include +#ifdef CONFIG_QPIC_NAND +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +39,12 @@ const char *del_node[] = {"uboot", NULL}; const add_node_t add_fdt_node[] = {{}}; +unsigned int qpic_frequency = 0, qpic_phase = 0; + +#ifdef CONFIG_QPIC_SERIAL +extern unsigned int qpic_training_offset; +#endif + void qca_serial_init(struct ipq_serial_platdata *plat) { int ret; @@ -103,15 +113,30 @@ void reset_cpu(unsigned long a) while(1); } - void board_nand_init(void) { +#ifdef CONFIG_QPIC_SERIAL + /* check for nand node in dts + * if nand node in dts is disabled then + * simply return from here without + * initializing + */ + int node; + node = fdt_path_offset(gd->fdt_blob, "/nand-controller"); + if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) { + printf("QPIC: disabled, skipping initialization\n"); + } else { + qpic_nand_init(NULL); + } +#endif #ifdef CONFIG_QCA_SPI int gpio_node; gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio"); if (gpio_node >= 0) { qca_gpio_init(gpio_node); +#ifdef CONFIG_MTD_DEVICE ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX); +#endif } #endif } diff --git a/board/qca/arm/devsoc/devsoc.h b/board/qca/arm/devsoc/devsoc.h index ea4a830065..cd7c10a48c 100644 --- a/board/qca/arm/devsoc/devsoc.h +++ b/board/qca/arm/devsoc/devsoc.h @@ -25,24 +25,21 @@ extern const char *rsvd_node; extern const char *del_node[]; extern const add_node_t add_fdt_node[]; -/* - * weak function - */ - -__weak void aquantia_phy_reset_init_done(void) {} -__weak void aquantia_phy_reset_init(void) {} -__weak void qgic_init(void) {} -__weak void handle_noc_err(void) {} -__weak void board_pcie_clock_init(int id) {} -__weak void ubi_power_collapse(void) {} - - #define KERNEL_AUTH_CMD 0x13 #define SCM_CMD_SEC_AUTH 0x15 #define BLSP1_UART0_BASE 0x078AF000 #define UART_PORT_ID(reg) ((reg - BLSP1_UART0_BASE) / 0x1000) +/* + * weak function + */ +__weak void aquantia_phy_reset_init_done(void) {} +__weak void aquantia_phy_reset_init(void) {} +__weak void qgic_init(void) {} +__weak void handle_noc_err(void) {} +__weak void board_pcie_clock_init(int id) {} +__weak void ubi_power_collapse(void) {} /* * SMEM @@ -154,5 +151,7 @@ void ipq_fdt_fixup_socinfo(void *blob); int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable); int smem_ram_ptable_init_v2( struct usable_ram_partition_table *usable_ram_partition_table); +void qpic_set_clk_rate(unsigned int clk_rate, int blk_type, + int req_clk_src_type); #endif /* _DEVSOC_CDP_H_ */ diff --git a/configs/devsoc_defconfig b/configs/devsoc_defconfig index 3683d54a83..4e0e76a6b5 100644 --- a/configs/devsoc_defconfig +++ b/configs/devsoc_defconfig @@ -226,12 +226,12 @@ CONFIG_MMC_FLASH=y # # Generic NAND options # -# CONFIG_NAND_FLASH is not set +CONFIG_NAND_FLASH=y # # Serial NAND # -# CONFIG_QPIC_SERIAL is not set +CONFIG_QPIC_SERIAL=y # # SPI Flash Support diff --git a/include/configs/devsoc.h b/include/configs/devsoc.h index 5b604840ad..608d2f0ab2 100644 --- a/include/configs/devsoc.h +++ b/include/configs/devsoc.h @@ -137,20 +137,6 @@ extern loff_t board_env_size; #define CONFIG_ENV_RANGE board_env_range #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (500 << 10)) -/* - * NAND Flash Configs -*/ - -/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode - * CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode. - * BAM is enabled by default. - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_SYS_NAND_SELF_INIT - - -#define CONFIG_CMD_NAND - #define CONFIG_IPQ_NO_MACS 1 /* @@ -250,6 +236,38 @@ extern loff_t board_env_size; #define CONFIG_QUP_SPI_USE_DMA 1 #define CONFIG_QCA_BAM 1 +/* + * NAND Flash Configs + */ + +/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode + * CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode. + * BAM is enabled by default. + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_SYS_NAND_SELF_INIT + +#ifdef CONFIG_NAND_FLASH +#define CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_QPIC_NAND +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_CMD_NAND_YAFFS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#endif + +#ifdef CONFIG_QPIC_SERIAL +#ifdef QSPI_SERIAL_DEBUG /* QSPI DEBUG */ +#define qspi_debug(fmt,args...) printf (fmt ,##args) +#else +#define qspi_debug(fmt,args...) +#endif /* QSPI DEBUG */ +#define CONFIG_PAGE_SCOPE_MULTI_PAGE_READ +#define CONFIG_QSPI_SERIAL_TRAINING +#define CONFIG_QSPI_LAYOUT_SWITCH +#endif + #undef CONFIG_BOOTM_NETBSD #undef CONFIG_BOOTM_PLAN9 #undef CONFIG_BOOTM_RTEMS