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arm: socfpga: cache: Define cacheline size

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The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut 2014-09-15 01:27:57 +02:00
parent 807abb18f1
commit 9ca2116ce4
1 changed files with 2 additions and 0 deletions
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2
include/configs/socfpga_cyclone5.h
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@ -26,6 +26,8 @@
#define CONFIG_SOCFPGA
#define CONFIG_CLOCKS
#define CONFIG_SYS_CACHELINE_SIZE 32
/* base address for .text section */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040