diff --git a/arch/arm/dts/ipq9574-emulation.dts b/arch/arm/dts/ipq9574-emulation.dts
index 25e610c8bc..71c4a9ad87 100644
--- a/arch/arm/dts/ipq9574-emulation.dts
+++ b/arch/arm/dts/ipq9574-emulation.dts
@@ -105,4 +105,11 @@
 			};
 		};
 	};
+
+	ess-switch {
+		switch_mac_mode0 = <PORT_WRAPPER_SGMII0_RGMII4>;
+		switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
+		switch_mac_mode2 = <PORT_WRAPPER_SGMII0_RGMII4>;
+		uniphy0_port5 = <1>;
+	};
 };
diff --git a/arch/arm/dts/ipq9574-soc.dtsi b/arch/arm/dts/ipq9574-soc.dtsi
index a610fd86d4..c2c838f7e8 100644
--- a/arch/arm/dts/ipq9574-soc.dtsi
+++ b/arch/arm/dts/ipq9574-soc.dtsi
@@ -13,6 +13,7 @@
 
 #include "skeleton.dtsi"
 #include <dt-bindings/qcom/gpio-ipq9574.h>
+#include <dt-bindings/qcom/eth-ipq9574.h>
 
 / {
 
diff --git a/include/dt-bindings/qcom/eth-ipq9574.h b/include/dt-bindings/qcom/eth-ipq9574.h
index 00e7f76c5e..3d618c919a 100644
--- a/include/dt-bindings/qcom/eth-ipq9574.h
+++ b/include/dt-bindings/qcom/eth-ipq9574.h
@@ -15,17 +15,33 @@
 #define __DT_BINDINGS_IPQ9574_ETH_H__
 
 /* ESS Switch Mac Modes */
-#define PORT_WRAPPER_PSGMII 0x0
-#define PORT_WRAPPER_SGMII 0x1
-#define PORT_WRAPPER_USXGMII 0x2
-#define PORT_WRAPPER_QSGMII 0x5
-#define PORT_WRAPPER_SGMII_PLUS 0x6
-#define PORT_WRAPPER_10GBASE_R 0x7
-#define PORT_WRAPPER_SGMII_FIBER 0x8
-#define UNUSED 0xFF
+#define PORT_WRAPPER_PSGMII		0
+#define PORT_WRAPPER_PSGMII_RGMII5	1
+#define PORT_WRAPPER_SGMII0_RGMII5	2
+#define PORT_WRAPPER_SGMII1_RGMII5	3
+#define PORT_WRAPPER_PSGMII_RMII0	4
+#define PORT_WRAPPER_PSGMII_RMII1	5
+#define PORT_WRAPPER_PSGMII_RMII0_RMII1	6
+#define PORT_WRAPPER_PSGMII_RGMII4	7
+#define PORT_WRAPPER_SGMII0_RGMII4	8
+#define PORT_WRAPPER_SGMII1_RGMII4	9
+#define PORT_WRAPPER_SGMII4_RGMII4	10
+#define PORT_WRAPPER_QSGMII		11
+#define PORT_WRAPPER_SGMII_PLUS		12
+#define PORT_WRAPPER_USXGMII		13
+#define PORT_WRAPPER_10GBASE_R		14
+#define PORT_WRAPPER_SGMII_CHANNEL0	15
+#define PORT_WRAPPER_SGMII_CHANNEL1	16
+#define PORT_WRAPPER_SGMII_CHANNEL4	17
+#define PORT_WRAPPER_RGMII		18
+#define PORT_WRAPPER_PSGMII_FIBER	19
+#define PORT_WRAPPER_SGMII_FIBER	20
+#define PORT_WRAPPER_MAX		0xFF
 
 /* ETH PHY Types */
-#define MALIBU_PHY_TYPE 0x1
-#define QCA8081_PHY_TYPE 0x2
-#define AQ_PHY_TYPE 0x3
+#define MALIBU_PHY_TYPE			0x1
+#define QCA8081_PHY_TYPE		0x2
+#define AQ_PHY_TYPE			0x3
+#define QCA8033_PHY_TYPE		0x4
+#define SFP_PHY_TYPE			0x5
 #endif