From 11329094c29a385764d82829ac07f401b14cd662 Mon Sep 17 00:00:00 2001
From: Antony Arun T <antothom@codeaurora.org>
Date: Mon, 15 Apr 2019 16:48:16 +0530
Subject: [PATCH] ipq6018: Enable PMIC reset during abnormal reset

Change-Id: I353f13f8b7ca286ad7c1bcd2d5c162e5592b2a86
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
---
 arch/arm/dts/ipq6018-soc.dtsi    | 24 +++++++++++++++
 board/qca/arm/common/crashdump.c |  2 +-
 board/qca/arm/ipq40xx/ipq40xx.c  |  5 ++++
 board/qca/arm/ipq6018/ipq6018.c  | 51 ++++++++++++++++++++++++++++++++
 board/qca/arm/ipq806x/ipq806x.c  |  5 ++++
 board/qca/arm/ipq807x/ipq807x.c  |  5 ++++
 include/configs/ipq6018.h        |  5 ++++
 7 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/ipq6018-soc.dtsi b/arch/arm/dts/ipq6018-soc.dtsi
index 3b8401f172..8edde413f2 100644
--- a/arch/arm/dts/ipq6018-soc.dtsi
+++ b/arch/arm/dts/ipq6018-soc.dtsi
@@ -249,6 +249,30 @@
 
 		};
 	};
+	i2c1: i2c@78b7000 {
+		compatible = "qcom,qup-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x78b7000 0x600>;
+		clock-frequency  = <400000>;
 
+		i2c_gpio {
+			gpio1 {
+				gpio = <46>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_ENABLE>;
+			};
+
+			gpio2 {
+				gpio = <47>;
+				func = <1>;
+				pull = <GPIO_PULL_UP>;
+				drvstr = <GPIO_2MA>;
+				oe = <GPIO_OE_ENABLE>;
+			};
+		};
+	};
 };
 
diff --git a/board/qca/arm/common/crashdump.c b/board/qca/arm/common/crashdump.c
index b893732ca3..31e6dab2b9 100644
--- a/board/qca/arm/common/crashdump.c
+++ b/board/qca/arm/common/crashdump.c
@@ -493,7 +493,7 @@ void dump_func(unsigned int dump_level)
 	 * when crashmagic is found
 	 */
 reset:
-	run_command("reset", 0);
+	reset_board();
 }
 
 /*
diff --git a/board/qca/arm/ipq40xx/ipq40xx.c b/board/qca/arm/ipq40xx/ipq40xx.c
index 044b06450e..0412f95693 100644
--- a/board/qca/arm/ipq40xx/ipq40xx.c
+++ b/board/qca/arm/ipq40xx/ipq40xx.c
@@ -146,6 +146,11 @@ void reset_cpu(ulong addr)
 	while (1);
 }
 
+void reset_board(void)
+{
+	run_command("reset", 0);
+}
+
 void board_nand_init(void)
 {
 	int gpio_node;
diff --git a/board/qca/arm/ipq6018/ipq6018.c b/board/qca/arm/ipq6018/ipq6018.c
index 1d9ceae72e..68c3bd98c1 100644
--- a/board/qca/arm/ipq6018/ipq6018.c
+++ b/board/qca/arm/ipq6018/ipq6018.c
@@ -25,6 +25,9 @@
 #include <mmc.h>
 #include <sdhci.h>
 #include <usb.h>
+#include <i2c.h>
+#include <dm.h>
+#include <command.h>
 
 #define DLOAD_MAGIC_COOKIE	0x10
 DECLARE_GLOBAL_DATA_PTR;
@@ -70,6 +73,8 @@ struct dumpinfo_t dumpinfo_s[] = {
 	{ "UTCM.BIN", 0x08600658, 0x00030000, 0, 1, 0x2000 },
 };
 int dump_entries_s = ARRAY_SIZE(dumpinfo_s);
+u32 *tz_wonce = (u32 *)CONFIG_IPQ6018_TZ_WONCE_3_ADDR;
+
 
 void uart2_configure_mux(void)
 {
@@ -165,6 +170,40 @@ void qca_serial_init(struct ipq_serial_platdata *plat)
 	qca_gpio_init(node);
 }
 
+int do_pmic_reset()
+{
+	struct udevice *bus, *dev;
+	int bus_no=0;
+	int ret;
+	uchar byte = CONFIG_IPQ6018_PMIC_RESET_VAL;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, bus_no, &bus);
+	if (ret) {
+		debug("%s: No bus %d\n", __func__, bus_no);
+		return -1;
+	}
+
+	ret = dm_i2c_probe(bus, CONFIG_IPQ6018_PMIC_CHIP_ADDR, 0, &dev);
+	if (ret) {
+		printf("Probe failed\n");
+		return -1;
+	}
+
+	ret = i2c_get_chip(bus, CONFIG_IPQ6018_PMIC_CHIP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Error 'i2c_get_chip': %d\n",ret);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = dm_i2c_write(dev, CONFIG_IPQ6018_PMIC_OFFSET, &byte, 1);
+	if (ret) {
+		printf("Error writing the chip: %d\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	return 0;
+}
+
 void reset_crashdump(void)
 {
 	unsigned int ret = 0;
@@ -959,6 +998,18 @@ void reset_cpu(unsigned long a)
 	while(1);
 }
 
+void reset_board(void)
+{
+	if(*tz_wonce == 0) {	/*COLD REBOOT*/
+		if(do_pmic_reset())
+			printf("PMIC Reset failed, please do power cycle\n");
+	}
+	else {		/*WARM REBOOT*/
+		psci_sys_reset();
+	}
+	while(1);	/*loop here inorder to avoid returning to console*/
+}
+
 void ipq_fdt_fixup_socinfo(void *blob)
 {
 	return;
diff --git a/board/qca/arm/ipq806x/ipq806x.c b/board/qca/arm/ipq806x/ipq806x.c
index 42cc3aaf85..b23c613d05 100644
--- a/board/qca/arm/ipq806x/ipq806x.c
+++ b/board/qca/arm/ipq806x/ipq806x.c
@@ -188,6 +188,11 @@ void reset_cpu(unsigned long a)
 	while(1);
 }
 
+void reset_board(void)
+{
+	run_command("reset", 0);
+}
+
 void ipq_uboot_fdt_fixup(void)
 {
 	int ret, len;
diff --git a/board/qca/arm/ipq807x/ipq807x.c b/board/qca/arm/ipq807x/ipq807x.c
index c071e44845..e44d3fc90a 100644
--- a/board/qca/arm/ipq807x/ipq807x.c
+++ b/board/qca/arm/ipq807x/ipq807x.c
@@ -243,6 +243,11 @@ void reset_cpu(unsigned long a)
 	while(1);
 }
 
+void reset_board(void)
+{
+	run_command("reset", 0);
+}
+
 void emmc_clock_config(int mode)
 {
 	/* Enable root clock generator */
diff --git a/include/configs/ipq6018.h b/include/configs/ipq6018.h
index bfcf715498..de045677de 100644
--- a/include/configs/ipq6018.h
+++ b/include/configs/ipq6018.h
@@ -290,6 +290,11 @@ extern loff_t board_env_size;
 #define RPM_VERSION				3
 #endif
 
+#define CONFIG_IPQ6018_PMIC_CHIP_ADDR		0x69
+#define CONFIG_IPQ6018_PMIC_OFFSET		0x0
+#define CONFIG_IPQ6018_PMIC_RESET_VAL		0x40
+#define CONFIG_IPQ6018_TZ_WONCE_3_ADDR		0x193d00C
+
 #define CONFIG_IPQ6018_EDMA		1
 #define CONFIG_IPQ6018_BRIDGED_MODE	1
 #define CONFIG_NET_RETRY_COUNT		5