From 8d670ad213ee961b5086ea25998a1cc10f2bc907 Mon Sep 17 00:00:00 2001
From: Pavithra Palanisamy <pavip@codeaurora.org>
Date: Wed, 30 May 2018 15:00:32 +0530
Subject: [PATCH] ipq807x: Increase drive strength of nand_gpio pins

This change increases Drive strength of nand-controller
GPIO pins from 2 MA to 8 MA to support all NAND flash.

Change-Id: I250deb47f0ddc770fe5c22dad1be32eb1a8f129d
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
---
 arch/arm/dts/ipq807x-soc.dtsi | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/dts/ipq807x-soc.dtsi b/arch/arm/dts/ipq807x-soc.dtsi
index 834136dbf6..26a101baad 100644
--- a/arch/arm/dts/ipq807x-soc.dtsi
+++ b/arch/arm/dts/ipq807x-soc.dtsi
@@ -134,98 +134,98 @@
 				gpio = <1>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio2 {
 				gpio = <3>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio3 {
 				gpio = <4>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio4 {
 				gpio = <5>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio5 {
 				gpio = <6>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio6 {
 				gpio = <7>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio7 {
 				gpio = <8>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio8 {
 				gpio = <10>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio9 {
 				gpio = <11>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio10 {
 				gpio = <12>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio11 {
 				gpio = <13>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio12 {
 				gpio = <14>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio13 {
 				gpio = <15>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};
 			gpio14 {
 				gpio = <17>;
 				func = <1>;
 				pull = <GPIO_PULL_UP>;
-				drvstr = <GPIO_2MA>;
+				drvstr = <GPIO_8MA>;
 				oe = <GPIO_OE_DISABLE>;
 			};