mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
ipq9048: Add USB support
Change-Id: I4e638f9fef05551f9e96744a9fb719fbc6d0ffb4 Signed-off-by: anusha <anusharao@codeaurora.org>
This commit is contained in:
anusha
Gerrit - the friendly Code Review server
parent
b46fde9c99
commit
8bdcb0c32b
6 changed files with 436 additions and 6 deletions
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@ -23,6 +23,7 @@
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console = "/serial@78AF000";
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nand = "/nand-controller@79B0000";
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mmc = "/sdhci@7804000";
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usb0 = "/xhci@8a00000";
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};
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timer {
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@ -37,4 +38,8 @@
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mmc: sdhci@7804000 {
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compatible = "qcom,sdhci-msm";
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};
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xhci@8a00000 {
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qcom,emulation = <1>;
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};
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};
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@ -66,6 +66,13 @@
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compatible = "qcom,sdhci-msm";
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};
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xhci@8a00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8a00000 0xcd00>;
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};
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timer {
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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@ -26,6 +26,7 @@
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#include <ipq9048.h>
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#include <mmc.h>
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#include <sdhci.h>
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sdhci_host mmc_host;
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@ -270,6 +271,277 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void board_usb_deinit(int id)
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{
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int nodeoff;
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char node_name[8];
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snprintf(node_name, sizeof(node_name), "usb%d", id);
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nodeoff = fdt_path_offset(gd->fdt_blob, node_name);
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if (fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0))
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return;
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/* Enable USB PHY Power down */
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setbits_le32(USB30_PHY_1_QUSB2PHY_BASE + 0xB4, 0x1);
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/* Disable clocks */
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0xcff0, GCC_USB0_MASTER_CBCR);
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writel(0, GCC_USB0_SLEEP_CBCR);
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writel(0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0, GCC_USB0_AUX_CBCR);
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/* GCC_QUSB2_0_PHY_BCR */
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set_mdelay_clearbits_le32(GCC_QUSB2_0_PHY_BCR, 0x1, 10);
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/* GCC_USB0_PHY_BCR */
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set_mdelay_clearbits_le32(GCC_USB0_PHY_BCR, 0x1, 10);
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/* GCC Reset USB BCR */
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set_mdelay_clearbits_le32(GCC_USB_BCR, 0x1, 10);
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}
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static void usb_clock_init(int id)
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{
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int cfg;
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/* Configure usb0_master_clk_src */
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cfg = (GCC_USB0_MASTER_CFG_RCGR_SRC_SEL |
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GCC_USB0_MASTER_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_USB0_MASTER_CFG_RCGR);
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writel(CMD_UPDATE, GCC_USB0_MASTER_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MASTER_CMD_RCGR);
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/* Configure usb0_mock_utmi_clk_src */
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cfg = (GCC_USB_MOCK_UTMI_SRC_SEL |
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GCC_USB_MOCK_UTMI_SRC_DIV);
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writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR);
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writel(UTMI_M, GCC_USB0_MOCK_UTMI_M);
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writel(UTMI_N, GCC_USB0_MOCK_UTMI_N);
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writel(UTMI_D, GCC_USB0_MOCK_UTMI_D);
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writel(CMD_UPDATE, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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/* Configure usb0_aux_clk_src */
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cfg = (GCC_USB0_AUX_CFG_SRC_SEL |
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GCC_USB0_AUX_CFG_SRC_DIV);
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writel(cfg, GCC_USB0_AUX_CFG_RCGR);
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writel(AUX_M, GCC_USB0_AUX_M);
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writel(AUX_N, GCC_USB0_AUX_N);
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writel(AUX_D, GCC_USB0_AUX_D);
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writel(CMD_UPDATE, GCC_USB0_AUX_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_AUX_CMD_RCGR);
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/* Configure CBCRs */
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writel((readl(GCC_USB0_MASTER_CBCR) | CLK_ENABLE),
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GCC_USB0_MASTER_CBCR);
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writel(CLK_ENABLE, GCC_USB0_SLEEP_CBCR);
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writel(CLK_ENABLE, GCC_USB0_MOCK_UTMI_CBCR);
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writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN),
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GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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}
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static void usb_init_hsphy(void __iomem *phybase)
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{
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/* Enable QUSB2PHY Power down */
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setbits_le32(phybase+0xB4, 0x1);
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/* PHY Config Sequence */
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/* QUSB2PHY_PLL:PLL Feedback Divider Value */
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out_8(phybase+0x00, 0x14);
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/* QUSB2PHY_PORT_TUNE1: USB Product Application Tuning Register A */
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out_8(phybase+0x80, 0xF8);
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/* QUSB2PHY_PORT_TUNE2: USB Product Application Tuning Register B */
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out_8(phybase+0x84, 0xB3);
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/* QUSB2PHY_PORT_TUNE3: USB Product Application Tuning Register C */
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out_8(phybase+0x88, 0x83);
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/* QUSB2PHY_PORT_TUNE4: USB Product Application Tuning Register D */
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out_8(phybase+0x8C, 0xC0);
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/* QUSB2PHY_PORT_TEST2 */
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out_8(phybase+0x9C, 0x14);
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/* QUSB2PHY_PLL_TUNE: PLL Test Configuration */
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out_8(phybase+0x08, 0x30);
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/* QUSB2PHY_PLL_USER_CTL1: PLL Control Configuration */
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out_8(phybase+0x0C, 0x79);
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/* QUSB2PHY_PLL_USER_CTL2: PLL Control Configuration */
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out_8(phybase+0x10, 0x21);
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/* QUSB2PHY_PORT_TUNE5 */
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out_8(phybase+0x90, 0x00);
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/* QUSB2PHY_PLL_PWR_CTL: PLL Manual SW Programming
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* and Biasing Power Options */
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out_8(phybase+0x18, 0x00);
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/* QUSB2PHY_PLL_AUTOPGM_CTL1: Auto vs. Manual PLL/Power-mode
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* programming State Machine Control Options */
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out_8(phybase+0x1C, 0x9F);
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/* QUSB2PHY_PLL_TEST: PLL Test Configuration-Disable diff ended clock */
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out_8(phybase+0x04, 0x80);
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/* Disable QUSB2PHY Power down */
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clrbits_le32(phybase+0xB4, 0x1);
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}
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static void usb_init_ssphy(void __iomem *phybase)
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{
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out_8(phybase + USB3_PHY_POWER_DOWN_CONTROL,0x1);
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out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x1a);
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out_8(phybase + QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08);
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out_8(phybase + QSERDES_COM_CLK_SELECT,0x30);
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out_8(phybase + QSERDES_COM_BG_TRIM,0x0f);
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out_8(phybase + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b);
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out_8(phybase + QSERDES_COM_SVS_MODE_CLK_SEL,0x01);
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out_8(phybase + QSERDES_COM_HSCLK_SEL,0x00);
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out_8(phybase + QSERDES_COM_CMN_CONFIG,0x06);
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out_8(phybase + QSERDES_COM_PLL_IVCO,0x0f);
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out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x06);
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out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x68);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0xAB);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0xAA);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x02);
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out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x09);
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out_8(phybase + QSERDES_COM_PLL_RCTRL_MODE0,0x16);
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out_8(phybase + QSERDES_COM_PLL_CCTRL_MODE0,0x28);
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out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0xA0);
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out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0xAA);
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out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x29);
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out_8(phybase + QSERDES_COM_LOCK_CMP3_MODE0,0x00);
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out_8(phybase + QSERDES_COM_CORE_CLK_EN,0x00);
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out_8(phybase + QSERDES_COM_LOCK_CMP_CFG,0x00);
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out_8(phybase + QSERDES_COM_VCO_TUNE_MAP,0x00);
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out_8(phybase + QSERDES_COM_BG_TIMER,0x0a);
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out_8(phybase + QSERDES_COM_SSC_EN_CENTER,0x01);
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out_8(phybase + QSERDES_COM_SSC_PER1,0x7D);
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out_8(phybase + QSERDES_COM_SSC_PER2,0x01);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER1,0x00);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER2,0x00);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0x0A);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x05);
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out_8(phybase + QSERDES_RX_UCDR_SO_GAIN,0x06);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8);
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out_8(phybase + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL,0x77);
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out_8(phybase + QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2,0x80);
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out_8(phybase + QSERDES_RX_SIGDET_CNTRL,0x03);
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out_8(phybase + QSERDES_RX_SIGDET_DEGLITCH_CNTRL,0x16);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0c);
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out_8(phybase + QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D,0x45);
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out_8(phybase + QSERDES_TX_RCV_DETECT_LVL_2,0x12);
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out_8(phybase + QSERDES_TX_LANE_MODE,0x06);
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out_8(phybase + PCS_TXDEEMPH_M6DB_V0,0x15);
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out_8(phybase + PCS_TXDEEMPH_M3P5DB_V0,0x0e);
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out_8(phybase + PCS_FLL_CNTRL2,0x83);
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out_8(phybase + PCS_FLL_CNTRL1,0x02);
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out_8(phybase + PCS_FLL_CNT_VAL_L,0x09);
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out_8(phybase + PCS_FLL_CNT_VAL_H_TOL,0xa2);
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out_8(phybase + PCS_FLL_MAN_CODE,0x85);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG1,0xd1);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG2,0x1f);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG3,0x47);
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out_8(phybase + PCS_POWER_STATE_CONFIG2,0x1b);
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out_8(phybase + PCS_RXEQTRAINING_WAIT_TIME,0x75);
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out_8(phybase + PCS_RXEQTRAINING_RUN_TIME,0x13);
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out_8(phybase + PCS_LFPS_TX_ECSTART_EQTLOCK,0x86);
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out_8(phybase + PCS_PWRUP_RESET_DLY_TIME_AUXCLK,0x04);
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out_8(phybase + PCS_TSYNC_RSYNC_TIME,0x44);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_L,0xe7);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_H,0x03);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_L,0x40);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_H,0x00);
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out_8(phybase + PCS_RX_SIGDET_LVL,0x88);
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out_8(phybase + USB3_PCS_TXDEEMPH_M6DB_V0,0x17);
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out_8(phybase + USB3_PCS_TXDEEMPH_M3P5DB_V0,0x0f);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0);
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out_8(phybase + USB3_PHY_START_CONTROL,0x03);
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out_8(phybase + USB3_PHY_SW_RESET,0x00);
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}
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static void usb_init_phy(int index)
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{
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void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
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boot_clk_ctl = (u32 *)GCC_USB_0_BOOT_CLOCK_CTL;
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usb_bcr = (u32 *)GCC_USB_BCR;
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qusb2_phy_bcr = (u32 *)GCC_QUSB2_0_PHY_BCR;
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/* Disable USB Boot Clock */
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clrbits_le32(boot_clk_ctl, 0x0);
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/* GCC Reset USB BCR */
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set_mdelay_clearbits_le32(usb_bcr, 0x1, 10);
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/* GCC_QUSB2_PHY_BCR */
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setbits_le32(qusb2_phy_bcr, 0x1);
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/* GCC_USB0_PHY_BCR */
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setbits_le32(GCC_USB0_PHY_BCR, 0x1);
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setbits_le32(GCC_USB3PHY_0_PHY_BCR, 0x1);
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mdelay(10);
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clrbits_le32(GCC_USB3PHY_0_PHY_BCR, 0x1);
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clrbits_le32(GCC_USB0_PHY_BCR, 0x1);
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/* Config user control register */
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writel(0x0c80c010, USB30_1_GUCTL);
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writel(0x0a87f0a0, USB30_1_FLADJ);
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/* GCC_QUSB2_0_PHY_BCR */
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clrbits_le32(qusb2_phy_bcr, 0x1);
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mdelay(10);
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usb_init_hsphy((u32 *)USB30_PHY_1_QUSB2PHY_BASE);
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usb_init_ssphy((u32 *)USB30_PHY_1_USB3PHY_AHB2PHY_BASE);
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}
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int ipq_board_usb_init(void)
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{
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int i, nodeoff;
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char node_name[8];
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for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
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snprintf(node_name, sizeof(node_name), "usb%d", i);
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nodeoff = fdt_path_offset(gd->fdt_blob, node_name);
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if (!fdtdec_get_int(gd->fdt_blob, nodeoff, "qcom,emulation", 0)) {
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usb_clock_init(i);
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usb_init_phy(i);
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} else {
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/* Config user control register */
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writel(0x0c80c010, USB30_1_GUCTL);
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}
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}
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return 0;
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}
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#endif
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static void __fixup_usb_device_mode(void *blob)
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{
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parse_fdt_fixup("/soc/usb3@8A00000/dwc3@8A00000%dr_mode%?peripheral", blob);
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parse_fdt_fixup("/soc/usb3@8A00000/dwc3@8A00000%maximum-speed%?high-speed", blob);
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}
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static void fdt_fixup_diag_gadget(void *blob)
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{
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__fixup_usb_device_mode(blob);
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parse_fdt_fixup("/soc/qcom,gadget_diag@0%status%?ok", blob);
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}
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void ipq_fdt_fixup_usb_device_mode(void *blob)
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{
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const char *usb_cfg;
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usb_cfg = getenv("usb_mode");
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if (!usb_cfg)
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return;
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if (!strncmp(usb_cfg, "peripheral", sizeof("peripheral")))
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__fixup_usb_device_mode(blob);
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else if (!strncmp(usb_cfg, "diag_gadget", sizeof("diag_gadget")))
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fdt_fixup_diag_gadget(blob);
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else
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printf("%s: invalid param for usb_mode\n", __func__);
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}
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void enable_caches(void)
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{
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qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
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@ -353,11 +625,6 @@ void ipq_fdt_fixup_socinfo(void *blob)
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return;
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}
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void ipq_fdt_fixup_usb_device_mode(void *blob)
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{
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return;
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}
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void fdt_fixup_auto_restart(void *blob)
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{
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return;
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@ -81,6 +81,131 @@
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#define GCC_SDCC1_AHB_CBCR 0x1833034
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#define PSCI_RESET_SMC_ID 0x84000009
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#define set_mdelay_clearbits_le32(addr, value, delay) \
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setbits_le32(addr, value); \
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mdelay(delay); \
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clrbits_le32(addr, value); \
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/* USB Registers */
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#define SW_COLLAPSE_ENABLE (1 << 0)
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#define SW_OVERRIDE_ENABLE (1 << 2)
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#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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||||
#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0xb << 0)
|
||||
#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
|
||||
#define GCC_USB0_MASTER_CBCR 0x182C044
|
||||
#define GCC_USB0_SLEEP_CBCR 0x182C058
|
||||
#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
|
||||
#define GCC_USB_MOCK_UTMI_SRC_SEL (0 << 8)
|
||||
#define GCC_USB_MOCK_UTMI_SRC_DIV (1 << 0)
|
||||
#define UTMI_M 0x1
|
||||
#define UTMI_N 0xf7
|
||||
#define UTMI_D 0xf6
|
||||
#define GCC_USB0_MOCK_UTMI_M 0x182C034
|
||||
#define GCC_USB0_MOCK_UTMI_N 0x182C038
|
||||
#define GCC_USB0_MOCK_UTMI_D 0x182C03C
|
||||
#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
|
||||
#define GCC_USB0_MOCK_UTMI_CBCR 0x182C04C
|
||||
#define GCC_USB0_PHY_PIPE_MISC 0x182C074
|
||||
#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
|
||||
#define GCC_USB0_AUX_CBCR 0x182C048
|
||||
#define GCC_USB0_PIPE_CBCR 0x182C054
|
||||
#define GCC_USB_0_BOOT_CLOCK_CTL 0x182C060
|
||||
#define GCC_USB_BCR 0x182C000
|
||||
#define GCC_QUSB2_0_PHY_BCR 0x182C068
|
||||
#define GCC_USB0_PHY_BCR 0x182C06C
|
||||
#define GCC_USB3PHY_0_PHY_BCR 0x182C070
|
||||
#define USB30_1_GUCTL 0x8A0C12C
|
||||
#define USB30_1_FLADJ 0x8A0C630
|
||||
#define USB30_PHY_1_QUSB2PHY_BASE 0x7B000
|
||||
#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
|
||||
#define GCC_USB0_AUX_CMD_RCGR 0x182C018
|
||||
#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
|
||||
#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
|
||||
#define GCC_USB0_AUX_CFG_SRC_DIV (0 << 0)
|
||||
#define GCC_USB0_AUX_M 0x182C020
|
||||
#define GCC_USB0_AUX_N 0x182C024
|
||||
#define GCC_USB0_AUX_D 0x182C028
|
||||
#define AUX_M 0x0
|
||||
#define AUX_N 0x0
|
||||
#define AUX_D 0x0
|
||||
|
||||
#define USB30_PHY_1_USB3PHY_AHB2PHY_BASE 0x7D000
|
||||
|
||||
#define USB3_PHY_POWER_DOWN_CONTROL 0x804
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL 0xac
|
||||
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
|
||||
#define QSERDES_COM_CLK_SELECT 0x174
|
||||
#define QSERDES_COM_BG_TRIM 0x70
|
||||
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x440
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
|
||||
#define QSERDES_COM_HSCLK_SEL 0x178
|
||||
#define QSERDES_COM_CMN_CONFIG 0x194
|
||||
#define QSERDES_COM_PLL_IVCO 0x048
|
||||
#define QSERDES_COM_SYS_CLK_CTRL 0x3c
|
||||
#define QSERDES_COM_DEC_START_MODE0 0xd0
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xdc
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xe0
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xe4
|
||||
#define QSERDES_COM_CP_CTRL_MODE0 0x78
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE0 0x84
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE0 0x90
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE0 0x4c
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE0 0x50
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE0 0x54
|
||||
#define QSERDES_COM_CORE_CLK_EN 0x18c
|
||||
#define QSERDES_COM_LOCK_CMP_CFG 0xcc
|
||||
#define QSERDES_COM_VCO_TUNE_MAP 0x128
|
||||
#define QSERDES_COM_BG_TIMER 0x0c
|
||||
#define QSERDES_COM_SSC_EN_CENTER 0x10
|
||||
#define QSERDES_COM_SSC_PER1 0x1c
|
||||
#define QSERDES_COM_SSC_PER2 0x20
|
||||
#define QSERDES_COM_SSC_ADJ_PER1 0x14
|
||||
#define QSERDES_COM_SSC_ADJ_PER2 0x18
|
||||
#define QSERDES_COM_SSC_STEP_SIZE1 0x24
|
||||
#define QSERDES_COM_SSC_STEP_SIZE2 0x28
|
||||
#define QSERDES_RX_UCDR_SO_GAIN 0x410
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4d8
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4dc
|
||||
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4e0
|
||||
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL 0x508
|
||||
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x50c
|
||||
#define QSERDES_RX_SIGDET_CNTRL 0x514
|
||||
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51c
|
||||
#define QSERDES_RX_SIGDET_ENABLES 0x510
|
||||
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D 0x268
|
||||
#define QSERDES_TX_RCV_DETECT_LVL_2 0x2ac
|
||||
#define QSERDES_TX_LANE_MODE 0x294
|
||||
#define PCS_TXDEEMPH_M6DB_V0 0x824
|
||||
#define PCS_TXDEEMPH_M3P5DB_V0 0x828
|
||||
#define PCS_FLL_CNTRL2 0x8c8
|
||||
#define PCS_FLL_CNTRL1 0x8c4
|
||||
#define PCS_FLL_CNT_VAL_L 0x8cc
|
||||
#define PCS_FLL_CNT_VAL_H_TOL 0x8d0
|
||||
#define PCS_FLL_MAN_CODE 0x8d4
|
||||
#define PCS_LOCK_DETECT_CONFIG1 0x880
|
||||
#define PCS_LOCK_DETECT_CONFIG2 0x884
|
||||
#define PCS_LOCK_DETECT_CONFIG3 0x888
|
||||
#define PCS_POWER_STATE_CONFIG2 0x864
|
||||
#define PCS_RXEQTRAINING_WAIT_TIME 0x8b8
|
||||
#define PCS_RXEQTRAINING_RUN_TIME 0x8bc
|
||||
#define PCS_LFPS_TX_ECSTART_EQTLOCK 0x8b0
|
||||
#define PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x8a0
|
||||
#define PCS_TSYNC_RSYNC_TIME 0x88c
|
||||
#define PCS_RCVR_DTCT_DLY_P1U2_L 0x870
|
||||
#define PCS_RCVR_DTCT_DLY_P1U2_H 0x874
|
||||
#define PCS_RCVR_DTCT_DLY_U3_L 0x878
|
||||
#define PCS_RCVR_DTCT_DLY_U3_H 0x87c
|
||||
#define PCS_RX_SIGDET_LVL 0x9d8
|
||||
#define USB3_PCS_TXDEEMPH_M6DB_V0 0x824
|
||||
#define USB3_PCS_TXDEEMPH_M3P5DB_V0 0x828
|
||||
#define QSERDES_RX_SIGDET_ENABLES 0x510
|
||||
#define USB3_PHY_START_CONTROL 0x808
|
||||
#define USB3_PHY_SW_RESET 0x800
|
||||
#define NOC_HANDSHAKE_FSM_EN (1 << 15)
|
||||
|
||||
unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
|
||||
unsigned int, unsigned int);
|
||||
|
||||
|
|
@ -197,4 +322,5 @@ extern const char *del_node[];
|
|||
extern const add_node_t add_fdt_node[];
|
||||
int ipq_get_tz_version(char *version_name, int buf_size);
|
||||
void ipq_fdt_fixup_socinfo(void *blob);
|
||||
int ipq_board_usb_init(void);
|
||||
#endif /* _IPQ9048_CDP_H_ */
|
||||
|
|
|
|||
|
|
@ -261,7 +261,12 @@ CONFIG_REQUIRE_SERIAL_CONSOLE=y
|
|||
#
|
||||
# TPM support
|
||||
#
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
|
|
|
|||
|
|
@ -130,6 +130,26 @@ extern loff_t board_env_size;
|
|||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Block Device & Disk Partition Config
|
||||
*/
|
||||
#define HAVE_BLOCK_DEVICE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* USB Support
|
||||
*/
|
||||
#define CONFIG_USB_XHCI_IPQ
|
||||
#ifdef CONFIG_USB_XHCI_IPQ
|
||||
#define CONFIG_USB_XHCI
|
||||
#define CONFIG_USB_XHCI_DWC3
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* NAND Flash Configs
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue