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ipq6018: Add SPI clock settings
Currently SPI clocks are enabled by default in SBL. Added the clock settings in uboot to remove SBL dependency. Change-Id: I78340daeb267edf4f4bb579fba991699d1bccb3d Signed-off-by: anusha <anusharao@codeaurora.org>
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2 changed files with 25 additions and 0 deletions
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@ -324,6 +324,23 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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static void spi_clock_init(void)
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{
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int cfg;
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/* Configure qup1_spi_apps_clk_src */
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cfg = (GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL |
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GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR);
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writel(CMD_UPDATE, GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR);
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/* Configure CBCR */
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writel(CLK_ENABLE, GCC_BLSP1_QUP1_SPI_APPS_CBCR);
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}
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void board_nand_init(void)
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{
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#ifdef CONFIG_QCA_SPI
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@ -333,6 +350,7 @@ void board_nand_init(void)
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qpic_nand_init();
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#ifdef CONFIG_QCA_SPI
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spi_clock_init();
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gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
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if (gpio_node >= 0) {
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qca_gpio_init(gpio_node);
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@ -264,6 +264,13 @@
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#define GCC_PCIE0_PHY_PIPE_MISC_SRC_SEL (0x1 << 8)
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#define GCC_PCIE0_PHY_PIPE_MISC 0x187501C
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#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR 0x1802028
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#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV (0x1F << 0)
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#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1802024
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#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x1802004
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#define set_mdelay_clearbits_le32(addr, value, delay) \
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setbits_le32(addr, value); \
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mdelay(delay); \
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