From cad940227910fb487cb0aeb443f9995f3d44b8f1 Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Tue, 30 Jun 2020 13:43:56 +0530 Subject: [PATCH] ipq5018: reduce delay in pci initialization This changes reduce boot delay because of delay in pci initialization Signed-off-by: Vandhiadevan Karunamoorthy Change-Id: I15d4ed26a07dafe0c8dd7eb8a666b3c7a3d2cfb6 --- board/qca/arm/ipq5018/ipq5018.c | 50 ++++++++++++++++----------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/board/qca/arm/ipq5018/ipq5018.c b/board/qca/arm/ipq5018/ipq5018.c index e7fe245e0c..18ada447ec 100644 --- a/board/qca/arm/ipq5018/ipq5018.c +++ b/board/qca/arm/ipq5018/ipq5018.c @@ -1278,12 +1278,12 @@ static void pcie_v2_clock_init(int lane) if (lane == 1) { base = (void __iomem *)GCC_PCIE1_BOOT_CLOCK_CTL; writel(CLK_ENABLE, GCC_SYS_NOC_PCIE1_AXI_CBCR); - mdelay(100); + mdelay(1); /* Configure pcie1_aux_clk_src */ writel((GCC_PCIE1_AUX_CFG_RCGR_SRC_SEL | GCC_PCIE1_AUX_CFG_RCGR_SRC_DIV), base + PCIE_AUX_CFG_RCGR); - mdelay(100); + mdelay(1); reg_val = readl(base + PCIE_AUX_CMD_RCGR); reg_val &= ~0x1; reg_val |= 0x1; @@ -1293,7 +1293,7 @@ static void pcie_v2_clock_init(int lane) writel((GCC_PCIE1_AXI_CFG_RCGR_SRC_SEL | GCC_PCIE1_AXI_CFG_RCGR_SRC_DIV), base + PCIE_AXI_CFG_RCGR); - mdelay(100); + mdelay(1); reg_val = readl(base + PCIE_AXI_CMD_RCGR); reg_val &= ~0x1; reg_val |= 0x1; @@ -1301,12 +1301,12 @@ static void pcie_v2_clock_init(int lane) } else { /*double lane*/ base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; writel(CLK_ENABLE, GCC_SYS_NOC_PCIE0_AXI_CBCR); - mdelay(100); + mdelay(1); /* Configure pcie1_aux_clk_src */ writel((GCC_PCIE0_AUX_CFG_RCGR_SRC_SEL | GCC_PCIE0_AUX_CFG_RCGR_SRC_DIV), base + PCIE_AUX_CFG_RCGR); - mdelay(100); + mdelay(1); reg_val = readl(base + PCIE_AUX_CMD_RCGR); reg_val &= ~0x1; reg_val |= 0x1; @@ -1316,36 +1316,36 @@ static void pcie_v2_clock_init(int lane) writel((GCC_PCIE0_AXI_CFG_RCGR_SRC_SEL | GCC_PCIE0_AXI_CFG_RCGR_SRC_DIV), base + PCIE_AXI_CFG_RCGR); - mdelay(100); + mdelay(1); reg_val = readl(base + PCIE_AXI_CMD_RCGR); reg_val &= ~0x1; reg_val |= 0x1; writel(reg_val, base + PCIE_AXI_CMD_RCGR); } - mdelay(50); + mdelay(1); reg_val= readl(base + PCIE_AXI_M_CBCR); reg_val |= CLK_ENABLE; writel(reg_val, base + PCIE_AXI_M_CBCR); - mdelay(50); + mdelay(1); reg_val = readl(base + PCIE_AXI_S_CBCR); reg_val |= CLK_ENABLE; writel(reg_val, base + PCIE_AXI_S_CBCR); - mdelay(50); + mdelay(1); writel(CLK_ENABLE, base + PCIE_AHB_CBCR); - mdelay(50); + mdelay(1); writel(CLK_ENABLE, base + PCIE_AUX_CBCR); - mdelay(50); + mdelay(1); writel(CLK_ENABLE, base + PCIE_AXI_S_BRIDGE_CBCR); - mdelay(50); + mdelay(1); reg_val= readl(base + PCIE_PIPE_CBCR); reg_val |= CLK_ENABLE; writel(reg_val, base + PCIE_PIPE_CBCR); - mdelay(50); + mdelay(1); #endif return; } @@ -1363,7 +1363,7 @@ static void pcie_v2_clock_deinit(int lane) base = (void __iomem *)GCC_PCIE0_BOOT_CLOCK_CTL; writel(0x0, GCC_SYS_NOC_PCIE0_AXI_CBCR); } - mdelay (50); + mdelay (5); writel(0x0, base + PCIE_AHB_CBCR); writel(0x0, base + PCIE_AXI_M_CBCR); writel(0x0, base + PCIE_AXI_S_CBCR); @@ -1423,77 +1423,77 @@ static void pcie_reset(int lane) reg_val = readl(base + PCIE_BCR); writel(reg_val | GCC_PCIE_BCR_ENABLE, (base + PCIE_BCR)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_BCR_ENABLE), (base + PCIE_BCR)); reg_val = readl(base + PCIE_PHY_BCR); writel(reg_val | GCC_PCIE_BLK_ARES, (base + PCIE_PHY_BCR)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_BLK_ARES), (base + PCIE_PHY_BCR)); reg_val = readl(base + PCIE_PHY_PHY_BCR); writel(reg_val | GCC_PCIE_BLK_ARES, (base + PCIE_PHY_PHY_BCR)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_BLK_ARES), (base + PCIE_PHY_PHY_BCR)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_PIPE_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_PIPE_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_SLEEP_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_SLEEP_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_CORE_STICKY_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_CORE_STICKY_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_AXI_MASTER_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_AXI_MASTER_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_AXI_SLAVE_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_AXI_SLAVE_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCIE_AHB_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCIE_AHB_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCI_AXI_MASTER_STICKY_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCI_AXI_MASTER_STICKY_ARES), (base + PCIE_MISC_RESET)); reg_val = readl(base + PCIE_MISC_RESET); writel(reg_val | GCC_PCI_AXI_SLAVE_STICKY_ARES, (base + PCIE_MISC_RESET)); - mdelay(20); + mdelay(1); writel(reg_val & (~GCC_PCI_AXI_SLAVE_STICKY_ARES), (base + PCIE_MISC_RESET)); }