diff --git a/drivers/mtd/nand/qpic_nand.c b/drivers/mtd/nand/qpic_nand.c
index 8b087c1ef5..c3d9410433 100644
--- a/drivers/mtd/nand/qpic_nand.c
+++ b/drivers/mtd/nand/qpic_nand.c
@@ -1430,13 +1430,44 @@ static void qpic_spi_init(struct mtd_info *mtd)
 	uint32_t xfer_start = NAND_XFR_STEPS_V1_5_20;
 	int i;
 
+	unsigned int val;
+	int num_desc = 0;
+
+	struct cmd_element *cmd_list_ptr = ce_array;
+	struct cmd_element *cmd_list_ptr_start = ce_array;
+
+	val = readl(NAND_QSPI_MSTR_CONFIG);
+	val |= FB_CLK_BIT;
+
+	bam_add_cmd_element(cmd_list_ptr, NAND_QSPI_MSTR_CONFIG, (uint32_t)val, CE_WRITE_TYPE);
+	cmd_list_ptr++;
+
+	bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_SPI_CFG, (uint32_t)0, CE_WRITE_TYPE);
+	cmd_list_ptr++;
+
+	bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_SPI_CFG, (uint32_t)SPI_CFG_VAL, CE_WRITE_TYPE);
+	cmd_list_ptr++;
+
+	val = SPI_CFG_VAL & ~SPI_LOAD_CLK_CNTR_INIT_EN;
+	bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_SPI_CFG, (uint32_t)val, CE_WRITE_TYPE);
+	cmd_list_ptr++;
+
+	bam_add_one_desc(&bam,
+			CMD_PIPE_INDEX,
+			(unsigned char*)cmd_list_ptr_start,
+			((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
+			BAM_DESC_CMD_FLAG | BAM_DESC_LOCK_FLAG);
+	num_desc++;
+
+	qpic_nand_wait_for_cmd_exec(num_desc);
+
+	num_desc = 0;
+
 	/* set the FB_CLK_BIT of register QPIC_QSPI_MSTR_CONFIG
 	 * to by pass the serial training. if this FB_CLK_BIT
 	 * bit enabled then , we can apply upto maximum 200MHz
 	 * input to IO_MACRO_BLOCK.
 	 */
-	writel((FB_CLK_BIT | readl(NAND_QSPI_MSTR_CONFIG)),
-			NAND_QSPI_MSTR_CONFIG);
 
 	qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK,
 			GPLL0_CLK_SRC);
@@ -1444,25 +1475,6 @@ static void qpic_spi_init(struct mtd_info *mtd)
 	/*qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK,
 			XO_CLK_SRC);*/
 
-	/* Configure the NAND_FLASH_SPI_CFG to load the timer CLK_CNTR_INIT_VAL_VEC
-	 * value, enable the LOAD_CLK_CNTR_INIT_EN bit and enable SPI_CFG mode.
-	 */
-	writel(0x0, NAND_FLASH_SPI_CFG);
-
-	/* Make bit-28 of NAND_FLASH_SPI_CFG register to load
-	 * CLK_CNTR_INIT_VAL_VEC into IO Macro clock generation
-	 * registers is its not worked then,
-	 * check with this val 0x1DB6C00D
-	 */
-	writel(SPI_CFG_VAL, NAND_FLASH_SPI_CFG);
-	/*Change LOAD_CLK_CNTR_INIT_EN to generate a pulse,
-	 * with CLK_CNTR_INIT_VAL_VEC loaded and SPI_CFG enabled
-	 * If not worked then,
-	 * Check with this val 0xDB6C00D
-	 */
-	writel((SPI_CFG_VAL & ~SPI_LOAD_CLK_CNTR_INIT_EN),
-			NAND_FLASH_SPI_CFG);
-
 	/* According to HPG Setting Xfer steps and spi_num_addr_cycles
 	 * is part of initialization flow before reset.However these
 	 * values differ from NAND part to part.sitting in QPIC layer
@@ -1500,9 +1512,26 @@ static void qpic_spi_init(struct mtd_info *mtd)
 	/* No of address cycle is same for Giga device & Micron so
 	 * configure no of address cycle now.
 	 */
-	writel(SPI_NUM_ADDR_CYCLES, NAND_SPI_NUM_ADDR_CYCLES);
+	cmd_list_ptr = ce_array;
+	bam_add_cmd_element(cmd_list_ptr, NAND_SPI_NUM_ADDR_CYCLES,
+			(uint32_t)SPI_NUM_ADDR_CYCLES, CE_WRITE_TYPE);
 
-	writel(SPI_BUSY_CHECK_WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT);
+	cmd_list_ptr++;
+
+	bam_add_cmd_element(cmd_list_ptr, NAND_SPI_BUSY_CHECK_WAIT_CNT,
+			(uint32_t)SPI_BUSY_CHECK_WAIT_CNT, CE_WRITE_TYPE);
+
+	cmd_list_ptr++;
+
+	bam_add_one_desc(&bam,
+			CMD_PIPE_INDEX,
+			(unsigned char*)cmd_list_ptr_start,
+			((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
+			BAM_DESC_CMD_FLAG | BAM_DESC_LOCK_FLAG);
+	num_desc++;
+	qpic_nand_wait_for_cmd_exec(num_desc);
+
+	num_desc = 0;
 }
 #endif
 static int qpic_nand_reset(struct mtd_info *mtd)
@@ -4229,26 +4258,9 @@ void qpic_nand_init(qpic_nand_cfg_t *qpic_nand_cfg)
 		return;
 	}
 
-#ifdef CONFIG_QPIC_SERIAL
-
-	qpic_spi_init(mtd);
-
-	/* Read the Hardware Version register */
-	hw_ver = readl(NAND_VERSION);
-	/* Only maintain major number */
-	hw_ver >>= 28;
-	if (hw_ver >= QCA_QPIC_V2_1_1) {
-		printf("QPIC controller support serial NAND\n");
-	} else {
-		printf("%s : Qpic controller not support serial NAND\n",
-				__func__);
-		return;
-	}
-
 #ifdef CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
 	config.pipes.status_pipe = NAND_BAM_STATUS_PIPE;
 	config.pipes.status_pipe_grp = NAND_BAM_STATUS_PIPE_GRP;
-#endif
 #endif
 	config.pipes.read_pipe = DATA_PRODUCER_PIPE;
 	config.pipes.write_pipe = DATA_CONSUMER_PIPE;
@@ -4265,6 +4277,21 @@ void qpic_nand_init(qpic_nand_cfg_t *qpic_nand_cfg)
 
 	qpic_bam_init(&config);
 
+#ifdef CONFIG_QPIC_SERIAL
+	qpic_spi_init(mtd);
+
+	/* Read the Hardware Version register */
+	hw_ver = readl(NAND_VERSION);
+	/* Only maintain major number */
+	hw_ver >>= 28;
+	if (hw_ver >= QCA_QPIC_V2_1_1) {
+		printf("QPIC controller support serial NAND\n");
+	} else {
+		printf("%s : Qpic controller not support serial NAND\n",
+				__func__);
+		return;
+	}
+#endif
 	ret = qpic_nand_reset(mtd);
 	if (ret < 0)
 		return;