From 75bc424247e55806fef6b8cfe3e65eca32bd3e9c Mon Sep 17 00:00:00 2001 From: Ram Kumar D Date: Mon, 4 Jul 2022 12:36:58 +0530 Subject: [PATCH] driver: net: qca8084: change inline func to non-inline func Currently, bottom level apis such as qca8084 clk and pinconf functions are defined as inline functions, which took around 1.3K memory in the uboot. So, update those functions to non- inline functions to save that space. Change-Id: I2972ca80d7df80a72d4a027e790400f391546d4b Signed-off-by: Ram Kumar D --- drivers/net/ipq_common/ipq_mdio.c | 8 ++++---- drivers/net/ipq_common/ipq_qca8084.c | 6 +++--- drivers/net/ipq_common/ipq_qca8084_clk.c | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/net/ipq_common/ipq_mdio.c b/drivers/net/ipq_common/ipq_mdio.c index e84b199a0a..88eb20e252 100644 --- a/drivers/net/ipq_common/ipq_mdio.c +++ b/drivers/net/ipq_common/ipq_mdio.c @@ -171,7 +171,7 @@ int ipq_phy_read(struct mii_dev *bus, } #ifdef CONFIG_QCA8084_PHY -static inline void split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, +static void split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, uint16_t *page, uint16_t *switch_phy_id) { *r1 = regaddr & 0x1c; @@ -233,7 +233,7 @@ void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val) ipq_mii_write(reg, new_val); } -static inline void ipq_clk_enable(uint32_t reg) +static void ipq_clk_enable(uint32_t reg) { u32 val; @@ -242,7 +242,7 @@ static inline void ipq_clk_enable(uint32_t reg) ipq_mii_write(reg, val); } -static inline void ipq_clk_disable(uint32_t reg) +static void ipq_clk_disable(uint32_t reg) { u32 val; @@ -251,7 +251,7 @@ static inline void ipq_clk_disable(uint32_t reg) ipq_mii_write(reg, val); } -static inline void ipq_clk_reset(uint32_t reg) +static void ipq_clk_reset(uint32_t reg) { u32 val; diff --git a/drivers/net/ipq_common/ipq_qca8084.c b/drivers/net/ipq_common/ipq_qca8084.c index b340e214a3..449f989419 100644 --- a/drivers/net/ipq_common/ipq_qca8084.c +++ b/drivers/net/ipq_common/ipq_qca8084.c @@ -557,12 +557,12 @@ int qca8084_gpio_pin_cfg_get_oe(u32 pin, bool *oe) return rv; } -static inline enum qca8084_pin_config_param pinconf_to_config_param(unsigned long config) +static enum qca8084_pin_config_param pinconf_to_config_param(unsigned long config) { return (enum qca8084_pin_config_param) (config & 0xffUL); } -static inline u32 pinconf_to_config_argument(unsigned long config) +static u32 pinconf_to_config_argument(unsigned long config) { return (u32) ((config >> 8) & 0xffffffUL); } @@ -722,7 +722,7 @@ static int qca8084_reg_field_set(u32 reg_addr, u32 bit_offset, return 0; } -static inline void ipq_qca8084_switch_reset(void) +static void ipq_qca8084_switch_reset(void) { /* Reset switch core */ qca8084_clk_reset(QCA8084_SWITCH_CORE_CLK); diff --git a/drivers/net/ipq_common/ipq_qca8084_clk.c b/drivers/net/ipq_common/ipq_qca8084_clk.c index 894fae8e4f..ea225b897a 100644 --- a/drivers/net/ipq_common/ipq_qca8084_clk.c +++ b/drivers/net/ipq_common/ipq_qca8084_clk.c @@ -390,7 +390,7 @@ static struct clk_lookup qca8084_clk_lookup_table[] = { CLK_LOOKUP(0, 0, 0x30c, BIT(0), QCA8084_UNIPHY_XPCS_RST, NULL, 0, NULL, 0), }; -static inline struct clk_lookup *qca8084_clk_find(const char *clock_id) +static struct clk_lookup *qca8084_clk_find(const char *clock_id) { int i; struct clk_lookup *clk; @@ -404,7 +404,7 @@ static inline struct clk_lookup *qca8084_clk_find(const char *clock_id) return NULL; } -static inline void qca8084_clk_update(uint32_t cmd_reg) +static void qca8084_clk_update(uint32_t cmd_reg) { uint32_t i, reg_val; @@ -933,7 +933,7 @@ void qca8084_port_clk_rate_set(uint32_t qca8084_port_id, uint32_t rate) return; } -static inline void qca8084_clk_ids_get(uint32_t qca8084_port_id, +static void qca8084_clk_ids_get(uint32_t qca8084_port_id, uint8_t mask, char **clk_ids) { switch (qca8084_port_id) {