From ee631ab742a946e04e5222050aa673079322e0a8 Mon Sep 17 00:00:00 2001
From: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Date: Thu, 26 Aug 2021 22:25:23 +0530
Subject: [PATCH] ipq9574: Add support for DPR feature

The command dpr_execute <load_address_of_dpr_binary>
is defined for the user to initiate DPR processing.
Uboot will raise scm call to TZ and pass the DPR load address.

Change-Id: Ide4495b49485a4ac6b722f0cb7d423d6a93946ca
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
---
 arch/arm/cpu/armv7/qca/common/scm.c | 26 ++++++++++++++++
 board/qca/arm/ipq9574/ipq9574.c     | 48 +++++++++++++++++++++++++++++
 board/qca/arm/ipq9574/ipq9574.h     |  1 +
 3 files changed, 75 insertions(+)

diff --git a/arch/arm/cpu/armv7/qca/common/scm.c b/arch/arm/cpu/armv7/qca/common/scm.c
index 61ad5f233d..0ad978c40a 100644
--- a/arch/arm/cpu/armv7/qca/common/scm.c
+++ b/arch/arm/cpu/armv7/qca/common/scm.c
@@ -492,6 +492,28 @@ int qca_scm_part_info(void *cmd_buf,
 	return ret;
 }
 
+int qca_scm_dpr(u32 svc_id, u32 cmd_id, void *buf, size_t len)
+{
+	int ret = 0;
+	uint32_t *status;
+	if (is_scm_armv8())
+	{
+		struct qca_scm_desc desc = {0};
+		desc.arginfo = QCA_SCM_ARGS(1, SCM_VAL);
+		desc.args[0] = *((unsigned int *)buf);
+
+		ret = scm_call_64(svc_id, cmd_id, &desc);
+
+		status = (uint32_t *)(*(((uint32_t *)buf) + 1));
+		*status = desc.ret[0];
+	}
+	else
+	{
+		ret = scm_call(svc_id, cmd_id, buf, len, NULL, 0);
+	}
+	return ret;
+}
+
 int qca_scm_auth_kernel(void *cmd_buf,
 			size_t cmd_len)
 {
@@ -664,6 +686,10 @@ int qca_scm_part_info(void *cmd_buf, size_t cmd_len)
 {
 	return 0;
 }
+int qca_scm_dpr(u32 svc_id, u32 cmd_id, void *buf, size_t len)
+{
+	return 0;
+}
 int qca_scm_auth_kernel(void *cmd_buf,
 			size_t cmd_len)
 {
diff --git a/board/qca/arm/ipq9574/ipq9574.c b/board/qca/arm/ipq9574/ipq9574.c
index 8439af636e..a1c272e96d 100644
--- a/board/qca/arm/ipq9574/ipq9574.c
+++ b/board/qca/arm/ipq9574/ipq9574.c
@@ -40,6 +40,8 @@ extern int ipq_spi_init(u16);
 unsigned int qpic_frequency = 0, qpic_phase = 0;
 extern unsigned int qpic_training_offset;
 
+extern	int qca_scm_dpr(u32, u32, void *, size_t);
+
 void qca_serial_init(struct ipq_serial_platdata *plat)
 {
 	int ret;
@@ -1448,3 +1450,49 @@ void ipq_uboot_fdt_fixup(void)
 	}
 	return;
 }
+
+int do_dpr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int ret;
+	char *loadaddr;
+	uint32_t dpr_status = 0;
+	struct dpr {
+		uint32_t address;
+		uint32_t status;
+	} dpr;
+
+	if (argc > 2) {
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 2){
+		dpr.address = simple_strtoul(argv[1], NULL, 16);
+	} else {
+		loadaddr = getenv("fileaddr");
+
+		if (loadaddr == NULL) {
+			printf("No Arguments provided\n");
+			printf("Command format: dpr_execute <address>\n");
+			return CMD_RET_USAGE;
+		}
+		if (loadaddr != NULL)
+			dpr.address = simple_strtoul(loadaddr, NULL, 16);
+	}
+
+	dpr.status = (uint32_t)&dpr_status;
+
+	ret = qca_scm_dpr(SCM_SVC_FUSE, TME_DPR_PROCESSING,
+			&dpr, sizeof(dpr));
+
+	if (ret || dpr_status){
+		printf("%s: Error in DPR Processing (%d, %d)\n",
+			__func__, ret, dpr_status);
+	} else {
+		printf("DPR Process sucessful\n");
+	}
+	return ret;
+}
+
+U_BOOT_CMD(dpr_execute, 2, 0, do_dpr,
+		"Debug Policy Request processing\n",
+		"dpr_execute [address] - Processing dpr\n");
diff --git a/board/qca/arm/ipq9574/ipq9574.h b/board/qca/arm/ipq9574/ipq9574.h
index 51a6a25399..794a018932 100644
--- a/board/qca/arm/ipq9574/ipq9574.h
+++ b/board/qca/arm/ipq9574/ipq9574.h
@@ -108,6 +108,7 @@
 
 #define KERNEL_AUTH_CMD				0x1E
 #define SCM_CMD_SEC_AUTH			0x1F
+#define TME_DPR_PROCESSING			0x21
 
 #ifdef CONFIG_SMEM_VERSION_C
 #define RAM_PART_NAME_LENGTH			16