From 0cb77bfa7a828f7d62eb92e03861d4fcb4d8226d Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 19 Jul 2011 01:56:06 +0000 Subject: [PATCH 001/145] at91: reworked support for meesc board The meesc board support was broken. Within this opportunity, I completely reworked the board files. Signed-off-by: Daniel Gorsulowski Signed-off-by: Matthias Fuchs --- board/esd/meesc/config.mk | 1 - board/esd/meesc/meesc.c | 49 ++++----- include/configs/meesc.h | 208 ++++++++++++++++++++++---------------- 3 files changed, 147 insertions(+), 111 deletions(-) delete mode 100644 board/esd/meesc/config.mk diff --git a/board/esd/meesc/config.mk b/board/esd/meesc/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/esd/meesc/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 41fa3e1567..ad43531cb1 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop * Lead Tech Design * - * (C) Copyright 2009-2010 + * (C) Copyright 2009-2011 * Daniel Gorsulowski * esd electronic system design gmbh * @@ -27,7 +27,7 @@ */ #include -#include +#include #include #include #include @@ -35,8 +35,6 @@ #include #include #include -#include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -67,8 +65,8 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -88,7 +86,7 @@ static void meesc_nand_hw_init(void) writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); /* Configure RDY/BSY */ @@ -102,9 +100,9 @@ static void meesc_nand_hw_init(void) #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,7 +115,7 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { - at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; /* Configure SMC EBI1_CS0 for EtherCAT */ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | @@ -142,8 +140,9 @@ static void meesc_ethercat_hw_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -151,7 +150,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -225,7 +224,7 @@ int misc_init_r(void) { char *str; char buf[32]; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* * Normally the processor clock has a divisor of 2. @@ -246,24 +245,28 @@ int misc_init_r(void) } #endif /* CONFIG_MISC_INIT_R */ -int board_init(void) +int board_early_init_f(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - /* Peripheral Clock Enable Register */ - writel(1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_UHP, + /* enable all clocks */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP), &pmc->pcer); + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index a27b36b378..e100cb41ce 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -3,7 +3,7 @@ * Stelian Pop * Lead Tech Design * - * (C) Copyright 2009-2010 + * (C) Copyright 2009-2011 * Daniel Gorsulowski * esd electronic system design gmbh * @@ -31,49 +31,68 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Common stuff */ -#define CONFIG_MEESC 1 /* Board is esd MEESC */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x20002000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ -#define CONFIG_DISPLAY_BOARDINFO 1 -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SERIAL_TAG 1 -#define CONFIG_REVISION_TAG 1 + +/* Misc CPU related */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ #undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MISC_INIT_R /* Call misc_init_r */ - -#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */ +#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ +#define CONFIG_PREBOOT /* enable preboot variable */ /* * Hardware drivers */ -/* Console output */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* Console output */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -84,97 +103,112 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* LED */ -#define CONFIG_AT91_LED 1 +#define CONFIG_AT91_LED -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x02000000 + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ -#define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) +#ifdef CONFIG_SYS_USE_DATAFLASH +# define CONFIG_ATMEL_DATAFLASH_SPI +# define CONFIG_HAS_DATAFLASH +# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +# define AT91_SPI_CLK 15000000 +# define DATAFLASH_TCSS (0x1a << 16) +# define DATAFLASH_TCHS (0x1 << 24) +#endif /* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +# define CONFIG_NAND_ATMEL +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ +# define CONFIG_SYS_NAND_DBW_8 +# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +# define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_FIT #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x21e00000 - -#define CONFIG_SYS_USE_DATAFLASH 1 -#undef CONFIG_SYS_USE_NANDFLASH /* CAN */ -#define CONFIG_AT91_CAN 1 +#define CONFIG_AT91_CAN /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CONFIG_ET1100_BASE 0x70000000 + +#ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ +# define CONFIG_ENV_IS_IN_DATAFLASH +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ +# define CONFIG_ENV_OFFSET 0x4200 +# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 +# define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +# define CONFIG_ENV_IS_IN_NAND 1 +# define CONFIG_ENV_OFFSET 0xC0000 +# define CONFIG_ENV_SIZE 0x20000 + +#endif #define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool @@ -185,7 +219,7 @@ #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported +# error CONFIG_USE_IRQ not supported #endif #endif From 6785c7c84ad6803587b247f363fe977d3e0775fb Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 4 Aug 2011 02:22:20 +0000 Subject: [PATCH 002/145] sbc35_a9g20: update board to the new AT91 organization Cc: Albin Tonnerre Cc: Gregory Hermant Signed-off-by: Thomas Petazzoni Signed-off-by: Reinhard Meyer Removed SBC35 from MAKEALL --- MAKEALL | 1 - Makefile | 7 --- board/calao/sbc35_a9g20/sbc35_a9g20.c | 88 ++++++++++++++------------- boards.cfg | 2 + include/configs/sbc35_a9g20.h | 87 +++++++++++++------------- 5 files changed, 88 insertions(+), 97 deletions(-) diff --git a/MAKEALL b/MAKEALL index 3b98f03101..0ec668522d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -446,7 +446,6 @@ LIST_ARMV7=" \ LIST_at91="$(boards_by_soc at91)\ at91sam9m10g45ek \ pm9g45 \ - SBC35_A9G20 \ TNY_A9260 \ TNY_A9G20 \ " diff --git a/Makefile b/Makefile index 03d80b7c50..47dc73f9f3 100644 --- a/Makefile +++ b/Makefile @@ -827,13 +827,6 @@ pm9g45_config : unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 -SBC35_A9G20_NANDFLASH_config \ -SBC35_A9G20_EEPROM_config \ -SBC35_A9G20_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91 - TNY_A9G20_NANDFLASH_config \ TNY_A9G20_EEPROM_config \ TNY_A9G20_config \ diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index 9df45c0ea3..5f448d9f50 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -26,15 +26,14 @@ */ #include -#include +#include #include #include #include #include #include #include -#include -#include + #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include #endif @@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void sbc35_a9g20_nand_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void) #ifdef CONFIG_MACB static void sbc35_a9g20_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* * Disable pull-up on: @@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); at91_macb_hw_init(); } @@ -150,9 +154,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); sbc35_a9g20_nand_hw_init(); #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4 | 1 << 5); @@ -166,11 +170,9 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) - return -1; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); #endif return rc; } diff --git a/boards.cfg b/boards.cfg index c253f03deb..89d4c7a590 100644 --- a/boards.cfg +++ b/boards.cfg @@ -102,6 +102,8 @@ at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH +sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 00f4dc9f7c..967a9914a1 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -26,54 +26,49 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY +/* SoC type is defined in boards.cfg */ +#include +#include -#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM) -#define CONFIG_SBC35_A9G20 -#endif - -#define CONFIG_AT91SAM9G20 - -#if defined(CONFIG_SBC35_A9G20_NANDFLASH) +#if defined(CONFIG_SYS_USE_NANDFLASH) #define CONFIG_ENV_IS_IN_NAND #else #define CONFIG_ENV_IS_IN_EEPROM #endif /* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -/* - * Hardware drivers - */ -#define CONFIG_AT91_GPIO 1 +/* GPIO */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO + +/* Serial */ #define CONFIG_ATMEL_USART -#define CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BOOTDELAY 3 /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -86,14 +81,16 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) /* SPI EEPROM */ #define CONFIG_SPI @@ -117,7 +114,7 @@ #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -129,27 +126,27 @@ #define CONFIG_SYS_NO_FLASH 1 /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 -#define CONFIG_MACB_SEARCH_PHY 1 +#define CONFIG_RESET_PHY_R +#define CONFIG_MACB_SEARCH_PHY /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 /* Env in EEPROM, bootstrap + u-boot in NAND*/ @@ -172,8 +169,6 @@ "120M(rootfs),-(other) " \ "rw rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 From 65b0f87a806f849670cbe23e7bbda15314621d70 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 4 Aug 2011 02:48:56 +0000 Subject: [PATCH 003/145] tny_a9260/tny_a9g20: update board to the new AT91 organization Cc: Albin Tonnerre CC: Gregory Hermant Signed-off-by: Thomas Petazzoni --- MAKEALL | 2 - Makefile | 10 ---- board/calao/tny_a9260/tny_a9260.c | 55 ++++++++++--------- boards.cfg | 4 ++ include/configs/tny_a9260.h | 89 +++++++++++++++---------------- 5 files changed, 75 insertions(+), 85 deletions(-) diff --git a/MAKEALL b/MAKEALL index 0ec668522d..7e748d60f9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -446,8 +446,6 @@ LIST_ARMV7=" \ LIST_at91="$(boards_by_soc at91)\ at91sam9m10g45ek \ pm9g45 \ - TNY_A9260 \ - TNY_A9G20 \ " ######################################################################### diff --git a/Makefile b/Makefile index 47dc73f9f3..f478ec6053 100644 --- a/Makefile +++ b/Makefile @@ -827,16 +827,6 @@ pm9g45_config : unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 -TNY_A9G20_NANDFLASH_config \ -TNY_A9G20_EEPROM_config \ -TNY_A9G20_config \ -TNY_A9260_NANDFLASH_config \ -TNY_A9260_EEPROM_config \ -TNY_A9260_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91 - ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index d51ca150cc..ab51a335a0 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -26,14 +26,12 @@ */ #include -#include #include #include #include #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -45,33 +43,36 @@ DECLARE_GLOBAL_DATA_PTR; static void tny_a9260_nand_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -91,9 +92,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); tny_a9260_nand_hw_init(); at91_spi0_hw_init(1 << 5); return 0; @@ -101,10 +102,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) - return -1; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/boards.cfg b/boards.cfg index 89d4c7a590..6e9ab9b1a9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -104,6 +104,10 @@ snapper9260 arm arm926ejs - bluewat snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM +tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH +tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM +tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH +tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 7b18022c6e..986aebaae4 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -30,19 +30,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - -#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM) -#define CONFIG_TNY_A9260 -#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM) -#define CONFIG_TNY_A9G20 -#endif - -#ifdef CONFIG_TNY_A9260 -#define CONFIG_AT91SAM9260 -#else -#define CONFIG_AT91SAM9G20 -#endif +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH) #define CONFIG_ENV_IS_IN_NAND @@ -50,29 +42,36 @@ #define CONFIG_ENV_IS_IN_EEPROM #endif -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +/* Define actual evaluation board type from used processor type */ +#ifdef CONFIG_AT91SAM9G20 +# define CONFIG_TNY_A9G20 +#else +# define CONFIG_TNY_A9260 +#endif + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BOOTDELAY 3 @@ -86,13 +85,16 @@ #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) /* SPI EEPROM */ #define CONFIG_SPI @@ -109,8 +111,8 @@ #define CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -119,27 +121,27 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 /* Env in EEPROM, bootstrap + u-boot in NAND*/ #ifdef CONFIG_ENV_IS_IN_EEPROM #define CONFIG_ENV_OFFSET 0x20 -#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SIZE 0x1000 #endif /* Env, bootstrap and u-boot in NAND */ #ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 #endif #define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" @@ -149,15 +151,12 @@ "120M(rootfs),-(other) " \ "rw rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool From f47316a8ba3e83e136be33a7610cbdd0a8ca7990 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 26 Jul 2011 04:48:41 +0000 Subject: [PATCH 004/145] pm9261: compiles with the AT91 reworked scheme Signed-off-by: Asen Chavdarov Dimov --- board/ronetix/pm9261/led.c | 9 ++++----- board/ronetix/pm9261/pm9261.c | 38 +++++++++++++++++------------------ boards.cfg | 2 +- include/configs/pm9261.h | 18 +++++++++-------- 4 files changed, 33 insertions(+), 34 deletions(-) diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index ff21ce667b..f65987035d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -24,17 +24,16 @@ */ #include -#include #include -#include -#include +#include +#include void coloured_LED_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); at91_set_pio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 2c50fe8e6e..871b94ada7 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -26,17 +26,15 @@ #include #include -#include +#include #include #include #include #include #include -#include #include -#include -#include -#include +#include + #include #include #include @@ -56,9 +54,9 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9261_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; @@ -86,8 +84,8 @@ static void pm9261_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << AT91SAM9261_ID_PIOA | - 1 << AT91SAM9261_ID_PIOC, + writel(1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ @@ -105,8 +103,8 @@ static void pm9261_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void pm9261_dm9000_hw_init(void) { - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Configure SMC CS2 for DM9000 */ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | @@ -127,7 +125,7 @@ static void pm9261_dm9000_hw_init(void) &smc->cs[2].mode); /* Configure Interrupt pin as input, no pull-up */ - writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer); + writel(1 << ATMEL_ID_PIOA, &pmc->pcer); at91_set_pio_input(AT91_PIO_PORTA, 24, 0); } #endif @@ -147,7 +145,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -162,7 +160,7 @@ void lcd_disable(void) static void pm9261_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ @@ -189,7 +187,7 @@ static void pm9261_lcd_hw_init(void) writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ - gd->fb_base = AT91SAM9261_SRAM_BASE; + gd->fb_base = ATMEL_BASE_SRAM; } #ifdef CONFIG_LCD_INFO @@ -241,13 +239,13 @@ void lcd_show_board_info(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel(1 << AT91SAM9261_ID_PIOA | - 1 << AT91SAM9261_ID_PIOC, + writel(1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOC, &pmc->pcer); /* arch number of PM9261-Board */ @@ -256,7 +254,7 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9261_nand_hw_init(); #endif diff --git a/boards.cfg b/boards.cfg index 6e9ab9b1a9..c3d72eb578 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,7 +122,7 @@ meesc arm arm926ejs meesc esd meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH -pm9261 arm arm926ejs - ronetix at91 +pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 pm9263 arm arm926ejs - ronetix at91 da830evm arm arm926ejs da8xxevm davinci davinci da850evm arm arm926ejs da8xxevm davinci davinci diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 26e50490f7..3a8b095f01 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,25 +28,29 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ + +#include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_AT91FAMILY /* clocks */ /* CKGR_MOR - enable main osc. */ @@ -160,10 +164,8 @@ */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define CONFIG_LCD 1 From 58fb6020c15580365e441ab3a7b8cc6aa787269d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 4 Aug 2011 08:53:29 +0000 Subject: [PATCH 005/145] atmel: update at91sam9m10g45 SoC support to new style Based on earlier work by Alex Waterman . Signed-off-by: Thomas Petazzoni --- .../arm926ejs/at91/at91sam9m10g45_devices.c | 114 +++++----- arch/arm/include/asm/arch-at91/at91sam9g45.h | 12 ++ .../asm/arch-at91/at91sam9g45_matrix.h | 194 ++++++------------ 3 files changed, 135 insertions(+), 185 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 4ad9b1fcc9..5ff32e3749 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -26,135 +26,131 @@ #include #include #include -#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ - writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ - writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ - writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} - -#ifdef CONFIG_ATMEL_SPI +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); + at91_set_a_periph(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTB, 18, 0); + at91_set_b_periph(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTB, 19, 0); + at91_set_b_periph(AT91_PIO_PORTB, 19, 1); } if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTD, 27, 0); + at91_set_b_periph(AT91_PIO_PORTD, 27, 1); } if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 3, 0); + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTB, 18, 0); + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTB, 19, 0); + at91_set_pio_output(AT91_PIO_PORTB, 19, 1); } if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 27, 0); + at91_set_pio_output(AT91_PIO_PORTD, 27, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTD, 28, 0); + at91_set_b_periph(AT91_PIO_PORTD, 28, 1); } if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTD, 18, 0); + at91_set_a_periph(AT91_PIO_PORTD, 18, 1); } if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTD, 19, 0); + at91_set_a_periph(AT91_PIO_PORTD, 19, 1); } if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 17, 0); + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTD, 28, 0); + at91_set_pio_output(AT91_PIO_PORTD, 28, 1); } if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTD, 18, 0); + at91_set_pio_output(AT91_PIO_PORTD, 18, 1); } if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 19, 0); + at91_set_pio_output(AT91_PIO_PORTD, 19, 1); } } diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 364b86c88f..4df6b090b8 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -128,6 +128,18 @@ #define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ #define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h index 1620e1baff..01c9c636e1 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h @@ -15,139 +15,81 @@ #ifndef AT91SAM9G45_MATRIX_H #define AT91SAM9G45_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +struct at91_matrix { + u32 mcfg[16]; + u32 scfg[16]; + u32 pras[16][2]; + u32 mrcr; /* 0x100 Master Remap Control */ + u32 filler[3]; + u32 tcmr; + u32 filler2; + u32 ddrmpr; + u32 filler3[3]; + u32 ebicsa; + u32 filler4[47]; + u32 wpmr; + u32 wpsr; +}; -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0) -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) -#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 +#define AT91_MATRIX_M6PR_SHIFT 24 +#define AT91_MATRIX_M7PR_SHIFT 28 -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) +#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ +#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ +#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ +#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ +#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) #endif From 684a567ace2bc5673d52b2cb4f517909f5481153 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Wed, 8 Jun 2011 22:01:16 +0000 Subject: [PATCH 006/145] make pm9263 buildable for v2011.06 release Signed-off-by: Asen Chavdarov Dimov --- board/ronetix/pm9263/led.c | 9 ++++---- board/ronetix/pm9263/pm9263.c | 42 +++++++++++++++++------------------ boards.cfg | 2 +- include/configs/pm9263.h | 17 ++++++++------ 4 files changed, 35 insertions(+), 35 deletions(-) diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index 4e585a4751..d6eb69f04a 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -24,17 +24,16 @@ */ #include -#include #include -#include -#include +#include +#include void coloured_LED_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer); + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); at91_set_pio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 8071600081..cfc9847ccc 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -26,16 +26,14 @@ #include #include -#include +#include #include #include #include #include #include -#include #include -#include -#include +#include #include #include #include @@ -55,8 +53,8 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9263_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -95,7 +93,7 @@ static void pm9263_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9263_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* * PB27 enables the 50MHz oscillator for Ethernet PHY @@ -106,7 +104,7 @@ static void pm9263_macb_hw_init(void) at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -145,7 +143,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9263_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -168,8 +166,8 @@ static int pm9263_lcd_hw_psram_init(void) { volatile uint16_t x; unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; /* Enable CS3 3.3v, no pull-ups */ csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | @@ -249,7 +247,7 @@ static int pm9263_lcd_hw_psram_init(void) static void pm9263_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ @@ -275,7 +273,7 @@ static void pm9263_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); /* Power Control */ at91_set_pio_output(AT91_PIO_PORTA, 22, 1); @@ -285,9 +283,9 @@ static void pm9263_lcd_hw_init(void) /* initialize te PSRAM */ int stat = pm9263_lcd_hw_psram_init(); - gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; + gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; #else - gd->fb_base = AT91SAM9263_SRAM0_BASE; + gd->fb_base = ATMEL_BASE_SRAM0; #endif } @@ -341,14 +339,14 @@ void lcd_show_board_info(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel((1 << AT91SAM9263_ID_PIOA) | - (1 << AT91SAM9263_ID_PIOCDE) | - (1 << AT91SAM9263_ID_PIOB), + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOCDE) | + (1 << ATMEL_ID_PIOB), &pmc->pcer); /* arch number of AT91SAM9263EK-Board */ @@ -357,7 +355,7 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9263_nand_hw_init(); #endif @@ -400,7 +398,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); #endif return rc; } @@ -417,7 +415,7 @@ int checkboard (void) ss = "(PSRAM)"; break; - case AT91SAM9263_SRAM0_BASE: + case ATMEL_BASE_SRAM0: ss = "(Internal SRAM)"; break; diff --git a/boards.cfg b/boards.cfg index c3d72eb578..716435466e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -123,7 +123,7 @@ meesc_dataflash arm arm926ejs meesc esd otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 -pm9263 arm arm926ejs - ronetix at91 +pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 da830evm arm arm926ejs da8xxevm davinci davinci da850evm arm arm926ejs da8xxevm davinci davinci hawkboard arm arm926ejs da8xxevm davinci davinci diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 96e12f24ce..1e282d2016 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,6 +28,12 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -36,16 +42,15 @@ #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_AT91FAMILY /* clocks */ #define CONFIG_SYS_MOR_VAL \ @@ -170,10 +175,8 @@ */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define CONFIG_LCD 1 From eb6e608b32b92fad645979894c71ffd15b4cb20a Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Wed, 8 Jun 2011 22:01:37 +0000 Subject: [PATCH 007/145] make pm9g45 buildable for v2011.06 release Signed-off-by: Asen Chavdarov Dimov Signed-off-by: Reinhard Meyer changed at91_serial_hw_init to at91_seriald_hw_init --- MAKEALL | 1 - Makefile | 4 ---- board/ronetix/pm9g45/pm9g45.c | 32 +++++++++++++++----------------- boards.cfg | 1 + include/configs/pm9g45.h | 16 +++++++++++----- 5 files changed, 27 insertions(+), 27 deletions(-) diff --git a/MAKEALL b/MAKEALL index 7e748d60f9..dd6b1fc04b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -445,7 +445,6 @@ LIST_ARMV7=" \ LIST_at91="$(boards_by_soc at91)\ at91sam9m10g45ek \ - pm9g45 \ " ######################################################################### diff --git a/Makefile b/Makefile index f478ec6053..b71022cf55 100644 --- a/Makefile +++ b/Makefile @@ -823,10 +823,6 @@ at91sam9g45ekes_config : unconfig fi; @$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 -pm9g45_config : unconfig - @mkdir -p $(obj)include - @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 - ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index fa69599e90..f3374a4429 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -29,16 +29,14 @@ #include #include -#include +#include #include #include #include #include #include -#include +#include #include -#include -#include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include #endif @@ -54,9 +52,9 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9g45_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -80,7 +78,7 @@ static void pm9g45_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); #ifdef CONFIG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ @@ -95,7 +93,7 @@ static void pm9g45_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9g45_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* * PD2 enables the 50MHz oscillator for Ethernet PHY @@ -106,7 +104,7 @@ static void pm9g45_macb_hw_init(void) at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -131,22 +129,22 @@ static void pm9g45_macb_hw_init(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel((1 << AT91SAM9G45_ID_PIOA) | - (1 << AT91SAM9G45_ID_PIOB) | - (1 << AT91SAM9G45_ID_PIOC) | - (1 << AT91SAM9G45_ID_PIODE), &pmc->pcer); + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC) | + (1 << ATMEL_ID_PIODE), &pmc->pcer); /* arch number of AT91SAM9M10G45EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9g45_nand_hw_init(); #endif @@ -188,7 +186,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); #endif return rc; } diff --git a/boards.cfg b/boards.cfg index 716435466e..48b7592962 100644 --- a/boards.cfg +++ b/boards.cfg @@ -124,6 +124,7 @@ otc570 arm arm926ejs otc570 esd otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 +pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 da830evm arm arm926ejs da8xxevm davinci davinci da850evm arm arm926ejs da8xxevm davinci davinci hawkboard arm arm926ejs da8xxevm davinci davinci diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index ec51ccf062..672f66345a 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -32,15 +32,20 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include + #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_TEXT_BASE 0x73f00000 -#define CONFIG_AT91FAMILY +#define CONFIG_SYS_TEXT_BASE 0x73f00000 #define CONFIG_ARCH_CPU_INIT @@ -55,7 +60,8 @@ */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_SYS_USE_NANDFLASH 1 From 55d11d22ca08fdff59a9716f942e161e0bd614f6 Mon Sep 17 00:00:00 2001 From: Reinhard Meyer Date: Thu, 4 Aug 2011 20:56:11 +0000 Subject: [PATCH 008/145] AT91: fix at91sam9g45.h to include USB Host defines Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9g45.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 4df6b090b8..1aeedc04a1 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -144,7 +144,9 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ - +#define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_ID_UHP ATMEL_ID_UHPHS /* * Cpu Name */ From 5cfeec5125a1946da7d5f25576ea686047848182 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 4 Aug 2011 11:08:50 +0000 Subject: [PATCH 009/145] atmel: Update support of board AT91SAM9M10G45-EK to new style Based on earlier work by Alex Waterman . Signed-off-by: Thomas Petazzoni --- MAKEALL | 4 +- Makefile | 25 --- .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 117 ++++++----- board/atmel/at91sam9m10g45ek/led.c | 6 +- boards.cfg | 1 + include/configs/at91sam9m10g45ek.h | 185 ++++++++---------- 6 files changed, 153 insertions(+), 185 deletions(-) diff --git a/MAKEALL b/MAKEALL index dd6b1fc04b..69a9ed9f41 100755 --- a/MAKEALL +++ b/MAKEALL @@ -443,9 +443,7 @@ LIST_ARMV7=" \ ## AT91 Systems ######################################################################### -LIST_at91="$(boards_by_soc at91)\ - at91sam9m10g45ek \ -" +LIST_at91="$(boards_by_soc at91)" ######################################################################### ## Xscale Systems diff --git a/Makefile b/Makefile index b71022cf55..553382fa10 100644 --- a/Makefile +++ b/Makefile @@ -798,31 +798,6 @@ M5485HFE_config : unconfig # ARM #======================================================================== -######################################################################### -## ARM926EJ-S Systems -######################################################################### - -at91sam9m10g45ek_nandflash_config \ -at91sam9m10g45ek_dataflash_config \ -at91sam9m10g45ek_dataflash_cs0_config \ -at91sam9m10g45ek_config \ -at91sam9g45ekes_nandflash_config \ -at91sam9g45ekes_dataflash_config \ -at91sam9g45ekes_dataflash_cs0_config \ -at91sam9g45ekes_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9m10,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 - ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index f92b20f4a8..24a86063bf 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -23,17 +23,14 @@ */ #include -#include -#include -#include +#include +#include #include #include #include #include -#include #include -#include -#include +#include #include #include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; */ #ifdef CONFIG_CMD_NAND -static void at91sam9m10g45ek_nand_hw_init(void) +void at91sam9m10g45ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(3)); + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) #ifdef CONFIG_MACB static void at91sam9m10g45ek_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); + /* And the pins. */ at91_macb_hw_init(); } #endif @@ -161,7 +166,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:40, vl_lower_margin:1, - mmio: AT91SAM9G45_LCDC_BASE, + mmio : ATMEL_BASE_LCDC, }; @@ -177,6 +182,8 @@ void lcd_disable(void) static void at91sam9m10g45ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } @@ -227,7 +234,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -243,6 +250,12 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + int board_init(void) { /* Enable Ctrlc */ @@ -254,10 +267,10 @@ int board_init(void) #elif defined CONFIG_AT91SAM9G45EKES gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; #endif - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); #endif @@ -270,11 +283,9 @@ int board_init(void) #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4); #endif - #ifdef CONFIG_MACB at91sam9m10g45ek_macb_hw_init(); #endif - #ifdef CONFIG_LCD at91sam9m10g45ek_lcd_hw_init(); #endif @@ -283,8 +294,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -298,7 +309,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index ff59a2d5d3..dadbd6a761 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -23,15 +23,17 @@ */ #include +#include #include #include #include -#include void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/boards.cfg b/boards.cfg index 48b7592962..6a9d51eca5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -95,6 +95,7 @@ at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 +at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index de74dcf18b..b08cbf2345 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -27,48 +27,60 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#ifdef CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ -#else -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ -#endif +#define CONFIG_AT91SAM9M10G45EK +#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS /* - * Hardware drivers + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define ATMEL_ID_UHP ATMEL_ID_UHPHS + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* LCD */ -#define CONFIG_LCD 1 +#define CONFIG_LCD #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_RGB565 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* board specific(not enough SRAM) */ #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 @@ -82,10 +94,10 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -98,44 +110,29 @@ #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x70000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -/* DataFlash */ -#ifdef CONFIG_ATMEL_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH 1 -#define CONFIG_SPI_FLASH_ATMEL 1 -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#endif +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -/* NOR flash, if populated */ -#ifndef CONFIG_CMD_NAND -#define CONFIG_SYS_NO_FLASH 1 -#else -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -146,68 +143,52 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_STORAGE -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 " \ - "mtdparts=atmel_nand:-(root) "\ - "rw rootfstype=jffs2" - -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro, \ - 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ - 2M(linux),-(root) " \ - "rw rootfstype=jffs2" +#define CONFIG_ENV_SIZE 0x20000 -#endif +#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ + "bootm 0x70000000" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mtdblock5 " \ + "mtdparts=atmel_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ + "2M@1M(linux),-(root) " \ + "rw rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " From f37586bb14a338c03f6085b8b3ceec5f6d9e9313 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Fri, 5 Aug 2011 20:48:32 +0000 Subject: [PATCH 010/145] MAKEALL ARMv7: Use boards.cfg Use the boards from boards.cfg for building ./MAKEALL ARMV7. Signed-off-by: Dirk Behme --- MAKEALL | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/MAKEALL b/MAKEALL index 69a9ed9f41..0cb51f7861 100755 --- a/MAKEALL +++ b/MAKEALL @@ -417,27 +417,8 @@ LIST_ARM11=" \ ######################################################################### ## ARMV7 Systems ######################################################################### -LIST_ARMV7=" \ - am3517_crane \ - am3517_evm \ - ca9x4_ct_vxp \ - devkit8000 \ - dig297 \ - igep0020 \ - igep0030 \ - mx51evk \ - omap3_beagle \ - omap3_overo \ - omap3_evm \ - omap3_pandora \ - omap3_sdp3430 \ - omap3_zoom1 \ - omap3_zoom2 \ - omap4_panda \ - omap4_sdp4430 \ - s5p_goni \ - smdkc100 \ -" + +LIST_ARMV7="$(boards_by_cpu armv7)" ######################################################################### ## AT91 Systems From 221a0666db6fd127f0a82d7e036c7709a9094d19 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sun, 3 Jul 2011 23:00:20 +0000 Subject: [PATCH 011/145] arm: nvidia and smdk6400: use common code for machine type NVIDIA boards and Samsung SMDK6400 already use a local variant of CONFIG_MACH_TYPE option. Switch to use the new common code. Signed-off-by: Igor Grinberg --- board/nvidia/common/board.c | 2 -- board/samsung/smdk6400/smdk6400.c | 1 - include/configs/smdk6400.h | 2 +- 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 8ab94404d1..5eca5eb344 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -318,8 +318,6 @@ int board_init(void) { /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); - /* board id for Linux */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; return 0; } diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 13c7ed5189..c40d1f9b49 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -72,7 +72,6 @@ int board_init(void) /* Enable WAIT */ SROM_BW_REG |= 4 | 8 | 1; - gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index c9acf5815f..d175ed6b36 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -65,7 +65,7 @@ /* * Architecture magic and machine type */ -#define MACH_TYPE 1270 +#define CONFIG_MACH_TYPE 1270 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO From 2141e14428924792d5d0f1770d7c03bdc892208c Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sun, 3 Jul 2011 23:00:21 +0000 Subject: [PATCH 012/145] arm: omap: innovator: use common code for machine type Innovator and H2 boards used machine_is_* macros for setting the machine type. These macros are expanded in compile time and thus leaves unreachable code (though gcc might optimize it). Switch them to use common code for machine type setting. Signed-off-by: Igor Grinberg --- board/ti/omap1610inn/omap1610innovator.c | 7 ------- include/configs/omap1610h2.h | 3 ++- include/configs/omap1610inn.h | 3 ++- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/board/ti/omap1610inn/omap1610innovator.c b/board/ti/omap1610inn/omap1610innovator.c index 44818bbdae..16e823766a 100644 --- a/board/ti/omap1610inn/omap1610innovator.c +++ b/board/ti/omap1610inn/omap1610innovator.c @@ -63,13 +63,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - if (machine_is_omap_h2()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; - else if (machine_is_omap_innovator()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; - else - gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h index cb2a07f65a..9fa33172f7 100644 --- a/include/configs/omap1610h2.h +++ b/include/configs/omap1610h2.h @@ -34,7 +34,8 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP1610 1 /* which is in a 1610 */ #define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ -#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */ + +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2 /* input clock of PLL */ /* the OMAP1610 H2 has 12MHz input clock */ diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h index e82b4b258f..e3f3487ce2 100644 --- a/include/configs/omap1610inn.h +++ b/include/configs/omap1610inn.h @@ -34,7 +34,8 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP1610 1 /* which is in a 1610 */ #define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ -#define CONFIG_MACH_OMAP_INNOVATOR /* Select board mach-type */ + +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR /* input clock of PLL */ /* the OMAP1610 Innovator has 12MHz input clock */ From 34fe8281d7323784544e94d2f7218f52b8a2899d Mon Sep 17 00:00:00 2001 From: Matthias Weisser Date: Sun, 22 May 2011 23:06:50 +0000 Subject: [PATCH 013/145] arm: lib: memcpy: Do not copy to same address In some cases (e.g. bootm with a elf payload which is already at the right position) there is a in place copy of data to the same address. Catching this saves some ms while booting. Signed-off-by: Matthias Weisser --- arch/arm/lib/memcpy.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 3b5aeec4cf..f655256b5d 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -60,6 +60,9 @@ .globl memcpy memcpy: + cmp r0, r1 + moveq pc, lr + enter r4, lr subs r2, r2, #4 From a46877cc472230fddfe56f2dfd26017b28f4bba9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:49:36 +0000 Subject: [PATCH 014/145] integratorap: make the compile work again The integratorap/cp config for u-boot was outdated and would not even compile, so fix the obvious missing bits for it to start building. After this "make ap920t_config/make all" starts working again. Signed-off-by: Linus Walleij --- board/armltd/integrator/lowlevel_init.S | 2 +- include/configs/integratorap.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index ab9589c95c..6f55bb548c 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -199,7 +199,7 @@ cm_remap: /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ + ldr r2, =_TEXT_BASE /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 32ff1932c6..8b41885fed 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -120,6 +120,12 @@ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_FLASH_BASE 0x24000000 From 26c82638c92f1b21216df5852788280d81b45fe5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:50:08 +0000 Subject: [PATCH 015/145] integratorap: support relocation The integrator board was apparently never converted over to support relocation until now. After this the integrator u-boot both compiles and boots on the Integrator AP. This also fixes the SDRAM memory size detection. Signed-off-by: Linus Walleij --- board/armltd/integrator/integrator.c | 15 +++++++-------- include/configs/integratorap.h | 2 +- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 9bb56b5208..c8d2bc7bac 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -86,15 +86,9 @@ int misc_init_r (void) return (0); } -/****************************** - Routine: - Description: -******************************/ int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -118,8 +112,13 @@ extern void dram_query(void); */ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + 0x01000000 << sdram_shift); } +#else + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ return 0; diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 8b41885fed..1650c03e36 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -47,7 +47,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CM_INIT 1 #define CONFIG_CM_REMAP 1 -#undef CONFIG_CM_SPD_DETECT +#define CONFIG_CM_SPD_DETECT /* * Size of malloc() pool From e005754bf4af26c2639c3ebdcfea8d1c61474bb0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:50:47 +0000 Subject: [PATCH 016/145] integratorap: support the hush shell Give us some kind of sane shell environment so the bootloader can be used. Signed-off-by: Linus Walleij --- include/configs/integratorap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 1650c03e36..2754f67305 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -94,7 +94,9 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "# " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) From c53e4b74f71e35bf48da2f93864941a4c4f21adb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:51:08 +0000 Subject: [PATCH 017/145] integratorap: support some rudimentary commands This adds support for a subset of the default commands for the Integrator, however since the card does not have Ethernet (unless you plug in a PCI card) we can not use the default command set. Signed-off-by: Linus Walleij --- include/configs/integratorap.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2754f67305..90f21e879b 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -81,9 +81,15 @@ * Command line configuration. */ + #define CONFIG_CMD_IMI #define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD #define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS #define CONFIG_BOOTDELAY 2 From bc87d7641948ba49e1b9a4a3ce2cb2f922b77599 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:51:37 +0000 Subject: [PATCH 018/145] integratorap: remove hardcoded 32MB memory cmdline The default configuration for the Integrator AP forces memory to be 32 MB on the command line to the kernel, while we have perfect information and detection of the actual memory size in the ATAGs. Delete the confusion. Signed-off-by: Linus Walleij --- include/configs/integratorap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 90f21e879b..2318ad3849 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -93,7 +93,7 @@ #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" #define CONFIG_BOOTCOMMAND "" /* From 9ecefbfe26acff51cfb670b6716e0f68bfc90db4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 25 Jul 2011 01:52:00 +0000 Subject: [PATCH 019/145] integratorcp: make the board compile This defines the requires CONFIG_SYS_* variables to make the Integrator CP board compile. Signed-off-by: Linus Walleij --- include/configs/integratorcp.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 2c8ca2ddc5..b0486dfccd 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -140,6 +140,12 @@ SIB at Block62 End Block62 address 0x24f80000 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * FLASH and environment organization From 23b3ae0fe8e4ed9fde2fdc73daeaa5392953d11f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 12 Aug 2011 00:28:57 +0000 Subject: [PATCH 020/145] integrator: convert to new build system This deletes the integrator split_by_variant.sh script and defines a number of unique board types for the core modules that are meaningful to support for the Integrator AP/CP, i.e. the ones that did not just say "unsupported core module" in split_by_variant.sh. If more core modules need to be supported they are easy to add. We delete all the old cruft in Makefile and MAKEALL that was working around the old way of building boards. We create a unique config file per board to satisfy the build system, but they are just oneliners that include the existing integratorap.h and integratorcp.h configs. Signed-off-by: Linus Walleij --- MAKEALL | 22 -- Makefile | 27 --- arch/arm/cpu/arm720t/cpu.c | 5 - board/armltd/integrator/split_by_variant.sh | 220 -------------------- boards.cfg | 8 + include/configs/integratorap.h | 3 + include/configs/integratorcp.h | 2 + 7 files changed, 13 insertions(+), 274 deletions(-) delete mode 100755 board/armltd/integrator/split_by_variant.sh diff --git a/MAKEALL b/MAKEALL index 0cb51f7861..26685fbfcc 100755 --- a/MAKEALL +++ b/MAKEALL @@ -301,14 +301,11 @@ LIST_SA="$(boards_by_cpu sa1100)" ######################################################################### LIST_ARM7=" \ - ap7 \ - ap720t \ armadillo \ B2 \ ep7312 \ evb4510 \ impa7 \ - integratorap \ lpc2292sodimm \ modnet50 \ SMN42 \ @@ -320,17 +317,7 @@ LIST_ARM7=" \ LIST_ARM9=" \ a320evb \ - ap920t \ - ap922_XA10 \ - ap926ejs \ - ap946es \ - ap966 \ aspenite \ - cp920t \ - cp922_XA10 \ - cp926ejs \ - cp946es \ - cp966 \ da830evm \ da850evm \ edb9301 \ @@ -388,19 +375,10 @@ LIST_ARM9=" \ davinci_dm6467evm \ " -######################################################################### -## ARM10 Systems -######################################################################### -LIST_ARM10=" \ - integratorcp \ - cp1026 \ -" - ######################################################################### ## ARM11 Systems ######################################################################### LIST_ARM11=" \ - cp1136 \ omap2420h4 \ apollon \ imx31_litekit \ diff --git a/Makefile b/Makefile index 553382fa10..676dc29cfa 100644 --- a/Makefile +++ b/Makefile @@ -798,32 +798,6 @@ M5485HFE_config : unconfig # ARM #======================================================================== -######################################################################## -## ARM Integrator boards - see doc/README-integrator for more info. -integratorap_config \ -ap_config \ -ap966_config \ -ap922_config \ -ap922_XA10_config \ -ap7_config \ -ap720t_config \ -ap920t_config \ -ap926ejs_config \ -ap946es_config: unconfig - @board/armltd/integrator/split_by_variant.sh ap $@ - -integratorcp_config \ -cp_config \ -cp920t_config \ -cp926ejs_config \ -cp946es_config \ -cp1136_config \ -cp966_config \ -cp922_config \ -cp922_XA10_config \ -cp1026_config: unconfig - @board/armltd/integrator/split_by_variant.sh cp $@ - xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1)))) omap1610inn_config \ @@ -970,7 +944,6 @@ clean: $(obj)board/matrix_vision/*/bootscript.img \ $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/voiceblue/eeprom \ - $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ $(obj)u-boot.lds \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ $(obj)arch/blackfin/cpu/init.{lds,elf} diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 88c71bfe18..ff992aac52 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -82,9 +82,4 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific cache setup for IntegratorAP/CM720T as yet */ - void icache_enable (void) - { - } #endif diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh deleted file mode 100755 index 19fc832c2a..0000000000 --- a/board/armltd/integrator/split_by_variant.sh +++ /dev/null @@ -1,220 +0,0 @@ -#!/bin/sh - -mkdir -p ${obj}include -mkdir -p ${obj}board/armltd/integrator - -config_file=${obj}include/config.h - -if [ "$1" = "ap" ] -then -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -cat > ${config_file} << _EOF -/* Integrator configuration implied by Makefile target */ -#define CONFIG_INTEGRATOR /* Integrator board */ -#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */ -_EOF - -# --------------------------------------------------------- -# Set the core module defines according to Core Module -# --------------------------------------------------------- -cpu="arm_intcm" -variant="unknown core module" - -if [ "$2" = "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$2" in - ap7_config) - cpu="arm_intcm" - variant="unported core module CM7TDMI" - ;; - - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorap_config | \ - ap_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - ap720t_config) - cpu="arm720t" - echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \ - >> ${config_file} - variant="Core module CM720T" - ;; - - ap922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ - >> ${config_file} - ;; - - ap920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ - >> ${config_file} - ;; - - ap926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ - >> ${config_file} - ;; - - ap946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ - >> ${config_file} - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac -fi - -case "$cpu" in - arm_intcm) - cat >> ${config_file} << _EOF -/* Core module undefined/not ported */ -#define CONFIG_ARM_INTCM 1 -#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ -#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ -#undef CONFIG_CM_REMAP /* CM may not support remapping */ -#undef CONFIG_CM_INIT /* CM may not have initialization reg */ -#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ -/* May not be processor without cache support */ -#define CONFIG_SYS_ICACHE_OFF 1 -#define CONFIG_SYS_DCACHE_OFF 1 -_EOF - ;; - - arm720t) - cat >> ${config_file} << _EOF -/* May not be processor without cache support */ -#define CONFIG_SYS_ICACHE_OFF 1 -#define CONFIG_SYS_DCACHE_OFF 1 -_EOF - ;; -esac - -else - -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -cat >> ${config_file} << _EOF -/* Integrator configuration implied by Makefile target */ -#define CONFIG_INTEGRATOR /* Integrator board */ -#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */ -_EOF - -cpu="arm_intcm" -variant="unknown core module" - -if [ "$2" = "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$2" in - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorcp_config | \ - cp_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - cp922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ - >> ${config_file} - ;; - - cp920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ - >> ${config_file} - ;; - - cp926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ - >> ${config_file} - ;; - - - cp946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ - >> ${config_file} - ;; - - cp1136_config) - cpu="arm1136" - variant="Core module CM1136EJF-S" - echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \ - >> ${config_file} - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac - -fi - -if [ "$cpu" = "arm_intcm" ] -then - cat >> ${config_file} << _EOF -/* Core module undefined/not ported */ -#define CONFIG_ARM_INTCM 1 -#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ -#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ -#undef CONFIG_CM_REMAP /* CM may not support remapping */ -#undef CONFIG_CM_INIT /* CM may not have initialization reg */ -#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ -_EOF -fi - -fi # ap - -# --------------------------------------------------------- -# Complete the configuration -# --------------------------------------------------------- -$MKCONFIG -a -n "${2%%_config}" integrator$1 arm $cpu integrator armltd -echo "Variant: $variant with core $cpu" diff --git a/boards.cfg b/boards.cfg index 6a9d51eca5..abee8211ea 100644 --- a/boards.cfg +++ b/boards.cfg @@ -35,6 +35,7 @@ # Target ARCH CPU Board name Vendor SoC Options ########################################################################################################### +integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 imx31_litekit arm arm1136 - logicpd mx31 @@ -45,9 +46,12 @@ armadillo arm arm720t ep7312 arm arm720t impa7 arm arm720t modnet50 arm arm720t +integratorap_cm720t arm arm720t integrator armltd - integratorap lpc2292sodimm arm arm720t - - lpc2292 SMN42 arm arm720t - siemens lpc2292 evb4510 arm arm720t - - s3c4510b +integratorap_cm920t arm arm920t integrator armltd - integratorap +integratorcp_cm920t arm arm920t integrator armltd - integratorcp a320evb arm arm920t - faraday a320 at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT @@ -71,6 +75,8 @@ smdk2410 arm arm920t - samsung netstar arm arm925t voiceblue arm arm925t omap1510inn arm arm925t - ti +integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap +integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB @@ -164,6 +170,8 @@ nhk8815_onenand arm arm926ejs nhk8815 st omap5912osk arm arm926ejs - ti omap edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon +integratorap_cm946es arm arm946es integrator armltd - integratorap +integratorcp_cm946es arm arm946es integrator armltd - integratorcp ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2318ad3849..3b983afb69 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -30,6 +30,9 @@ #ifndef __CONFIG_H #define __CONFIG_H + +#define CONFIG_INTEGRATOR +#define CONFIG_ARCH_INTEGRATOR /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index b0486dfccd..e9b68c6918 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -31,6 +31,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_INTEGRATOR +#define CONFIG_ARCH_INTEGRATOR /* * High Level Configuration Options * (easy to change) From d321b64d64757faa863f45aae18d261253d8ee36 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 28 Jul 2011 19:28:13 +0200 Subject: [PATCH 021/145] MX31: removed warnings due to clock.h Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index fb035c4993..b132676460 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -32,7 +32,7 @@ enum mxc_clock { }; unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(); +extern u32 imx_get_uartclk(void); extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); From 8b5a4bcaa06edc7161fa380a674a891ea0631645 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Wed, 3 Aug 2011 00:05:47 +0000 Subject: [PATCH 022/145] mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF CONFIG_L2_OFF is obsolete after the following commit: e47f2db5371047eb9bcd115fee084e6a8a92a239 armv7: rename cache related CONFIG flags Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF Since imx5 does not provide L2 cache operations(Enable/Disable) Simply remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF Signed-off-by: Jason Liu Cc:Stefano Babic Acked-by: Stefano Babic --- include/configs/efikamx.h | 2 -- include/configs/mx51evk.h | 2 -- include/configs/mx53ard.h | 2 -- include/configs/mx53evk.h | 2 -- include/configs/mx53loco.h | 2 -- include/configs/mx53smd.h | 2 -- include/configs/vision2.h | 1 - 7 files changed, 13 deletions(-) diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index 7d3363aa79..b90e34299f 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -40,8 +40,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_SYS_L2CACHE_OFF - /* * Bootloader Components Configuration */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index fd42afcedc..3f2aca1bf3 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_SYS_L2CACHE_OFF - #include /* * Disabled for now due to build problems under Debian and a significant diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index c872510679..c0b8d6a61a 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -29,8 +29,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF - #include #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 5f5403558f..7fb1d9aa75 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -29,8 +29,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_SYS_L2CACHE_OFF - #include #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 544e3fbbdf..cfb38a5673 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -30,8 +30,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF - #include #define CONFIG_CMDLINE_TAG diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 65d5e05504..49f8c6e8e7 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -29,8 +29,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF - #include #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 50c920d0b8..b5c73571b3 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -26,7 +26,6 @@ #define CONFIG_MX51 /* in a mx51 */ -#define CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_TEXT_BASE 0x97800000 #include From b2b8f98f885c61f64aacaeb8fc4d247fbb3ae8cd Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 2 Jun 2011 22:11:37 +0000 Subject: [PATCH 023/145] arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize Signed-off-by: Heiko Schocher cc: Albert Aribaud --- arch/arm/lib/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 14a56f6f0a..646cf450f7 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -626,7 +626,7 @@ void board_init_r(gd_t *id, ulong dest_addr) pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif - sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram); setenv("mem", (char *)memsz); } #endif From 15c2e2c0ea64a0ab10b6765e2b0ab46d99d9ac34 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 16 Aug 2011 23:48:23 +0000 Subject: [PATCH 024/145] arm: fix bd pointer dereference prior initialization gd->bd pointer has been used prior been initialized. Move the relevant code after the initialization. Signed-off-by: Igor Grinberg --- arch/arm/lib/board.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 646cf450f7..c899839852 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -275,10 +275,6 @@ void board_init_f(ulong bootflag) gd->mon_len = _bss_end_ofs; -#ifdef CONFIG_MACH_TYPE - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ -#endif - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); @@ -376,6 +372,11 @@ void board_init_f(ulong bootflag) gd->bd = bd; debug("Reserving %zu Bytes for Board Info at: %08lx\n", sizeof (bd_t), addr_sp); + +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + addr_sp -= sizeof (gd_t); id = (gd_t *) addr_sp; debug("Reserving %zu Bytes for Global Data at: %08lx\n", From 34d34b88b6b3d947de86dae81574bdde85b8d01e Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 11 Jul 2011 08:49:18 +0000 Subject: [PATCH 025/145] SMDKV310: Fix host compilation of mkv310_image Fix compilation of mkv310_image host tool tools/mkv310_image.c: In function 'main': tools/mkv310_image.c:67: error: 'S_IRUSR' undeclared (first use in this function) tools/mkv310_image.c:67: error: (Each undeclared identifier is reported only once tools/mkv310_image.c:67: error: for each function it appears in.) tools/mkv310_image.c:67: error: 'S_IWUSR' undeclared (first use in this function) tools/mkv310_image.c:67: error: 'S_IRGRP' undeclared (first use in this function) tools/mkv310_image.c:67: error: 'S_IWGRP' undeclared (first use in this function) tools/mkv310_image.c:67: error: 'S_IROTH' undeclared (first use in this function) tools/mkv310_image.c:67: error: 'S_IWOTH' undeclared (first use in this function) resulting from a 'make smdkv310_config'. Signed-off-by: Dirk Behme Signed-off-by: Minkyu Kang --- mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c | 1 + 1 file changed, 1 insertion(+) diff --git a/mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c b/mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c index b98f23390f..1a51913f59 100644 --- a/mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c +++ b/mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c @@ -26,6 +26,7 @@ #include #include #include +#include #define CHECKSUM_OFFSET (14*1024-4) #define BUFSIZE (16*1024) From 9070872bb343e07945bf3882c572da82901c637d Mon Sep 17 00:00:00 2001 From: Anton Staaf Date: Thu, 30 Jun 2011 09:55:08 +0000 Subject: [PATCH 026/145] mmc: S5P: Support DMA restarts at buffer boundaries Currently if a DMA buffer straddles a buffer alignment boundary (512KiB) then the DMA engine will pause and generate a DMA interrupt. Since the DMA interrupt is not enabled it will hang the MMC driver. This patch adds support for restarting the DMA transfer. The SYSTEM_ADDRESS register contains the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf Signed-off-by: Minkyu Kang Tested-by : Jaehoon Chung Cc: Albert ARIBAUD --- drivers/mmc/s5p_mmc.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index f1368132a3..7786ecf2be 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -232,9 +232,15 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, __func__, mask); return -1; } else if (mask & (1 << 3)) { - /* DMA Interrupt */ + /* + * DMA Interrupt, restart the transfer where + * it was interrupted. + */ + unsigned int address = readl(&host->reg->sysad); + debug("DMA end\n"); - break; + writel((1 << 3), &host->reg->norintsts); + writel(address, &host->reg->sysad); } else if (mask & (1 << 1)) { /* Transfer Complete */ debug("r/w is done\n"); @@ -425,12 +431,13 @@ static int mmc_core_init(struct mmc *mmc) * NORMAL Interrupt Status Enable Register init * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable + * [3] ENSTADMAINT : DMA Interrupt Status Enable * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable * [0] ENSTACMDCMPLT : Command Complete Status Enable - */ + */ mask = readl(&host->reg->norintstsen); mask &= ~(0xffff); - mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0); + mask |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1) | (1 << 0); writel(mask, &host->reg->norintstsen); /* From ef5d9eb925cd1f5e13c1c3d940932b182e06446d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Fri, 15 Jul 2011 00:16:22 +0000 Subject: [PATCH 027/145] gpio:samsung s5p_ suffix add for GPIO functions This change is driven by need of general gpio_* functions, which as their parameter are accepting the GPIO pin number, NOT block and pin. This makes the code alike to omap, and allows for using more generic frameworks (e.g. software I2C). Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang Acked-by: Mike Frysinger --- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 16 ++++++++-------- arch/arm/include/asm/arch-s5pc2xx/gpio.h | 16 ++++++++-------- board/samsung/goni/goni.c | 8 ++++---- board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 8 ++++---- drivers/gpio/s5p_gpio.c | 20 ++++++++++---------- 6 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 485b9bf8e0..903de9c337 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -126,14 +126,14 @@ struct s5pc110_gpio { }; /* functions */ -void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); +void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); +void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); +unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); #endif /* Pin configurations */ diff --git a/arch/arm/include/asm/arch-s5pc2xx/gpio.h b/arch/arm/include/asm/arch-s5pc2xx/gpio.h index 38303e4f0c..8db5895b86 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc2xx/gpio.h @@ -80,14 +80,14 @@ struct s5pc210_gpio_part3 { }; /* functions */ -void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); +void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); +void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); +unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); #endif /* Pin configurations */ diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 581935d054..e24cd29f37 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -73,7 +73,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->j2, 7, 1); + s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -86,11 +86,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); + s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0, 4); diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 1ad68b9c07..c41e610a43 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -41,7 +41,7 @@ static void smc9115_pre_init(void) (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index acf9ee7b87..173520eb44 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -37,7 +37,7 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -116,10 +116,10 @@ int board_mmc_init(bd_t *bis) */ for (i = 0; i < 7; i++) { /* GPK2[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); /* GPK2[0:1] pull disable */ if (i == 0 || i == 1) { @@ -128,7 +128,7 @@ int board_mmc_init(bd_t *bis) } /* GPK2[2:6] pull up */ - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index a1bcddcf45..2043859906 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -36,7 +36,7 @@ #define RATE_MASK(x) (0x1 << (x + 16)) #define RATE_SET(x) (0x1 << (x + 16)) -void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) +void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) { unsigned int value; @@ -46,11 +46,11 @@ void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) writel(value, &bank->con); } -void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) +void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; - gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); value = readl(&bank->dat); value &= ~DAT_MASK(gpio); @@ -59,12 +59,12 @@ void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) +void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) { - gpio_cfg_pin(bank, gpio, GPIO_INPUT); + s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT); } -void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) +void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; @@ -75,7 +75,7 @@ void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio) +unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) { unsigned int value; @@ -83,7 +83,7 @@ unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio) return !!(value & DAT_MASK(gpio)); } -void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) +void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -102,7 +102,7 @@ void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->pull); } -void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) +void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -123,7 +123,7 @@ void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) +void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; From 0e74b56518e5479aa122b22bae10fa62c6ecd57e Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Mon, 25 Jul 2011 23:04:07 +0000 Subject: [PATCH 028/145] SMDKV310: Fix build error for smdkv310 board Fix build error for smdkv310 board: board/samsung/smdkv310/smdkv310.c:126: undefined reference to `gpio_set_pull' Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- board/samsung/smdkv310/smdkv310.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 173520eb44..e0b89dd55b 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -123,7 +123,7 @@ int board_mmc_init(bd_t *bis) /* GPK2[0:1] pull disable */ if (i == 0 || i == 1) { - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); continue; } From ebbc84af5e18f8f040996219dc92f64e950240cd Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Mon, 25 Jul 2011 23:25:16 +0000 Subject: [PATCH 029/145] SMDKV310: Fix undefined reference error Fix buld error: undefined reference to '__image_copy_end' and `save_boot_params'. start.o: In function `_image_copy_end_ofs': mmc_spl/board/samsung/smdkv310/start.S:44: undefined reference to `__image_copy_end' start.o: In function `reset': mmc_spl/board/samsung/smdkv310/start.S:137: undefined reference to `save_boot_params' Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- mmc_spl/board/samsung/smdkv310/mmc_boot.c | 4 ++++ mmc_spl/board/samsung/smdkv310/u-boot.lds | 2 ++ 2 files changed, 6 insertions(+) diff --git a/mmc_spl/board/samsung/smdkv310/mmc_boot.c b/mmc_spl/board/samsung/smdkv310/mmc_boot.c index 566f34eb02..dea1b869fa 100644 --- a/mmc_spl/board/samsung/smdkv310/mmc_boot.c +++ b/mmc_spl/board/samsung/smdkv310/mmc_boot.c @@ -54,6 +54,10 @@ void board_init_r(gd_t *id, ulong dest_addr) ; } +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} + void do_undefined_instruction(struct pt_regs *pt_regs) { } diff --git a/mmc_spl/board/samsung/smdkv310/u-boot.lds b/mmc_spl/board/samsung/smdkv310/u-boot.lds index 61cd16a71c..4a231d9df3 100644 --- a/mmc_spl/board/samsung/smdkv310/u-boot.lds +++ b/mmc_spl/board/samsung/smdkv310/u-boot.lds @@ -58,6 +58,8 @@ SECTIONS . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) From beb7f27a0d28e7209eb2e03515d6ef436fe121c6 Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Wed, 27 Jul 2011 20:36:30 +0000 Subject: [PATCH 030/145] SMDKV310: MMC SPL: Remove unwanted dummy functions Removed dummy functions in "mmc_spl/board/samsung/smdkv310/mmc_boot.c", @mmc_boot.c void do_undefined_instruction(struct pt_regs *pt_regs); void do_software_interrupt(struct pt_regs *pt_regs); void do_prefetch_abort(struct pt_regs *pt_regs); void do_data_abort(struct pt_regs *pt_regs); void do_not_used(struct pt_regs *pt_regs); void do_fiq(struct pt_regs *pt_regs); void do_irq(struct pt_regs *pt_regs); not required as called conditionally in start.S @start.S \#ifdef CONFIG_SPL_BUILD _undefined_instruction: .word _undefined_instruction _software_interrupt: .word _software_interrupt _prefetch_abort: .word _prefetch_abort _data_abort: .word _data_abort _not_used: .word _not_used _irq: .word _irq _fiq: .word _fiq _pad: .word 0x12345678 /* now 16*4=64 */ \#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ \#endif e.g. undefined_instruction: get_bad_stack bad_save_user_regs bl do_undefined_instruction Signed-off-by: Chander Kashyap --- mmc_spl/board/samsung/smdkv310/Makefile | 1 + mmc_spl/board/samsung/smdkv310/mmc_boot.c | 30 ----------------------- 2 files changed, 1 insertion(+), 30 deletions(-) diff --git a/mmc_spl/board/samsung/smdkv310/Makefile b/mmc_spl/board/samsung/smdkv310/Makefile index fdfd015cf6..85f48380d5 100644 --- a/mmc_spl/board/samsung/smdkv310/Makefile +++ b/mmc_spl/board/samsung/smdkv310/Makefile @@ -34,6 +34,7 @@ include $(TOPDIR)/config.mk LDSCRIPT= $(TOPDIR)/mmc_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS = -Bstatic -T $(mmcobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_MMC_SPL +AFLAGS += -DCONFIG_SPL_BUILD CFLAGS += -DCONFIG_MMC_SPL CFLAGS += -DCONFIG_SPL_BUILD diff --git a/mmc_spl/board/samsung/smdkv310/mmc_boot.c b/mmc_spl/board/samsung/smdkv310/mmc_boot.c index dea1b869fa..2f3e463bce 100644 --- a/mmc_spl/board/samsung/smdkv310/mmc_boot.c +++ b/mmc_spl/board/samsung/smdkv310/mmc_boot.c @@ -57,33 +57,3 @@ void board_init_r(gd_t *id, ulong dest_addr) void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) { } - -void do_undefined_instruction(struct pt_regs *pt_regs) -{ -} - -void do_software_interrupt(struct pt_regs *pt_regs) -{ -} - -void do_prefetch_abort(struct pt_regs *pt_regs) -{ -} - -void do_data_abort(struct pt_regs *pt_regs) -{ -} - -void do_not_used(struct pt_regs *pt_regs) -{ -} - -void do_fiq(struct pt_regs *pt_regs) -{ -} - -#ifndef CONFIG_USE_IRQ -void do_irq(struct pt_regs *pt_regs) -{ -} -#endif From c8fc4284cf2e447e07c7e0718982902a4f6e6bff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Tue, 9 Aug 2011 23:18:54 +0000 Subject: [PATCH 031/145] gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal) This is a cosmetic patch, which is changing the gpio_ prefix to s5p_gpio_. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/universal_c210/universal.c | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index b65bc6ecb7..1b27e8b428 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -160,7 +160,7 @@ int board_mmc_init(bd_t *bis) * you should set it HIGH since it removes the inverter */ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - gpio_direction_output(&gpio1->e3, 6, 0); + s5p_gpio_direction_output(&gpio1->e3, 6, 0); break; default: /* @@ -168,7 +168,7 @@ int board_mmc_init(bd_t *bis) * But set it as HIGH to ensure */ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - gpio_direction_output(&gpio1->e1, 3, 1); + s5p_gpio_direction_output(&gpio1->e1, 3, 1); break; } @@ -192,25 +192,25 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPK0[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k0, i, 0x2); + s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); /* GPK0[0:6] pull disable */ - gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); /* GPK0[0:6] drv 4x */ - gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); } for (i = 3; i < 7; i++) { /* GPK1[3:6] special function 3 */ - gpio_cfg_pin(&gpio2->k1, i, 0x3); + s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); /* GPK1[3:6] pull disable */ - gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); /* GPK1[3:6] drv 4x */ - gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); } /* T-flash detect */ - gpio_cfg_pin(&gpio2->x3, 4, 0xf); - gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); + s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); + s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); /* * MMC device init @@ -223,7 +223,7 @@ int board_mmc_init(bd_t *bis) * Check the T-flash detect pin * GPX3[4] T-flash detect pin */ - if (!gpio_get_value(&gpio2->x3, 4)) { + if (!s5p_gpio_get_value(&gpio2->x3, 4)) { /* * SD card GPIO: * GPK2[0] SD_2_CLK(2) @@ -235,11 +235,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPK2[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k2, i, 0x2); + s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); /* GPK2[0:6] pull disable */ - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); /* GPK2[0:6] drv 4x */ - gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); } err = s5p_mmc_init(2, 4); } From 080a46eaf1c2a51cc4df1a4cd3ff2578e64c46b6 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Sun, 31 Jul 2011 20:30:53 +0000 Subject: [PATCH 032/145] omap: fix gpio related build breaks Signed-off-by: Aneesh V Acked-by: Dirk Behme --- arch/arm/cpu/armv7/omap-common/gpio.c | 2 +- arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap4/board.c | 2 +- arch/arm/include/asm/arch-omap3/gpio.h | 50 +++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/omap3.h | 8 ---- arch/arm/include/asm/arch-omap4/gpio.h | 50 +++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/omap4.h | 8 ---- board/pandora/pandora.c | 1 + 8 files changed, 104 insertions(+), 19 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap3/gpio.h create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c index f4c347941d..2fcaf5a9f8 100644 --- a/arch/arm/cpu/armv7/omap-common/gpio.c +++ b/arch/arm/cpu/armv7/omap-common/gpio.c @@ -36,7 +36,7 @@ * published by the Free Software Foundation. */ #include -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 4aaf97b335..bce3ee695f 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include /* Declarations */ extern omap3_sysinfo sysinfo; diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 5943d61fc2..8e9054594d 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include "omap4_mux_data.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h new file mode 100644 index 0000000000..8bba3b030b --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/gpio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_OMAP3_H +#define _GPIO_OMAP3_H + +#include + +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 + +#endif /* _GPIO_OMAP3_H */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index d9d49da566..230eaadaa8 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -100,14 +100,6 @@ struct s32ktimer { #endif /* __ASSEMBLY__ */ -/* OMAP3 GPIO registers */ -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - #ifndef __ASSEMBLY__ struct gpio { unsigned char res1[0x34]; diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h new file mode 100644 index 0000000000..26f19d19a5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/gpio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_OMAP4_H +#define _GPIO_OMAP4_H + +#include + +#define OMAP44XX_GPIO1_BASE 0x4A310000 +#define OMAP44XX_GPIO2_BASE 0x48055000 +#define OMAP44XX_GPIO3_BASE 0x48057000 +#define OMAP44XX_GPIO4_BASE 0x48059000 +#define OMAP44XX_GPIO5_BASE 0x4805B000 +#define OMAP44XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP4_H */ diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 9aad0e6189..7ff46d771c 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -153,12 +153,4 @@ struct s32ktimer { #define DEV_DATA_PTR_OFFSET 0x18 #define BOOT_MODE_OFFSET 0x8 -/* GPIO */ -#define OMAP44XX_GPIO1_BASE 0x4A310000 -#define OMAP44XX_GPIO2_BASE 0x48055000 -#define OMAP44XX_GPIO3_BASE 0x48057000 -#define OMAP44XX_GPIO4_BASE 0x48059000 -#define OMAP44XX_GPIO5_BASE 0x4805B000 -#define OMAP44XX_GPIO6_BASE 0x4805D000 - #endif diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 992e9f7625..0df45702c7 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include "pandora.h" From 8fcf5959a8dcd92ef01d5e909a5c14581488df93 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Tue, 9 Aug 2011 07:52:57 +0000 Subject: [PATCH 033/145] mkimage: Fix 'Unknown OMAP image type - 5' Using mkimage with e.g. tools/mkimage -A arm -T firmware -O u-boot -d u-boot.bin foo.img gives a warning "Unknown OMAP image type - 5" while it seems that the image itself is created successfully. This does come from the patch "mkimage: Add OMAP boot image support". The method check_image_type in image_type_params is supposed to just return success or failure. However, for omap it also calls fprintf: static int omapimage_check_image_types(uint8_t type) { if (type == IH_TYPE_OMAPIMAGE) return EXIT_SUCCESS; else { fprintf(stderr, "Unknown OMAP image type - %x", type); return EXIT_FAILURE; } } All the other image checkers and no others have this, so the fix is to simply remove the fprintf. Signed-off-by: Dirk Behme CC: John Rigby CC: Aneesh V CC: Sandeep Paulraj --- tools/omapimage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/omapimage.c b/tools/omapimage.c index 29d91cc69c..5e739ac647 100644 --- a/tools/omapimage.c +++ b/tools/omapimage.c @@ -49,7 +49,6 @@ static int omapimage_check_image_types(uint8_t type) if (type == IH_TYPE_OMAPIMAGE) return EXIT_SUCCESS; else { - fprintf(stderr, "Unknown OMAP image type - %x", type); return EXIT_FAILURE; } } From 34455b04fc35ff9d1e5bcac7bec91e7a32b44d7a Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Sat, 20 Aug 2011 21:40:26 +0000 Subject: [PATCH 034/145] omap4: fix build warning due to signed unsigned comparison Signed-off-by: Aneesh V --- arch/arm/include/asm/arch-omap4/clocks.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 374e0642ec..45c947d648 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -679,12 +679,12 @@ struct dpll_regs { struct dpll_params { u32 m; u32 n; - u8 m2; - u8 m3; - u8 m4; - u8 m5; - u8 m6; - u8 m7; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; + s8 m7; }; #endif /* _CLOCKS_OMAP4_H_ */ From f89f6109e977cb1aea8cee69b384ed622c2f8549 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Sun, 7 Aug 2011 20:05:45 +0000 Subject: [PATCH 035/145] omap4: increase SRAM budget to fix build error Signed-off-by: Aneesh V Cc: Dirk Behme Cc: Sandeep Paulraj Acked-by: Dirk Behme --- include/configs/omap4_panda.h | 2 +- include/configs/omap4_sdp4430.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index e313231a4d..814f15c5c4 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -245,7 +245,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_MAX_SIZE (38 * 1024) #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 5b3110cd50..1a5d7a66c5 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -251,7 +251,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_MAX_SIZE (38 * 1024) #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 From 96c9745fa1f03a0e24d09a32344a1f0c821bc9af Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Aug 2011 21:24:27 +0000 Subject: [PATCH 036/145] ARM: versatilepb : drop warnings due to double definitions CONFIG_ARCH_VERSATILE_PB is defined twice - drop the define from config.h. Signed-off-by: Stefano Babic --- boards.cfg | 2 +- include/configs/versatile.h | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/boards.cfg b/boards.cfg index abee8211ea..413ab9244d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -77,7 +77,7 @@ voiceblue arm arm925t omap1510inn arm arm925t - ti integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp -versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU +versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB aspenite arm arm926ejs - Marvell armada100 diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 32cee824bb..3bfcdffb90 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -39,10 +39,6 @@ #define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ #define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ -#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */ -#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */ -#endif - #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END 0x10000000 #define CONFIG_SYS_HZ (1000000 / 256) From 9db1bfa110ac411ab3468e817f7f74b2439eb8c8 Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 13 Jul 2011 21:11:53 +0000 Subject: [PATCH 037/145] ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 38 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 5 ++++ doc/README.imx5 | 17 +++++++++++ 3 files changed, 60 insertions(+) create mode 100644 doc/README.imx5 diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 94de9f1d61..6c66b42619 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -121,6 +121,35 @@ beq 1b .endm +.macro setup_pll_errata pll, freq + ldr r2, =\pll + mov r1, #0x0 + str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ + ldr r1, =0x00001236 + str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */ +1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ + ands r1, r1, #0x1 + beq 1b + + ldr r5, \freq + str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */ + str r5, [r2, #PLL_DP_HFS_MFN] + + mov r1, #0x1 + str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */ + +2: ldr r1, [r2, #PLL_DP_CONFIG] + tst r1, #1 + bne 2b + + ldr r1, =100 /* Wait at least 4 us */ +3: subs r1, r1, #1 + bge 3b + + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ +.endm + .macro init_clock ldr r0, =CCM_BASE_ADDR @@ -157,7 +186,12 @@ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] +#if defined(CONFIG_MX51_PLL_ERRATA) + setup_pll PLL1_BASE_ADDR, 864 + setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT +#else setup_pll PLL1_BASE_ADDR, 800 +#endif #if defined(CONFIG_MX51) setup_pll PLL3_BASE_ADDR, 665 @@ -287,6 +321,10 @@ lowlevel_init: mov pc,lr /* Board level setting value */ +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT W_DP_OP_800: .word DP_OP_800 W_DP_MFD_800: .word DP_MFD_800 W_DP_MFN_800: .word DP_MFN_800 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index e83ca29006..fb2c66fa0e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -235,6 +235,11 @@ /* Assuming 24MHz input clock with doubler ON */ /* MFI PDF */ +#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_864 (180 - 1) /* PL Dither mode */ +#define DP_MFN_864 180 +#define DP_MFN_800_DIT 60 /* PL Dither mode */ + #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) #define DP_MFD_850 (48 - 1) #define DP_MFN_850 41 diff --git a/doc/README.imx5 b/doc/README.imx5 new file mode 100644 index 0000000000..f7eab7d4b2 --- /dev/null +++ b/doc/README.imx5 @@ -0,0 +1,17 @@ +U-Boot for Freescale i.MX5x + +This file contains information for the port of U-Boot to the Freescale +i.MX5x SoCs. + +1. CONFIGURATION OPTIONS/SETTINGS +--------------------------------- + +1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. + This option should be enabled by all boards using the i.MX51 silicon + version up until (including) 3.0 running at 800MHz. + The PLL's in the i.MX51 processor can go out of lock due to a metastable + condition in an analog flip-flop when used at high frequencies. + This workaround implements an undocumented feature in the PLL (dither + mode), which causes the effect of this failure to be much lower (in terms + of frequency deviation), avoiding system failure, or at least decreasing + the likelihood of system failure. From 9691c5b96d889b1d4c8908c449b47d80699dc915 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 19 Aug 2011 03:28:10 +0000 Subject: [PATCH 038/145] mx53: ddr3: Update DD3 initialization Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang Signed-off-by: Fabio Estevam --- board/freescale/mx53ard/imximage_dd3.cfg | 6 +++--- board/freescale/mx53loco/imximage.cfg | 6 +++--- board/freescale/mx53smd/imximage.cfg | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg index 0f298abbd5..50e05afa62 100644 --- a/board/freescale/mx53ard/imximage_dd3.cfg +++ b/board/freescale/mx53ard/imximage_dd3.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index ce9c8fc3e3..f30258eda4 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg index 0f298abbd5..50e05afa62 100644 --- a/board/freescale/mx53smd/imximage.cfg +++ b/board/freescale/mx53smd/imximage.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901C 0x00000000 From 6b5acfc12151ac151800375b447938cc4a4e86ff Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 2 Aug 2011 14:42:36 +0200 Subject: [PATCH 039/145] MX35: MX35PDK: support additional RAM on CSD1 Modules on mx35pdk have additional 128MB memory connected to CSD1. Signed-off-by: Stefano Babic --- board/freescale/mx35pdk/lowlevel_init.S | 9 +++++---- board/freescale/mx35pdk/mx35pdk.c | 17 +++++++++++++++-- include/configs/mx35pdk.h | 6 +++--- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S index 9b0f1b5259..9fd04cbdb8 100644 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -193,10 +193,11 @@ mov r2, #0x00 mov r1, #CSD0_BASE_ADDR bl setup_sdram_bank - cmp r3, #0x0 - orreq r5, r5, #1 - eorne r2, r2, #0x1 - blne setup_sdram_bank + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD1_BASE_ADDR + bl setup_sdram_bank mov lr, fp diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index da926e5781..a6b5a51f45 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -52,12 +52,25 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + static void setup_iomux_i2c(void) { int pad; diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 086355bb67..0d4b7334be 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -173,11 +173,11 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define iomem_valid_addr(addr, size) \ - (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) From 7acec2594840b2602054c5a9d1e14792837fd9db Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 17 Aug 2011 17:52:40 +0200 Subject: [PATCH 040/145] MX: MX35 / MX5: uniform clock command with powerpc There was already a command to show the processor clocks for PowerPC (clocks). For i.MX, the "clockinfo" command was introduce. The patch sets the same command name used on PowerPC. A nasty and not needed newline is also dropped in the help for the command. Signed-off-by: Stefano Babic --- arch/arm/cpu/arm1136/mx35/generic.c | 4 ++-- arch/arm/cpu/armv7/mx5/clock.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 1b4ab75036..fcfaba5515 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -417,8 +417,8 @@ int do_mx35_showclocks(cmd_tbl_t *cmdtp, } U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, - "display clocks\n", + clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, + "display clocks", "" ); diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 0b04a8819a..00610a0d59 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -288,7 +288,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /***************************************************/ U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, - "display clocks\n", + clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, + "display clocks", "" ); From d8e0ca851b91b8ac16c648d437f668997b606e6b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:45:44 +0200 Subject: [PATCH 041/145] IMX: uniform GPIO interface using GPIO framework IMX processors has a slightly different interface to access GPIOs and do not make use of the provided GPIO framework. The patch substitutes mxc_ specific functions and make use of the API in asm/gpio.h Signed-off-by: Stefano Babic --- drivers/gpio/mxc_gpio.c | 51 +++++++++++++++++++++++++++++++++--- drivers/spi/mxc_spi.c | 8 +++--- include/mxc_gpio.h | 57 ----------------------------------------- 3 files changed, 51 insertions(+), 65 deletions(-) delete mode 100644 include/mxc_gpio.h diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 6efbb02c16..a7f36b2933 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -2,6 +2,9 @@ * Copyright (C) 2009 * Guennadi Liakhovetski, DENX Software Engineering, * + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,10 +25,16 @@ */ #include #include +#include #include -#include #include +enum mxc_gpio_direction { + MXC_GPIO_DIRECTION_IN, + MXC_GPIO_DIRECTION_OUT, +}; + + /* GPIO port description */ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, @@ -41,7 +50,8 @@ static unsigned long gpio_ports[] = { #endif }; -int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) +static int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction) { unsigned int port = gpio >> 5; struct gpio_regs *regs; @@ -68,7 +78,7 @@ int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) return 0; } -void mxc_gpio_set(unsigned int gpio, unsigned int value) +void gpio_set_value(int gpio, int value) { unsigned int port = gpio >> 5; struct gpio_regs *regs; @@ -89,7 +99,7 @@ void mxc_gpio_set(unsigned int gpio, unsigned int value) writel(l, ®s->gpio_dr); } -int mxc_gpio_get(unsigned int gpio) +int gpio_get_value(int gpio) { unsigned int port = gpio >> 5; struct gpio_regs *regs; @@ -106,3 +116,36 @@ int mxc_gpio_get(unsigned int gpio) return l; } + +int gpio_request(int gp, const char *label) +{ + unsigned int port = gp >> 5; + if (port >= ARRAY_SIZE(gpio_ports)) + return -EINVAL; + return 0; +} + +void gpio_free(int gp) +{ +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + return mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_IN); +} + +int gpio_direction_output(int gp, int value) +{ + int ret = mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_OUT); + + if (ret < 0) + return ret; + + gpio_set_value(gp, value); + return 0; +} diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 81381d9b9a..2fa748608f 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include @@ -145,14 +145,14 @@ void spi_cs_activate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) - mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); + gpio_set_value(mxcs->gpio, mxcs->ss_pol); } void spi_cs_deactivate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) - mxc_gpio_set(mxcs->gpio, + gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); } @@ -468,7 +468,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) if (cs > 3) { mxcs->gpio = cs >> 8; cs &= 3; - ret = mxc_gpio_direction(mxcs->gpio, OUT); + ret = gpio_direction_output(mxcs->gpio, 0); if (ret) { printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); return -EINVAL; diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h deleted file mode 100644 index f673dcecd6..0000000000 --- a/include/mxc_gpio.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MXC_GPIO_H -#define __MXC_GPIO_H - -/* Converts a GPIO port number and the internal bit position - * to the GPIO number - */ -#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) - -enum mxc_gpio_direction { - MXC_GPIO_DIRECTION_IN, - MXC_GPIO_DIRECTION_OUT, -}; - -#ifdef CONFIG_MXC_GPIO -extern int mxc_gpio_direction(unsigned int gpio, - enum mxc_gpio_direction direction); -extern void mxc_gpio_set(unsigned int gpio, unsigned int value); -extern int mxc_gpio_get(unsigned int gpio); -#else -static inline int mxc_gpio_direction(unsigned int gpio, - enum mxc_gpio_direction direction) -{ - return 1; -} -static inline int mxc_gpio_get(unsigned int gpio) -{ - return 1; -} -static inline void mxc_gpio_set(unsigned int gpio, unsigned int value) -{ -} -#endif - -#endif From 41eca7416cfc882b22172960e5a3516f0eac6498 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:48:19 +0200 Subject: [PATCH 042/145] MX25: make use of GPIO framework for MX25 processor Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx25/gpio.h | 45 +++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/imx-regs.h | 12 ------ 2 files changed, 45 insertions(+), 12 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx25/gpio.h diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h new file mode 100644 index 0000000000..dc6edc7c85 --- /dev/null +++ b/arch/arm/include/asm/arch-mx25/gpio.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_MX25_GPIO_H +#define __ASM_ARCH_MX25_GPIO_H + +/* Converts a GPIO port number and the internal bit position + * to the GPIO number + */ +#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) + +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 psr; /* pad satus */ + u32 icr1; /* interrupt config 1 */ + u32 icr2; /* interrupt config 2 */ + u32 imr; /* interrupt mask */ + u32 isr; /* interrupt status */ + u32 edge_sel; /* edge select */ +}; + +#endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 2ccb445975..9e30f7c2bc 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -84,18 +84,6 @@ struct esdramc_regs { u32 cdlyl; /* delay line cycle length debug */ }; -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 psr; /* pad satus */ - u32 icr1; /* interrupt config 1 */ - u32 icr2; /* interrupt config 2 */ - u32 imr; /* interrupt mask */ - u32 isr; /* interrupt status */ - u32 edge_sel; /* edge select */ -}; - /* General Purpose Timer (GPT) registers */ struct gpt_regs { u32 ctrl; /* control */ From 6cb2e774f24ada52b2476b1cd7a1f7b63acbad2e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:50:06 +0200 Subject: [PATCH 043/145] MX31: make use of GPIO framework for MX31 processor Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx31/gpio.h | 35 +++++++++++++++++++++++ arch/arm/include/asm/arch-mx31/imx-regs.h | 7 ----- 2 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx31/gpio.h diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h new file mode 100644 index 0000000000..95b73bfc34 --- /dev/null +++ b/arch/arm/include/asm/arch-mx31/gpio.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_MX31_GPIO_H +#define __ASM_ARCH_MX31_GPIO_H + +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + +#endif diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 3c8d6076d2..2064870f44 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -57,13 +57,6 @@ struct clock_control_regs { u32 pdr2; }; -/* GPIO Registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; - struct cspi_regs { u32 rxdata; u32 txdata; From 7d8d0b1a4a7a679e4148a4e64d755321edc58f3e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:51:06 +0200 Subject: [PATCH 044/145] MX5: make use of GPIO framework for MX5 processor Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx5/gpio.h | 35 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 7 ----- 2 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx5/gpio.h diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h new file mode 100644 index 0000000000..1dc34e9164 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/gpio.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_MX5_GPIO_H +#define __ASM_ARCH_MX5_GPIO_H + +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + +#endif diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index fb2c66fa0e..a4e680b8d3 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -409,13 +409,6 @@ struct iomuxc { }; #endif -/* GPIO Registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; - /* System Reset Controller (SRC) */ struct src { u32 scr; From 729b74add90f5964b19e76f1de378d372007768e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:52:04 +0200 Subject: [PATCH 045/145] MX35: make use of GPIO framework for MX35 processor Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx35/gpio.h | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx35/gpio.h diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h new file mode 100644 index 0000000000..7bcc3e8688 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/gpio.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_MX35_GPIO_H +#define __ASM_ARCH_MX35_GPIO_H + +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 psr; /* pad satus */ + u32 icr1; /* interrupt config 1 */ + u32 icr2; /* interrupt config 2 */ + u32 imr; /* interrupt mask */ + u32 isr; /* interrupt status */ + u32 edge_sel; /* edge select */ +}; + +#endif From 9400f59267b599c622d99986799c15816459a984 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:52:58 +0200 Subject: [PATCH 046/145] MX31: QONG: make use of GPIO framework Signed-off-by: Stefano Babic --- board/davedenx/qong/fpga.c | 10 +++++----- board/davedenx/qong/qong.c | 36 +++++++++++++++++------------------- 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c index 789acf0696..6536a0b695 100644 --- a/board/davedenx/qong/fpga.c +++ b/board/davedenx/qong/fpga.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include "qong_fpga.h" @@ -41,22 +41,22 @@ static void qong_jtag_init(void) static void qong_fpga_jtag_set_tdi(int value) { - mxc_gpio_set(QONG_FPGA_TDI_PIN, value); + gpio_set_value(QONG_FPGA_TDI_PIN, value); } static void qong_fpga_jtag_set_tms(int value) { - mxc_gpio_set(QONG_FPGA_TMS_PIN, value); + gpio_set_value(QONG_FPGA_TMS_PIN, value); } static void qong_fpga_jtag_set_tck(int value) { - mxc_gpio_set(QONG_FPGA_TCK_PIN, value); + gpio_set_value(QONG_FPGA_TCK_PIN, value); } static int qong_fpga_jtag_get_tdo(void) { - return mxc_gpio_get(QONG_FPGA_TDO_PIN); + return gpio_get_value(QONG_FPGA_TDO_PIN); } lattice_board_specific_func qong_fpga_fns = { diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index ec22627680..99432edabc 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include "qong_fpga.h" #include @@ -51,9 +51,9 @@ int dram_init (void) static void qong_fpga_reset(void) { - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + gpio_set_value(QONG_FPGA_RST_PIN, 0); udelay(30); - mxc_gpio_set(QONG_FPGA_RST_PIN, 1); + gpio_set_value(QONG_FPGA_RST_PIN, 1); udelay(300); } @@ -76,21 +76,20 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); - mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(QONG_FPGA_RST_PIN, 0); /* set interrupt pin as input */ - mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(QONG_FPGA_IRQ_PIN); /* FPGA JTAG Interface */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO)); - mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_output(QONG_FPGA_TCK_PIN, 0); + gpio_direction_output(QONG_FPGA_TMS_PIN, 0); + gpio_direction_output(QONG_FPGA_TDI_PIN, 0); + gpio_direction_input(QONG_FPGA_TDO_PIN); #endif /* setup pins for UART1 */ @@ -263,27 +262,26 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mxc_gpio_set(15, 1); - mxc_gpio_set(14, 1); - mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); - mxc_gpio_set(15, 0); + gpio_set_value(15, 1); + gpio_set_value(14, 1); + gpio_direction_output(15, 0); + gpio_direction_input(16); + gpio_direction_input(14); } int qong_nand_rdy(void *chip) { udelay(1); - return mxc_gpio_get(16); + return gpio_get_value(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mxc_gpio_set(15, 0); + gpio_set_value(15, 0); else - mxc_gpio_set(15, 1); + gpio_set_value(15, 1); } From e70a10607ded4c3af4847f177b7a897b52e31fee Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:53:32 +0200 Subject: [PATCH 047/145] MX5: efikamx: make use of GPIO framework Signed-off-by: Stefano Babic CC: Marek Vasut --- board/efikamx/efikamx.c | 62 ++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 38 deletions(-) diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 4b3691808e..5be1f6ca58 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -76,28 +76,23 @@ u32 get_efika_rev(void) * rev1.4: 1,0,0 */ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), - MXC_GPIO_DIRECTION_OUT); /* set to 1 in order to get correct value on board rev1.1 */ - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; return (~rev & 0x7) + 1; } @@ -154,15 +149,11 @@ static void setup_iomux_spi(void) /* Configure SS0 as a GPIO */ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), - MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); /* Configure SS1 as a GPIO */ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), - MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); @@ -282,9 +273,9 @@ int board_mmc_getcd(u8 *absent, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); else - *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); return 0; } @@ -307,10 +298,8 @@ int board_mmc_init(bd_t *bis) PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), - MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), - MXC_GPIO_DIRECTION_IN); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ if (get_efika_rev() < EFIKAMX_BOARD_REV_12) { @@ -389,10 +378,8 @@ int board_mmc_init(bd_t *bis) PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), - MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), - MXC_GPIO_DIRECTION_IN); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (!ret) @@ -508,25 +495,24 @@ void setup_iomux_led(void) { /* Blue LED */ mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + /* Green LED */ mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); + /* Red LED */ mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); } void efikamx_toggle_led(uint32_t mask) { - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), mask & EFIKAMX_LED_BLUE); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), mask & EFIKAMX_LED_GREEN); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), mask & EFIKAMX_LED_RED); } From 7caa655f74245e15271878ed31bd1efc2eb68d90 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:55:05 +0200 Subject: [PATCH 048/145] MX25: zmx25: make use of GPIO framework Signed-off-by: Stefano Babic CC: Matthias Weisser --- board/syteco/zmx25/zmx25.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index f0550389eb..893adc6bd5 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -29,7 +29,7 @@ * */ #include -#include +#include #include #include #include @@ -56,8 +56,7 @@ int board_init() /* Setup of core volatage selection pin to run at 1.4V */ writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 15), 1); /* Setup of input daisy chains for SD card pins*/ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); @@ -69,11 +68,10 @@ int board_init() /* Setup of digital output for USB power and OC */ writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 28), 1); writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN); + gpio_direction_input(MXC_GPIO_PORT_TO_NUM(1, 18)); /* Setup of digital output control pins */ writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ @@ -85,25 +83,21 @@ int board_init() writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ /* Switch both output drivers off */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 7), 0); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 6), 0); /* Setup of key input pin GPIO2[29]*/ writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN); + gpio_direction_input(MXC_GPIO_PORT_TO_NUM(2, 29)); /* Setup of status LED outputs */ writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ /* Switch both LEDs off */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 29), 0); /* Setup of CAN1 and CAN2 signals */ writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ @@ -158,13 +152,12 @@ int board_late_init(void) writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); /* assert PHY reset (low) */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0); udelay(5000); /* deassert PHY reset */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1); udelay(5000); #endif @@ -172,12 +165,12 @@ int board_late_init(void) e = getenv("gs_base_board"); if (e != NULL) { if (strcmp(e, "G283") == 0) { - int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29)); + int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29)); if (key) { /* Switch on both LEDs to inidcate boot mode */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0); setenv("preboot", "run gs_slow_boot"); } else From 00c07fe6926ba27844eb480373bf45d0fcd76dff Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:56:06 +0200 Subject: [PATCH 049/145] MX5: mx53ard: make use of GPIO framework Signed-off-by: Stefano Babic CC: Fabio Estevam --- board/freescale/mx53ard/mx53ard.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 134603a7cf..6e3360b65f 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ @@ -93,9 +93,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(1); /*GPIO1_1*/ + *cd = gpio_get_value(1); /*GPIO1_1*/ else - *cd = mxc_gpio_get(4); /*GPIO1_4*/ + *cd = gpio_get_value(4); /*GPIO1_4*/ return 0; } @@ -176,7 +176,7 @@ static void weim_smc911x_iomux(void) { /* ETHERNET_INT as GPIO2_31 */ mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); - mxc_gpio_direction(ETHERNET_INT, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(ETHERNET_INT); /* Data bus */ mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); From 04e25fd6292966982818de5f98247bec130dd4ec Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:56:57 +0200 Subject: [PATCH 050/145] MX5: mx53smd: make use of GPIO framework Signed-off-by: Stefano Babic CC: Fabio Estevam --- board/freescale/mx53smd/mx53smd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 21b5d14c02..4a7ee550d5 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -139,7 +139,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ return 0; } From 4c0443c41fee7520c960d3394b0d3fc65c5b4756 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:57:53 +0200 Subject: [PATCH 051/145] MX5: vision2: make use of GPIO framework Signed-off-by: Stefano Babic --- board/ttcontrol/vision2/vision2.c | 71 ++++++++++++------------------- 1 file changed, 27 insertions(+), 44 deletions(-) diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index 565c4d05ba..17a25587d6 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -69,9 +69,9 @@ void hw_watchdog_reset(void) int val; /* toggle watchdog trigger pin */ - val = mxc_gpio_get(66); + val = gpio_get_value(66); val = val ? 0 : 1; - mxc_gpio_set(66, val); + gpio_set_value(66, val); } #endif @@ -233,30 +233,22 @@ static void reset_peripherals(int reset) if (reset) { /* reset_n is on NANDF_D15 */ - mxc_gpio_set(89, 0); - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(89, 0); #ifdef CONFIG_VISION2_HW_1_0 /* * set FEC Configuration lines * set levels of FEC config lines */ - mxc_gpio_set(75, 0); - mxc_gpio_set(74, 1); - mxc_gpio_set(95, 1); - mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(75, 0); + gpio_direction_output(74, 1); + gpio_direction_output(95, 1); /* set direction of FEC config lines */ - mxc_gpio_set(59, 0); - mxc_gpio_set(60, 0); - mxc_gpio_set(61, 0); - mxc_gpio_set(55, 1); - mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(59, 0); + gpio_direction_output(60, 0); + gpio_direction_output(61, 0); + gpio_direction_output(55, 1); /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); @@ -283,7 +275,7 @@ static void reset_peripherals(int reset) PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); } else { /* set FEC Control lines */ - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(89); udelay(500); #ifdef CONFIG_VISION2_HW_1_0 @@ -438,31 +430,23 @@ static void setup_gpios(void) * Set GPIO1_4 to high and output; it is used to reset * the system on reboot */ - mxc_gpio_set(4, 1); - mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(4, 1); - mxc_gpio_set(7, 0); - mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(7, 0); for (i = 65; i < 71; i++) { - mxc_gpio_set(i, 0); - mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(i, 0); } - mxc_gpio_set(94, 0); - mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(94, 0); /* Set POWER_OFF high */ - mxc_gpio_set(91, 1); - mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(91, 1); - mxc_gpio_set(90, 0); - mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(90, 0); - mxc_gpio_set(122, 0); - mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(122, 0); - mxc_gpio_set(121, 1); - mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(121, 1); WATCHDOG_RESET(); } @@ -551,7 +535,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(0); + *cd = gpio_get_value(0); else *cd = 0; @@ -623,8 +607,7 @@ int board_early_init_f(void) init_drive_strength(); /* Setup debug led */ - mxc_gpio_set(6, 0); - mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(6, 0); mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); @@ -644,12 +627,12 @@ int board_early_init_f(void) static void backlight(int on) { if (on) { - mxc_gpio_set(65, 1); + gpio_set_value(65, 1); udelay(10000); - mxc_gpio_set(68, 1); + gpio_set_value(68, 1); } else { - mxc_gpio_set(65, 0); - mxc_gpio_set(68, 0); + gpio_set_value(65, 0); + gpio_set_value(68, 0); } } @@ -660,7 +643,7 @@ void lcd_enable(void) mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0); - mxc_gpio_set(2, 1); + gpio_set_value(2, 1); mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0); ret = mx51_fb_init(&nec_nl6448bc26_09c); From f7a364745e20c63feaa2a4d2926e92fc2bd7bdc7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:58:22 +0200 Subject: [PATCH 052/145] MX5: mx53evk: make use of GPIO framework Signed-off-by: Stefano Babic CC: Jason Liu --- board/freescale/mx53evk/mx53evk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 88095dc7ae..81857ffed3 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -213,9 +213,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ else - *cd = mxc_gpio_get(75); /*GPIO3_11*/ + *cd = gpio_get_value(75); /*GPIO3_11*/ return 0; } From 50410078cd587f6b9ee915bd178854c0ee6d9bfe Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 10:59:33 +0200 Subject: [PATCH 053/145] MX5: mx53loco: make use of GPIO framework Signed-off-by: Stefano Babic CC: Jason Liu --- board/freescale/mx53loco/mx53loco.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 18b388eeda..ade100608d 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -146,9 +146,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ else - *cd = mxc_gpio_get(75); /*GPIO3_11*/ + *cd = gpio_get_value(75); /*GPIO3_11*/ return 0; } From a4adedd4399e5b8a164597964437c4b69e84c585 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 11:00:32 +0200 Subject: [PATCH 054/145] MX35: mx35pdk: make use of GPIO framework Signed-off-by: Stefano Babic --- board/freescale/mx35pdk/mx35pdk.c | 5 ++--- include/configs/mx35pdk.h | 1 + 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index a6b5a51f45..9eefe5ee16 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include @@ -240,8 +240,7 @@ int board_late_init(void) mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); - mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(37, 1); + gpio_direction_output(37, 1); } val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 0d4b7334be..4e9022d814 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -63,6 +63,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI +#define CONFIG_MXC_GPIO /* From 753fc2ebf98a5112fd1dea4ea0806548c741beaf Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 21 Aug 2011 23:29:52 +0200 Subject: [PATCH 055/145] MX5: mx51evk: make use of GPIO framework Signed-off-by: Stefano Babic --- board/freescale/mx51evk/mx51evk.c | 18 +++++------------- include/configs/mx51evk.h | 1 + 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index fd7342f112..94ea1f2905 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -180,7 +181,6 @@ static void setup_iomux_spi(void) static void power_init(void) { unsigned int val; - unsigned int reg; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; /* Write needed to Power Gate 2 register */ @@ -249,13 +249,7 @@ static void power_init(void) pmic_reg_write(REG_MODE_1, val); udelay(200); - reg = readl(GPIO2_BASE_ADDR + 0x0); - reg &= ~0x4000; /* Lower reset line */ - writel(reg, GPIO2_BASE_ADDR + 0x0); - - reg = readl(GPIO2_BASE_ADDR + 0x4); - reg |= 0x4000; /* configure GPIO lines as output */ - writel(reg, GPIO2_BASE_ADDR + 0x4); + gpio_direction_output(46, 0); /* Reset the ethernet controller over GPIO */ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); @@ -267,9 +261,7 @@ static void power_init(void) udelay(500); - reg = readl(GPIO2_BASE_ADDR + 0x0); - reg |= 0x4000; - writel(reg, GPIO2_BASE_ADDR + 0x0); + gpio_set_value(46, 1); } #ifdef CONFIG_FSL_ESDHC @@ -278,9 +270,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = readl(GPIO1_BASE_ADDR) & 0x01; + *cd = gpio_get_value(0); else - *cd = readl(GPIO1_BASE_ADDR) & 0x40; + *cd = gpio_get_value(6); return 0; } diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3f2aca1bf3..7d05dc8429 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -60,6 +60,7 @@ */ #define CONFIG_MXC_UART #define CONFIG_SYS_MX51_UART1 +#define CONFIG_MXC_GPIO /* * SPI Configs From 5bd9a9b01bd817948dc4b931e04fd0f7fcbde119 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 26 Aug 2011 11:44:52 +0200 Subject: [PATCH 056/145] MX31: mx31ads: make use of GPIO framework Signed-off-by: Stefano Babic --- include/configs/mx31ads.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 3c61911b04..adb2ee1ce9 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -65,6 +65,7 @@ #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CONFIG_MXC_GPIO #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 From 87e14f0f56df39c82dbfb0d997c1ba657c003882 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 26 Aug 2011 11:54:05 +0200 Subject: [PATCH 057/145] MX31: imx31_litekit: make use of GPIO framework Signed-off-by: Stefano Babic --- include/configs/imx31_litekit.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 1131db0a50..b7f1cb3c75 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -63,6 +63,7 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 From a410d0a343a474538b3751b3cbbb797d273987e1 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 26 Aug 2011 12:06:56 +0200 Subject: [PATCH 058/145] IMX: scb9328: drop warnings Drop warning: "passing argument 1 of 'get_ram_size' discards qualifiers from pointer target type" Signed-off-by: Stefano Babic CC: Torsten Koschorrek --- board/scb9328/scb9328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 2e31e8c7b3..076c046ced 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -40,7 +40,7 @@ int board_init (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1, + gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1, SCB9328_SDRAM_1_SIZE); return 0; From 689d0fa36a7c6dd79f6184d1ded5ca3f8d10d7ad Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 29 Aug 2011 22:49:54 +0000 Subject: [PATCH 059/145] ARM: versatile: drop warnings Drop warning: "passing argument 1 of 'get_ram_size' discards qualifiers from pointer target type" Signed-off-by: Stefano Babic CC: Albert Aribaud --- board/armltd/versatile/versatile.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index ee8cb5e3c7..4a5c31dbf7 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -94,7 +94,7 @@ int misc_init_r (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } From c91e90db8c3f4abbe28d7ec196b2499234ec8d68 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 17 Jul 2011 12:16:29 +0000 Subject: [PATCH 060/145] ARM: remove broken "assabet" board Signed-off-by: Wolfgang Denk Cc: George G. Davis --- MAINTAINERS | 1 - board/assabet/Makefile | 53 ------------ board/assabet/assabet.c | 131 ----------------------------- board/assabet/config.mk | 7 -- board/assabet/setup.S | 136 ------------------------------ boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/assabet.h | 173 -------------------------------------- 8 files changed, 1 insertion(+), 502 deletions(-) delete mode 100644 board/assabet/Makefile delete mode 100644 board/assabet/assabet.c delete mode 100644 board/assabet/config.mk delete mode 100644 board/assabet/setup.S delete mode 100644 include/configs/assabet.h diff --git a/MAINTAINERS b/MAINTAINERS index 7982c3663f..74191ad6aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -632,7 +632,6 @@ Eric Cooper George G. Davis - assabet SA1100 gcplus SA1100 Wolfgang Denk diff --git a/board/assabet/Makefile b/board/assabet/Makefile deleted file mode 100644 index b3cf4aa01c..0000000000 --- a/board/assabet/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# 2004 (c) MontaVista Software, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := assabet.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c deleted file mode 100644 index 753c8d2435..0000000000 --- a/board/assabet/assabet.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* - * Board dependent initialisation - */ - -#define ECOR 0x8000 -#define ECOR_RESET 0x80 -#define ECOR_LEVEL_IRQ 0x40 -#define ECOR_WR_ATTRIB 0x04 -#define ECOR_ENABLE 0x01 - -#define ECSR 0x8002 -#define ECSR_IOIS8 0x20 -#define ECSR_PWRDWN 0x04 -#define ECSR_INT 0x02 -#define SMC_IO_SHIFT 2 -#define NCR_0 (*((volatile u_char *)(0x100000a0))) -#define NCR_ENET_OSC_EN (1<<3) - -static inline u8 -readb(volatile u8 * p) -{ - return *p; -} - -static inline void -writeb(u8 v, volatile u8 * p) -{ - *p = v; -} - -static void -smc_init(void) -{ - u8 ecor; - u8 ecsr; - volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); - - NCR_0 |= NCR_ENET_OSC_EN; - udelay(100); - - ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; - writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); - udelay(100); - - /* - * The device will ignore all writes to the enable bit while - * reset is asserted, even if the reset bit is cleared in the - * same write. Must clear reset first, then enable the device. - */ - writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); - writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); - - /* - * Set the appropriate byte/word mode. - */ - ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; - ecsr |= ECSR_IOIS8; - writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); - udelay(100); -} - -static void -neponset_init(void) -{ - smc_init(); -} - -int -board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_ASSABET; - gd->bd->bi_boot_params = 0xc0000100; - - neponset_init(); - - return 0; -} - -int -dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/assabet/config.mk b/board/assabet/config.mk deleted file mode 100644 index d9866a0eb2..0000000000 --- a/board/assabet/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# SA-1110 based Intel Assabet board -# -# The Intel Assabet 1 bank of 32 MiB SDRAM -# - -CONFIG_SYS_TEXT_BASE = 0xc1f00000 diff --git a/board/assabet/setup.S b/board/assabet/setup.S deleted file mode 100644 index 56ea0dd928..0000000000 --- a/board/assabet/setup.S +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include "config.h" -#include "version.h" - - -/*----------------------------------------------------------------------- - * Board defines: - */ - -#define MDCNFG 0x00 -#define MDCAS00 0x04 -#define MDCAS01 0x08 -#define MDCAS02 0x0C -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 -#define MDREFR 0x1C -#define MDCAS20 0x20 -#define MDCAS21 0x24 -#define MDCAS22 0x28 -#define MSC2 0x2C -#define SMCNFG 0x30 - -#define ASSABET_BCR (0x12000000) -#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) -#define ASSABET_SCR_nNEPONSET (1 << 9) -#define NEPONSET_LEDS (0x10000010) - - -/*----------------------------------------------------------------------- - * Setup parameters for the board: - */ - - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -mdcnfg: .long 0x72547254 -mdcas00: .long 0xaaaaaa7f -mdcas01: .long 0xaaaaaaaa -mdcas02: .long 0xaaaaaaaa -msc0: .long 0x4b384370 -msc1: .long 0x22212419 -mecr: .long 0x994a994a -mdrefr: .long 0x04340327 -mdcas20: .long 0xaaaaaa7f -mdcas21: .long 0xaaaaaaaa -mdcas22: .long 0xaaaaaaaa -msc2: .long 0x42196669 -smcnfg: .long 0x00000000 - -BCR: .long ASSABET_BCR -BCR_DB1110: .long ASSABET_BCR_DB1110 -LEDS: .long NEPONSET_LEDS - - - .globl lowlevel_init -lowlevel_init: - - /* Setting up the memory and stuff */ - - ldr r0, MEM_BASE - ldr r1, mdcas00 - str r1, [r0, #MDCAS00] - ldr r1, mdcas01 - str r1, [r0, #MDCAS01] - ldr r1, mdcas02 - str r1, [r0, #MDCAS02] - ldr r1, mdcas20 - str r1, [r0, #MDCAS20] - ldr r1, mdcas21 - str r1, [r0, #MDCAS21] - ldr r1, mdcas22 - str r1, [r0, #MDCAS22] - ldr r1, mdrefr - str r1, [r0, #MDREFR] - ldr r1, mecr - str r1, [r0, #MECR] - ldr r1, msc0 - str r1, [r0, #MSC0] - ldr r1, msc1 - str r1, [r0, #MSC1] - ldr r1, msc2 - str r1, [r0, #MSC2] - ldr r1, smcnfg - str r1, [r0, #SMCNFG] - - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - - /* Load something to activate bank */ - ldr r2, MEM_START -.rept 8 - ldr r3, [r2] -.endr - - /* Enable SDRAM */ - orr r1, r1, #0x00000001 - str r1, [r0, #MDCNFG] - - ldr r1, BCR - ldr r2, BCR_DB1110 - str r2, [r1] - - ldr r1, LEDS - mov r0, #0x3 - str r0, [r1] - - /* All done... */ - mov pc, lr diff --git a/boards.cfg b/boards.cfg index 413ab9244d..3ab059f5e0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -236,7 +236,6 @@ xm250 arm pxa zipitz2 arm pxa zylonite arm pxa B2 arm s3c44b0 - dave -assabet arm sa1100 dnp1110 arm sa1100 gcplus arm sa1100 jornada arm sa1100 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 4cb727f78b..e2b2596aea 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +assabet arm sa1100 - 2011-07-16 George G. Davis trab arm S3C2400 - 2011-05-01 Gary Jennejohn xsengine ARM PXA2xx 4262a7c 2010-10-20 wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli diff --git a/include/configs/assabet.h b/include/configs/assabet.h deleted file mode 100644 index dc9bd88aca..0000000000 --- a/include/configs/assabet.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2004 (c) MontaVista Software, Inc. - * - * Configuation settings for the Intel Assabet board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ -#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ - -#undef CONFIG_USE_IRQ -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NET_MULTI -#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */ -#define CONFIG_LAN91C96_BASE 0x18000000 - -/* - * select serial console configuration - */ -#define CONFIG_SA1100_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ - -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMSTART -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#if defined(CONFIG_ENV_IS_IN_FLASH) -#define CONFIG_ENV_IN_OWN_SECTOR 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#endif - -#endif /* __CONFIG_H */ From be288570727fe37543a74b8c5469bbbb01a3d980 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:33 +0000 Subject: [PATCH 061/145] ARM: remove broken "armadillo" board Signed-off-by: Wolfgang Denk Cc: Rowel Atienza --- MAINTAINERS | 4 - MAKEALL | 1 - board/armadillo/Makefile | 55 ------ board/armadillo/armadillo.c | 72 ------- board/armadillo/config.mk | 29 --- board/armadillo/flash.c | 340 -------------------------------- board/armadillo/lowlevel_init.S | 66 ------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/armadillo.h | 157 --------------- 10 files changed, 1 insertion(+), 725 deletions(-) delete mode 100644 board/armadillo/Makefile delete mode 100644 board/armadillo/armadillo.c delete mode 100644 board/armadillo/config.mk delete mode 100644 board/armadillo/flash.c delete mode 100644 board/armadillo/lowlevel_init.S delete mode 100644 include/configs/armadillo.h diff --git a/MAINTAINERS b/MAINTAINERS index 74191ad6aa..a37ef42830 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -564,10 +564,6 @@ Albert ARIBAUD edminiv2 ARM926EJS (Orion5x SoC) -Rowel Atienza - - armadillo ARM720T - Stefano Babic ea20 davinci diff --git a/MAKEALL b/MAKEALL index 26685fbfcc..63be39115f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -301,7 +301,6 @@ LIST_SA="$(boards_by_cpu sa1100)" ######################################################################### LIST_ARM7=" \ - armadillo \ B2 \ ep7312 \ evb4510 \ diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile deleted file mode 100644 index 3b524524f9..0000000000 --- a/board/armadillo/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := armadillo.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c deleted file mode 100644 index a825144c5c..0000000000 --- a/board/armadillo/armadillo.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2005 Rowel Atienza - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Activate LED flasher */ - IO_LEDFLSH = 0x40; - - /* arch number MACH_TYPE_ARMADILLO - not official*/ - gd->bd->bi_arch_number = 83; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/armadillo/config.mk b/board/armadillo/config.mk deleted file mode 100644 index ecb8b745cf..0000000000 --- a/board/armadillo/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -#address where u-boot will be relocated -CONFIG_SYS_TEXT_BASE = 0xc0f80000 diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c deleted file mode 100644 index cf7d7f6a64..0000000000 --- a/board/armadillo/flash.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2005 Rowel Atienza - * Flash driver for armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x400000 - -/*value used by hermit is 0x200*/ -/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/ -#define MAIN_SECT_SIZE 0x10000 - -#define UNALIGNED_MASK (3) -#define FL_WORD(addr) (*(volatile unsigned short*)(addr)) -#define FLASH_TIMEOUT 20000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK); - /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */ - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("Fujitsu: "); - break; - default: - printf ("Unknown Vendor "); - break; - } -/* - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } -*/ - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -/* -Done: ; -*/ -} - -/* - * * Loop until both write state machines complete. - * */ -static unsigned short flash_status_wait (unsigned long addr, - unsigned short value) -{ - unsigned short status; - long timeout = FLASH_TIMEOUT; - - while (((status = (FL_WORD (addr))) != value) && timeout > 0) { - timeout--; - } - return status; -} - -/* - * Loop until the Write State machine is ready, then do a full error - * check. Clear status and leave the flash in Read Array mode; return - * 0 for no error, -1 for error. - */ -static int flash_status_full_check (unsigned long addr, unsigned short value1, - unsigned short value2) -{ - unsigned short status1, status2; - - status1 = flash_status_wait (addr, value1); - status2 = flash_status_wait (addr + 2, value2); - return (status1 != value1 || status2 != value2) ? -1 : 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - unsigned long base; - unsigned long addr; - ulong start; - - if ((info->flash_id & FLASH_VENDMASK) != - (FUJ_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first, sect); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - /* ARM simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - - addr = sect * MAIN_SECT_SIZE; - addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */ - base = addr & 0xF0000000; - - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0x80; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (addr) = 0x30; - if (flash_status_full_check (addr, 0xFFFF, 0xFFFF)) - return ERR_PROTECTED; - } - } - printf ("\nDone.\n"); - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - int flag; - unsigned long base; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((FL_WORD (dest) & data) != data) - return ERR_NOT_ERASED; - - /*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */ - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - base = dest & 0xF0000000; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0xA0; - FL_WORD (dest) = data; - /*printf("writing 0x%p = 0x%x\n",dest,data); */ - if (flash_status_wait (dest, data) != data) - return ERR_PROG_ERROR; - - if (flag) - enable_interrupts (); - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - printf ("\nDone.\n"); - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S deleted file mode 100644 index e7d373d274..0000000000 --- a/board/armadillo/lowlevel_init.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Initialization stuff - taken from hermit - * (C) Copyright 2005 Rowel Atienza - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ -/* setting up the memory */ -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0x0000c000 - -.globl lowlevel_init -lowlevel_init: - mov r0, #0x70 /* 32-bit code + data, MMU mandatory */ - mcr p15, 0, r0, c1, c0, 0 /* MMU init */ - - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov r0, #0x80000000 /* I/O base */ - - mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */ - add r2, r0, #0x2200 /* address of SYSCON3 in r2 */ - str r1, [r2] /* set clock speed to 73.728 MHz */ - - mov r1, #0x81 /* 64KHz DRAM refresh period */ - str r1, [r0, #0x200] /* set DRFPR */ - - mov r1, #0x500 /* permanent enable, 16bits wide */ - add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */ - add r2, r0, #0x2300 /* load address in r2 */ - str r1, [r2] - - mov r1, #0x100 /* SDRAM refresh rate */ - add r2, r0, #0x2340 /* load address in r2 */ - str r1, [r2] - - mov sp, #SRAM_START /* init stack pointer */ - add sp, sp, #SRAM_SIZE - - /* everything is fine now */ - mov pc, lr diff --git a/boards.cfg b/boards.cfg index 3ab059f5e0..65205a8455 100644 --- a/boards.cfg +++ b/boards.cfg @@ -42,7 +42,6 @@ imx31_litekit arm arm1136 - logicpd mx35pdk arm arm1136 - freescale mx35 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x -armadillo arm arm720t ep7312 arm arm720t impa7 arm arm720t modnet50 arm arm720t diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e2b2596aea..7c07c2b831 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +armadillo arm arm720t - 2011-07-16 Rowel Atienza assabet arm sa1100 - 2011-07-16 George G. Davis trab arm S3C2400 - 2011-05-01 Gary Jennejohn xsengine ARM PXA2xx 4262a7c 2010-10-20 diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h deleted file mode 100644 index d0d0998d6e..0000000000 --- a/include/configs/armadillo.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the EP7312 board. - * - * Modified to work on Armadillo HT1070 ARM720T board - * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 /* armadillo board */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 - -/* - * select serial console configuration - */ -#define CONFIG_CLPS7111_SERIAL -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" - -#define CONFIG_BOOTCOMMAND "bootm 40000 180000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "ARMADILLO # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ - -#define CONFIG_SYS_HZ 2000 /* decrementer freq: 2 kHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB armadillo SDRAM */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#endif /* __CONFIG_H */ From 5dcf53696fe1eff3daa1884fd154a27f652de25c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:34 +0000 Subject: [PATCH 062/145] ARM: remove broken "B2" board Signed-off-by: Wolfgang Denk Cc: Andrea Scian --- MAINTAINERS | 4 - MAKEALL | 1 - board/dave/B2/B2.c | 139 ---------------------- board/dave/B2/Makefile | 55 --------- board/dave/B2/config.mk | 30 ----- board/dave/B2/flash.c | 76 ------------ board/dave/B2/lowlevel_init.S | 167 -------------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/B2.h | 216 ---------------------------------- 10 files changed, 1 insertion(+), 689 deletions(-) delete mode 100644 board/dave/B2/B2.c delete mode 100644 board/dave/B2/Makefile delete mode 100644 board/dave/B2/config.mk delete mode 100644 board/dave/B2/flash.c delete mode 100644 board/dave/B2/lowlevel_init.S delete mode 100644 include/configs/B2.h diff --git a/MAINTAINERS b/MAINTAINERS index a37ef42830..322334dd5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -845,10 +845,6 @@ Michael Schwingen actux4 xscale/ixp dvlhost xscale/ixp -Andrea Scian - - B2 ARM7TDMI (S3C44B0X) - Nick Thompson da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/MAKEALL b/MAKEALL index 63be39115f..63315fb513 100755 --- a/MAKEALL +++ b/MAKEALL @@ -301,7 +301,6 @@ LIST_SA="$(boards_by_cpu sa1100)" ######################################################################### LIST_ARM7=" \ - B2 \ ep7312 \ evb4510 \ impa7 \ diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c deleted file mode 100644 index 096ebbd16c..0000000000 --- a/board/dave/B2/B2.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialization - */ - -int board_init (void) -{ - u32 temp; - - /* Configuration Port Control Register*/ - /* Port A */ - PCONA = 0x3ff; - - /* Port B */ - PCONB = 0xff; - PDATB = 0xFFFF; - - /* Port C */ - /* - PCONC = 0xff55ff15; - PDATC = 0x0; - PUPC = 0xffff; - */ - - /* Port D */ - /* - PCOND = 0xaaaa; - PUPD = 0xff; - */ - - /* Port E */ - PCONE = 0x0001aaa9; - PDATE = 0x0; - PUPE = 0xff; - - /* Port F */ - PCONF = 0x124955; - PDATF = 0xff; /* B2-eth_reset tied high level */ - /* - PUPF = 0x1e3; - */ - - /* Port G */ - PUPG = 0x1; - PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/ - - INTMSK = 0x03fffeff; - INTCON = 0x05; - - /* - Configure chip ethernet interrupt as High level - Port G EINT 0-7 EINT0 -> CHIP ETHERNET - */ - temp = EXTINT; - temp &= ~0x7; - temp |= 0x1; /*LEVEL_HIGH*/ - EXTINT = temp; - - /* - Reset SMSC LAN91C96 chip - */ - temp= PCONF; - temp |= 0x00000040; - PCONF = temp; - - /* Reset high */ - temp = PDATF; - temp |= (1 << 3); - PDATF = temp; - - /* Short delay */ - for (temp=0;temp<10;temp++) - { - /* NOP */ - } - - /* Reset low */ - temp = PDATF; - temp &= ~(1 << 3); - PDATF = temp; - - /* arch number MACH_TYPE_MBA44B0 */ - gd->bd->bi_arch_number = MACH_TYPE_S3C44B0; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0x0c000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile deleted file mode 100644 index b981579a8e..0000000000 --- a/board/dave/B2/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := B2.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/dave/B2/config.mk b/board/dave/B2/config.mk deleted file mode 100644 index f7b686a1eb..0000000000 --- a/board/dave/B2/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CONFIG_SYS_TEXT_BASE = 0x0C100000 - -PLATFORM_CPPFLAGS += -Uarm diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c deleted file mode 100644 index bb892e6700..0000000000 --- a/board/dave/B2/flash.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifdef __DEBUG_START_FROM_SRAM__ - return CONFIG_SYS_DUMMY_FLASH_SIZE; -#else - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i armadillo arm arm720t - 2011-07-16 Rowel Atienza assabet arm sa1100 - 2011-07-16 George G. Davis trab arm S3C2400 - 2011-05-01 Gary Jennejohn diff --git a/include/configs/B2.h b/include/configs/B2.h deleted file mode 100644 index e181fa88bf..0000000000 --- a/include/configs/B2.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Configuation settings for the B2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_B2 1 /* on an B2 Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ - - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024 ) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */ -#define CONFIG_SMC_USE_32_BIT -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * select serial console configuration - */ -#define CONFIG_S3C44B0_SERIAL -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -#define CONFIG_S3C44B0_I2C -#define CONFIG_RTC_S3C44B0 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#define CONFIG_NET_MULTI -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ETHADDR 00:50:c2:1e:af:fb -#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \ - ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb" -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.70 -#define CONFIG_SERVERIP 192.168.0.23 -#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot" -#define CONFIG_BOOTCOMMAND "bootm 20000 f0000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0C400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x0c700000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* 1 kHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (STM24C02W6) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* Flash banks JFFS2 should use */ -/* -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 2 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -*/ - -/* - Linux TAGs (see arch/arm/lib/armlinux.c) -*/ -#define CONFIG_CMDLINE_TAG -#undef CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#endif /* __CONFIG_H */ From 716f7ade104a9aeed647e19a8b8c9ed9f491359d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:35 +0000 Subject: [PATCH 063/145] ARM: remove broken "edb93xx" boards Remove edb9301, edb9302, edb9302a, edb9307, edb9307a, edb9312, edb9315 and edb9315a boards. Signed-off-by: Wolfgang Denk --- MAKEALL | 8 -- Makefile | 10 -- board/edb93xx/Makefile | 50 ------- board/edb93xx/config.mk | 33 ----- board/edb93xx/early_udelay.h | 34 ----- board/edb93xx/edb93xx.c | 110 -------------- board/edb93xx/flash_cfg.c | 38 ----- board/edb93xx/pll_cfg.c | 58 -------- board/edb93xx/pll_cfg.h | 72 ---------- board/edb93xx/sdram_cfg.c | 146 ------------------- board/edb93xx/sdram_cfg.h | 144 ------------------- doc/README.scrapyard | 8 ++ include/configs/edb93xx.h | 269 ----------------------------------- 13 files changed, 8 insertions(+), 972 deletions(-) delete mode 100644 board/edb93xx/Makefile delete mode 100644 board/edb93xx/config.mk delete mode 100644 board/edb93xx/early_udelay.h delete mode 100644 board/edb93xx/edb93xx.c delete mode 100644 board/edb93xx/flash_cfg.c delete mode 100644 board/edb93xx/pll_cfg.c delete mode 100644 board/edb93xx/pll_cfg.h delete mode 100644 board/edb93xx/sdram_cfg.c delete mode 100644 board/edb93xx/sdram_cfg.h delete mode 100644 include/configs/edb93xx.h diff --git a/MAKEALL b/MAKEALL index 63315fb513..289cd8b169 100755 --- a/MAKEALL +++ b/MAKEALL @@ -318,14 +318,6 @@ LIST_ARM9=" \ aspenite \ da830evm \ da850evm \ - edb9301 \ - edb9302 \ - edb9302a \ - edb9307 \ - edb9307a \ - edb9312 \ - edb9315 \ - edb9315a \ edminiv2 \ guruplug \ imx27lite \ diff --git a/Makefile b/Makefile index 676dc29cfa..6cafb994a2 100644 --- a/Makefile +++ b/Makefile @@ -851,16 +851,6 @@ tx25_config : unconfig @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk @$(MKCONFIG) $@ arm arm926ejs tx25 karo mx25 -edb9301_config \ -edb9302_config \ -edb9302a_config \ -edb9307_config \ -edb9307a_config \ -edb9312_config \ -edb9315_config \ -edb9315a_config: unconfig - @$(MKCONFIG) -n $@ -t $(@:_config=) edb93xx arm arm920t edb93xx - ep93xx - ######################################################################### ## XScale Systems ######################################################################### diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile deleted file mode 100644 index dcaed06b30..0000000000 --- a/board/edb93xx/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk deleted file mode 100644 index fab59ef73c..0000000000 --- a/board/edb93xx/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds - -ifdef CONFIG_EDB9301 -CONFIG_SYS_TEXT_BASE = 0x05700000 -endif - -ifdef CONFIG_EDB9302 -CONFIG_SYS_TEXT_BASE = 0x05700000 -endif - -ifdef CONFIG_EDB9302A -CONFIG_SYS_TEXT_BASE = 0xc5700000 -endif - -ifdef CONFIG_EDB9307 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9307A -CONFIG_SYS_TEXT_BASE = 0xc1f00000 -endif - -ifdef CONFIG_EDB9312 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9315 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9315A -CONFIG_SYS_TEXT_BASE = 0xc1f00000 -endif diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h deleted file mode 100644 index 185283d98d..0000000000 --- a/board/edb93xx/early_udelay.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* delay execution before timers are initialized */ -static inline void early_udelay(uint32_t usecs) -{ - /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ - register uint32_t loops = usecs * (1000 / 20); - - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c deleted file mode 100644 index dde30ffdc2..0000000000 --- a/board/edb93xx/edb93xx.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke - * - * (C) Copyright 2002 2003 - * Network Audio Technologies, Inc. - * Adam Bezanson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MAX_BANK_SIZE 0x04000000 /* 64 MB */ - -static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = { - PHYS_SDRAM_1, -#ifdef PHYS_SDRAM_2 - PHYS_SDRAM_2, -#endif -#ifdef PHYS_SDRAM_3 - PHYS_SDRAM_3, -#endif -#ifdef PHYS_SDRAM_4 - PHYS_SDRAM_4 -#endif -}; - -int board_init(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - - icache_enable(); - -#ifdef USE_920T_MMU - dcache_enable(); -#endif - - /* - * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of - * 14.7456/2 MHz - */ - uint32_t value = readl(&syscon->pwrcnt); - value |= SYSCON_PWRCNT_UART_BAUD; - writel(value, &syscon->pwrcnt); - - /* Enable the uart in devicecfg */ - value = readl(&syscon->devicecfg); - value |= 1<<18 /* U1EN */; - writel(0xAA, &syscon->sysswlock); - writel(value, &syscon->devicecfg); - - /* Machine number, as defined in linux/arch/arm/tools/mach-types */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* We have a console */ - gd->have_console = 1; - - return 0; -} - -int board_eth_init(bd_t *bd) -{ - return ep93xx_eth_initialize(0, MAC_BASE); -} - -int dram_init(void) -{ - unsigned int *src, *dst; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - const ulong bank_size = get_ram_size((long *)bank_addr[i], - MAX_BANK_SIZE); - if (bank_size) { - gd->bd->bi_dram[i].start = bank_addr[i]; - gd->bd->bi_dram[i].size = bank_size; - } - } - - /* copy exception vectors */ - src = (unsigned int *)_armboot_start; - dst = (unsigned int *)PHYS_SDRAM_1; - memcpy(dst, src, 16 * sizeof(unsigned int)); - - return 0; -} diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c deleted file mode 100644 index a4c20486c0..0000000000 --- a/board/edb93xx/flash_cfg.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Flash setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ - SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ - 1 << SMC_BCR_MW_SHIFT) - -void flash_cfg(void) -{ - struct smc_regs *smc = (struct smc_regs *)SMC_BASE; - - writel(SMC_BCR6_VALUE, &smc->bcr6); -} diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c deleted file mode 100644 index a687af0a01..0000000000 --- a/board/edb93xx/pll_cfg.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * PLL setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke - * - * Copyright (C) 2006 Dominic Rath - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "pll_cfg.h" -#include "early_udelay.h" - -void pll_cfg(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - - /* setup PLL1 */ - writel(CLKSET1_VAL, &syscon->clkset1); - - /* - * flush the pipeline - * writing to CLKSET1 causes the EP93xx to enter standby for between - * 8 ms to 16 ms, until PLL1 stabilizes - */ - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - - /* setup PLL2 */ - writel(CLKSET2_VAL, &syscon->clkset2); - - /* - * the user's guide recommends to wait at least 1 ms for PLL2 to - * stabilize - */ - early_udelay(1000); -} diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h deleted file mode 100644 index 0b6f469340..0000000000 --- a/board/edb93xx/pll_cfg.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * PLL register values for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9302A) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 - * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, - * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 - */ -#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ - defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ - defined(CONFIG_EDB9315A) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 - * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, - * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 - */ -#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#else -#error "Undefined board" -#endif - -/* - * usb_div: 4, nbyp2: 1, pll2_en: 1 - * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, - * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 - */ -#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ - SYSCON_CLKSET2_PLL2_EN | \ - SYSCON_CLKSET2_NBYP2 | \ - 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c deleted file mode 100644 index 440ad11fcb..0000000000 --- a/board/edb93xx/sdram_cfg.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2009, 2010 Matthias Kaehlcke - * - * Copyright (C) 2006 Dominic Rath - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "sdram_cfg.h" -#include "early_udelay.h" - -#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) - -#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 - -static void precharge_all_banks(void); -static void setup_refresh_timer(void); -static void program_mode_registers(void); - -void sdram_cfg(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); - - /* Issue continous NOP commands */ - writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - early_udelay(200); - - precharge_all_banks(); - - setup_refresh_timer(); - - program_mode_registers(); - - /* Select normal operation mode */ - writel(GLCONFIG_CKE, &sdram->glconfig); -} - -static void precharge_all_banks(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Issue PRECHARGE ALL commands */ - writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); - - /* - * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always - * issued - * - * Cirrus proposes a workaround which consists in performing a read from - * each bank to force the precharge. This causes some boards to hang. - * Writing to the SDRAM banks instead of reading has the same - * side-effect (the SDRAM controller issues the necessary precharges), - * but is known to work on all supported boards - */ - - PRECHARGE_BANK(0); - -#if (CONFIG_NR_DRAM_BANKS >= 2) - PRECHARGE_BANK(1); -#endif - -#if (CONFIG_NR_DRAM_BANKS >= 3) - PRECHARGE_BANK(2); -#endif - -#if (CONFIG_NR_DRAM_BANKS == 4) - PRECHARGE_BANK(3); -#endif -} - -static void setup_refresh_timer(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Load refresh timer with 10 to issue refresh every 10 cycles */ - writel(0x0a, &sdram->refrshtimr); - - /* - * Wait at least 80 clock cycles to provide 8 refresh cycles - * to all SDRAMs - */ - early_udelay(1); - - /* - * Program refresh timer with normal value - * We need 8192 refresh cycles every 64ms - * at 15ns (HCLK >= 66MHz) per cycle: - * 64ms / 8192 = 7.8125us - * 7.8125us / 15ns = 520 (0x208) - */ - /* - * TODO: redboot uses 0x1e0 for the slowest possible device - * but i don't understand how this value is calculated - */ - writel(0x208, &sdram->refrshtimr); -} - -static void program_mode_registers(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Select mode register update mode */ - writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - /* - * The mode registers are programmed by performing a read from each - * SDRAM bank. The value of the address that is read defines the value - * that is written into the mode register - */ - - PROGRAM_MODE_REG(0); - -#if (CONFIG_NR_DRAM_BANKS >= 2) - PROGRAM_MODE_REG(1); -#endif - -#if (CONFIG_NR_DRAM_BANKS >= 3) - PROGRAM_MODE_REG(2); -#endif - -#if (CONFIG_NR_DRAM_BANKS == 4) - PROGRAM_MODE_REG(3); -#endif -} diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h deleted file mode 100644 index 757b63c256..0000000000 --- a/board/edb93xx/sdram_cfg.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke - * - * Copyright (C) 2006 Dominic Rath - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define SDRAM_BASE_ADDR PHYS_SDRAM_1 - -#ifdef CONFIG_EDB93XX_SDCS0 -#define SDRAM_DEVCFG_REG devcfg0 -#elif defined(CONFIG_EDB93XX_SDCS3) -#define SDRAM_DEVCFG_REG devcfg3 -#else -#error "SDRAM bank configuration" -#endif - -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9302A) -/* - * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 15ns cycle time, we use RAS-to-CAS delay = 2 - * - * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear - * as four blocks of 8MB size, instead of eight blocks of 4MB size: - * - * EDB9301/EDB9302: - * - * 0x00000000 - 0x007fffff - * 0x01000000 - 0x017fffff - * 0x04000000 - 0x047fffff - * 0x05000000 - 0x057fffff - * - * - * EDB9302a: - * - * 0xc0000000 - 0xc07fffff - * 0xc1000000 - 0xc17fffff - * 0xc4000000 - 0xc47fffff - * 0xc5000000 - 0xc57fffff - * - * BANKCOUNT = 1: This is a device with four banks - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2 | \ - SDRAM_DEVCFG_EXTBUSWIDTH) - -/* - * 16 bit ext. bus - * - * A[22:09] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 8 (required for 16 bit ext. bus) - * SYA[13:0] = 0x0023 - */ -#define SDRAM_MODE_REG_VAL 0x4600 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ -#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ -#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ -#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ - -#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ - defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ - defined(CONFIG_EDB9315A) -/* - * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 10ns cycle time, we use RAS-to-CAS delay = 2 - * - * EDB9307, EDB9312, EDB9315: - * - * 0x00000000 - 0x01ffffff - * 0x04000000 - 0x05ffffff - * - * - * EDB9307a, EDB9315a: - * - * 0xc0000000 - 0xc1ffffff - * 0xc4000000 - 0xc5ffffff - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2) - -/* - * 32 bit ext. bus - * - * A[23:10] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 4 - * SYA[13:0] = 0x0022 - */ -#define SDRAM_MODE_REG_VAL 0x8800 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ -#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ -#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ -#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ -#endif diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b734e20950..ed953d36bd 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,14 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +edb9301 arm arm920t - 2011-07-17 +edb9302 arm arm920t - 2011-07-17 +edb9302a arm arm920t - 2011-07-17 +edb9307 arm arm920t - 2011-07-17 +edb9307a arm arm920t - 2011-07-17 +edb9312 arm arm920t - 2011-07-17 +edb9315 arm arm920t - 2011-07-17 +edb9315a arm arm920t - 2011-07-17 B2 arm s3c44b0 - 2011-07-16 Andrea Scian armadillo arm arm720t - 2011-07-16 Rowel Atienza assabet arm sa1100 - 2011-07-16 George G. Davis diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h deleted file mode 100644 index 19b76321e6..0000000000 --- a/include/configs/edb93xx.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * U-boot - Configuration file for Cirrus Logic EDB93xx boards - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_edb9301 -#define CONFIG_EDB9301 -#elif defined(CONFIG_edb9302) -#define CONFIG_EDB9302 -#elif defined(CONFIG_edb9302a) -#define CONFIG_EDB9302A -#elif defined(CONFIG_edb9307) -#define CONFIG_EDB9307 -#elif defined(CONFIG_edb9307a) -#define CONFIG_EDB9307A -#elif defined(CONFIG_edb9312) -#define CONFIG_EDB9312 -#elif defined(CONFIG_edb9315) -#define CONFIG_EDB9315 -#elif defined(CONFIG_edb9315a) -#define CONFIG_EDB9315A -#else -#error "no board defined" -#endif - -/* Initial environment and monitor configuration options. */ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" -#define CONFIG_BOOTFILE "edb93xx.img" - -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#ifdef CONFIG_EDB9301 -#define CONFIG_EP9301 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 -#define CONFIG_SYS_PROMPT "EDB9301> " -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9302) -#define CONFIG_EP9302 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 -#define CONFIG_SYS_PROMPT "EDB9302> " -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9302A) -#define CONFIG_EP9302 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A -#define CONFIG_SYS_PROMPT "EDB9302A> " -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9307) -#define CONFIG_EP9307 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 -#define CONFIG_SYS_PROMPT "EDB9307> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9307A) -#define CONFIG_EP9307 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A -#define CONFIG_SYS_PROMPT "EDB9307A> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9312) -#define CONFIG_EP9312 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 -#define CONFIG_SYS_PROMPT "EDB9312> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9315) -#define CONFIG_EP9315 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 -#define CONFIG_SYS_PROMPT "EDB9315> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9315A) -#define CONFIG_EP9315 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A -#define CONFIG_SYS_PROMPT "EDB9315A> " -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#else -#error "no board defined" -#endif - -/* High-level configuration options */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ -#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ - -#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ -#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ -#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ - -/* Monitor configuration */ -#include -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -#undef CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 - -#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -/* Print buffer size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* Boot argument buffer size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ - -/* Serial port hardware configuration */ -#define CONFIG_PL010_SERIAL -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_SERIAL0 0x808C0000 -#define CONFIG_SYS_SERIAL1 0x808D0000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} - -/* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_GREEN 0 -#define STATUS_LED_RED 1 -/* Green */ -#define STATUS_LED_BIT STATUS_LED_GREEN -#define STATUS_LED_STATE STATUS_LED_ON -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Red */ -#define STATUS_LED_BIT1 STATUS_LED_RED -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -/* Network hardware configuration */ -#define CONFIG_DRIVER_EP93XX_MAC -#define CONFIG_MII_SUPPRESS_PREAMBLE -#define CONFIG_MII -#define CONFIG_PHY_ADDR 1 -#define CONFIG_NET_MULTI -#undef CONFIG_NETCONSOLE - -/* SDRAM configuration */ -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) -/* - * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set - * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_SIZE_1 0x00800000 -#define PHYS_SDRAM_2 0x01000000 -#define PHYS_SDRAM_SIZE_2 0x00800000 -#define PHYS_SDRAM_3 0x04000000 -#define PHYS_SDRAM_SIZE_3 0x00800000 -#define PHYS_SDRAM_4 0x05000000 -#define PHYS_SDRAM_SIZE_4 0x00800000 -#define CONFIG_EDB93XX_SDCS3 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x007fffff - -#elif defined(CONFIG_EDB9302A) -/* - * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set - * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0xc0000000 -#define PHYS_SDRAM_SIZE_1 0x00800000 -#define PHYS_SDRAM_2 0xc1000000 -#define PHYS_SDRAM_SIZE_2 0x00800000 -#define PHYS_SDRAM_3 0xc4000000 -#define PHYS_SDRAM_SIZE_3 0x00800000 -#define PHYS_SDRAM_4 0xc5000000 -#define PHYS_SDRAM_SIZE_4 0x00800000 -#define CONFIG_EDB93XX_SDCS0 -#define CONFIG_SYS_MEMTEST_START 0xc0100000 -#define CONFIG_SYS_MEMTEST_END 0xc07fffff - -#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ - defined(CONFIG_EDB9315) -/* - * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of - * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of - * 64 MB of SDRAM. - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_SIZE_1 0x02000000 -#define PHYS_SDRAM_2 0x04000000 -#define PHYS_SDRAM_SIZE_2 0x02000000 -#define CONFIG_EDB93XX_SDCS3 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01e00000 - -#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) -/* - * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung - * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0xc0000000 -#define PHYS_SDRAM_SIZE_1 0x02000000 -#define PHYS_SDRAM_2 0xc4000000 -#define PHYS_SDRAM_SIZE_2 0x02000000 -#define CONFIG_EDB93XX_SDCS0 -#define CONFIG_SYS_MEMTEST_START 0xc0100000 -#define CONFIG_SYS_MEMTEST_END 0xc1e00000 -#endif - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000) - -/* Must match kernel config */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) - -/* Run-time memory allocatons */ -#define CONFIG_STACKSIZE (128 * 1024) - -#if defined(CONFIG_USE_IRQ) -#define CONFIG_STACKSIZE_IRQ (4 * 1024) -#define CONFIG_STACKSIZE_FIQ (4 * 1024) -#endif - -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* ----------------------------------------------------------------------------- - * FLASH and environment organization - * - * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000 - * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus, - * for a total of 16 MB of CFI-compatible flash. - * - * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at - * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit - * data bus, for a total of 32 MB of CFI-compatible flash. - * - * EDB9301/02(a) EDB9307(a)/12/15(a) - * 0x60000000 - 0x0003FFFF u-boot u-boot - * 0x60040000 - 0x0005FFFF environment #1 environment #1 - * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) - * 0x60080000 - 0x0009FFFF unused environment #2 - * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) - * 0x600C0000 - 0x00FFFFFF unused unused - * 0x61000000 - 0x01FFFFFF not present unused - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define PHYS_FLASH_1 0x60000000 -#define CONFIG_SYS_FLASH_BASE (PHYS_FLASH_1) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x60040000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) - -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#endif /* !defined (__CONFIG_H) */ From 957731eda0fe7610de93f73ef54686a618dbc605 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:36 +0000 Subject: [PATCH 064/145] ARM: remove broken "lpd7a40x" boards Remove lpd7a400 and lpd7a404 boards. Signed-off-by: Wolfgang Denk --- MAKEALL | 1 - board/lpd7a40x/Makefile | 51 ---- board/lpd7a40x/config.mk | 38 --- board/lpd7a40x/flash.c | 490 --------------------------------- board/lpd7a40x/lowlevel_init.S | 212 -------------- board/lpd7a40x/lpd7a40x.c | 93 ------- boards.cfg | 2 - doc/README.scrapyard | 1 + include/configs/lpd7a400-10.h | 80 ------ include/configs/lpd7a400.h | 117 -------- include/configs/lpd7a404-10.h | 80 ------ include/configs/lpd7a404.h | 117 -------- 12 files changed, 1 insertion(+), 1281 deletions(-) delete mode 100644 board/lpd7a40x/Makefile delete mode 100644 board/lpd7a40x/config.mk delete mode 100644 board/lpd7a40x/flash.c delete mode 100644 board/lpd7a40x/lowlevel_init.S delete mode 100644 board/lpd7a40x/lpd7a40x.c delete mode 100644 include/configs/lpd7a400-10.h delete mode 100644 include/configs/lpd7a400.h delete mode 100644 include/configs/lpd7a404-10.h delete mode 100644 include/configs/lpd7a404.h diff --git a/MAKEALL b/MAKEALL index 289cd8b169..1f6baba7e7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -323,7 +323,6 @@ LIST_ARM9=" \ imx27lite \ jadecpu \ km_kirkwood \ - lpd7a400 \ magnesium \ mv88f6281gtw_ge \ mx1ads \ diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile deleted file mode 100644 index 3aeb2fb1ad..0000000000 --- a/board/lpd7a40x/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := lpd7a40x.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/lpd7a40x/config.mk b/board/lpd7a40x/config.mk deleted file mode 100644 index 003e70740f..0000000000 --- a/board/lpd7a40x/config.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine -# w/Sharp LH7A400 SoC (ARM920T) cpu -# - -# -# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000 -# -# Linux-Kernel is @ 0xC0008000, entry 0xc0008000 -# params @ 0xc0000100 -# optionally with a ramdisk at 0xc0300000 -# -# we load ourself to 0xc1fc0000 (32M - 256K) -# -# download area is 0xc0f00000 -# - -CONFIG_SYS_TEXT_BASE = 0xc1fc0000 -#CONFIG_SYS_TEXT_BASE = 0x00000000 diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c deleted file mode 100644 index f5c07135dc..0000000000 --- a/board/lpd7a40x/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#define FLASH_BANK_SIZE 0x1000000 /* 16MB (2 x 8 MB) */ -#define MAIN_SECT_SIZE 0x40000 /* 256KB (2 x 128kB) */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S deleted file mode 100644 index de34fc6f04..0000000000 --- a/board/lpd7a40x/lowlevel_init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Memory Setup - initialize memory controller(s) for devices required - * to boot and relocate - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* memory controller */ -#define BCRX_DEFAULT (0x0000fbe0) -#define BCRX_MW_8 (0x00000000) -#define BCRX_MW_16 (0x10000000) -#define BCRX_MW_32 (0x20000000) -#define BCRX_PME (0x08000000) -#define BCRX_WP (0x04000000) -#define BCRX_WST2_SHIFT (11) -#define BCRX_WST1_SHIFT (5) -#define BCRX_IDCY_SHIFT (0) - -/* Bank0 Async Flash */ -#define BCR0 (0x80002000) -#define BCR0_FLASH (BCRX_MW_32 | (0x08< - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#if defined(CONFIG_LH7A400) -#include -#elif defined(CONFIG_LH7A404) -#include -#else -#error "No CPU defined!" -#endif -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* set up the I/O ports */ - - /* enable flash programming */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN; - - /* Auto wakeup, LCD disable, WLAN enable */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &= - ~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE); - - /* Status LED 2 on (leds are active low) */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) = - (EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2); - -#if defined(CONFIG_LH7A400) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A400; -#elif defined(CONFIG_LH7A404) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A404; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 409a6db2a4..a5af6bf8ac 100644 --- a/boards.cfg +++ b/boards.cfg @@ -212,8 +212,6 @@ actux4 arm ixp dvlhost arm ixp ixdp425 arm ixp ixdpg425 arm ixp ixdp425 -lpd7a400 arm lh7a40x lpd7a40x -lpd7a404 arm lh7a40x lpd7a40x balloon3 arm pxa cerf250 arm pxa colibri_pxa270 arm pxa diff --git a/doc/README.scrapyard b/doc/README.scrapyard index ed953d36bd..4cf2717267 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +lpd7a404 arm lh7a40x - 2011-07-17 edb9301 arm arm920t - 2011-07-17 edb9302 arm arm920t - 2011-07-17 edb9302a arm arm920t - 2011-07-17 diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h deleted file mode 100644 index 91bf1fabdd..0000000000 --- a/include/configs/lpd7a400-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A400_10_H -#define __LPD7A400_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A400 1 /* Sharp LH7A400 S0C */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CONFIG_SYS_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT - -#endif /* __LPD7A400_10_H */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h deleted file mode 100644 index 06f3d7e58f..0000000000 --- a/include/configs/lpd7a400.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A400_H_ -#define __LPD7A400_H_ - -#define CONFIG_LPD7A400 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A400-10 card engine - */ -#include - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * select serial console configuration - */ -#define CONFIG_LH7A40X_SERIAL -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#ifndef USE_920T_MMU - #define CONFIG_CMD_PING - #undef CONFIG_CMD_CACHE -#else - #define CONFIG_CMD_DATE -#endif - - -#define CONFIG_BOOTDELAY 3 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "LPD7A400> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256<<10) - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xFC0000) -#define CONFIG_ENV_SIZE 0x40000 - -#endif /* __LPD7A400_H_ */ diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h deleted file mode 100644 index b10e69d237..0000000000 --- a/include/configs/lpd7a404-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A404_10_H -#define __LPD7A404_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CONFIG_SYS_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT - -#endif /* __LPD7A404_10_H */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h deleted file mode 100644 index 7535f62d3d..0000000000 --- a/include/configs/lpd7a404.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A404_H_ -#define __LPD7A404_H_ - -#define CONFIG_LPD7A404 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A404-10 card engine - */ -#include - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * select serial console configuration - */ -#define CONFIG_LH7A40X_SERIAL -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#ifndef USE_920T_MMU - #define CONFIG_CMD_PING - #undef CONFIG_CMD_CACHE -#else - #define CONFIG_CMD_DATE -#endif - - -#define CONFIG_BOOTDELAY 3 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "LPD7A404> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256<<10) - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xFC0000) -#define CONFIG_ENV_SIZE 0x40000 - -#endif /* __LPD7A404_H_ */ From 69624195a3678b78569addf739b58275ae39460a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:37 +0000 Subject: [PATCH 065/145] ARM: remove broken "mx1fs2" board Signed-off-by: Wolfgang Denk --- MAKEALL | 1 - board/mx1fs2/Makefile | 51 --- board/mx1fs2/config.mk | 10 - board/mx1fs2/flash.c | 849 ----------------------------------- board/mx1fs2/intel.h | 99 ---- board/mx1fs2/lowlevel_init.S | 188 -------- board/mx1fs2/mx1fs2.c | 122 ----- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/mx1fs2.h | 305 ------------- 10 files changed, 1 insertion(+), 1626 deletions(-) delete mode 100644 board/mx1fs2/Makefile delete mode 100644 board/mx1fs2/config.mk delete mode 100644 board/mx1fs2/flash.c delete mode 100644 board/mx1fs2/intel.h delete mode 100644 board/mx1fs2/lowlevel_init.S delete mode 100644 board/mx1fs2/mx1fs2.c delete mode 100644 include/configs/mx1fs2.h diff --git a/MAKEALL b/MAKEALL index 1f6baba7e7..8eaa0d5ac9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -326,7 +326,6 @@ LIST_ARM9=" \ magnesium \ mv88f6281gtw_ge \ mx1ads \ - mx1fs2 \ netstar \ nhk8815 \ nhk8815_onenand \ diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile deleted file mode 100644 index c55b695a51..0000000000 --- a/board/mx1fs2/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx1fs2.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk deleted file mode 100644 index eb4d046939..0000000000 --- a/board/mx1fs2/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of IMX sources -# -# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -CONFIG_SYS_TEXT_BASE = 0x08f00000 diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c deleted file mode 100644 index da4ebe6e75..0000000000 --- a/board/mx1fs2/flash.c +++ /dev/null @@ -1,849 +0,0 @@ -/* - * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) 2003 August Hoeraendl, Logotronic GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef CONFIG_FLASH_16BIT - -#include - -#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE -#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -#if 0 -static ulong flash_get_size(FPWV * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -#endif -static void flash_reset(flash_info_t * info); -static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); -#define write_word(in, de, da) write_word_amd(in, de, da) -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -ulong -flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = MX1FS2_FLASH_BASE; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_reset(flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void -flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ - -void -flash_print_info(flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf(fmt, bootletter, boottype); - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf("\n "); - } - - printf(" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -#if 0 -ulong -flash_get_size(FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} -#endif /* 0 */ - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void -flash_sync_real_protect(flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int -flash_erase(flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay(1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf(" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int -bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int -write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* handle unaligned start bytes */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* handle word aligned part */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((FPW *) src); - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - src += sizeof (FPW); - wp += sizeof (FPW); - cnt -= sizeof (FPW); - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word(info, (FPWV *)wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_amd(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - printf("SHA timeout\n"); - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_intel(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int -flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset(info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset(info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h deleted file mode 100644 index 8db5dd4f64..0000000000 --- a/board/mx1fs2/intel.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Written by Marcel Telka , 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S deleted file mode 100644 index 56a4819b08..0000000000 --- a/board/mx1fs2/lowlevel_init.S +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - * 02111-1307, USA. - * - */ - -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* Change PERCLK1DIV to 14 ie 14+1 */ - ldr r0, =PCDR - ldr r1, =CONFIG_SYS_PCDR_VAL - str r1, [r0] - -/* set MCU PLL Control Register 0 */ - - ldr r0, =MPCTL0 - ldr r1, =CONFIG_SYS_MPCTL0_VAL - str r1, [r0] - -/* set MCU PLL Control Register 1 */ - - ldr r0, =MPCTL1 - ldr r1, =CONFIG_SYS_MPCTL1_VAL - str r1, [r0] - -/* set mpll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<21) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - -/* set System PLL Control Register 0 */ - - ldr r0, =SPCTL0 - ldr r1, =CONFIG_SYS_SPCTL0_VAL - str r1, [r0] - -/* set System PLL Control Register 1 */ - - ldr r0, =SPCTL1 - ldr r1, =CONFIG_SYS_SPCTL1_VAL - str r1, [r0] - -/* set spll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<22) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - - ldr r0, =CSCR - ldr r1, =CONFIG_SYS_CSCR_VAL - str r1, [r0] - - ldr r0, =GPCR - ldr r1, =CONFIG_SYS_GPCR_VAL - str r1, [r0] - -/* - * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - * this..... - * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 - * register 1, this stops it using the output of the PLL and thus runs at the - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never - * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - * - * Slapping this into my bootloader does the trick... - * - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register - * - */ - MRC p15,0,r0,c1,c0,0 -/* ORR r0,r0,#0xC0000000 async mode */ -/* ORR r0,r0,#0x40000000 sync mode */ - ORR r0,r0,#0xC0000000 - MCR p15,0,r0,c1,c0,0 - - ldr r0, =GIUS(0) - ldr r1, =CONFIG_SYS_GIUS_A_VAL - str r1, [r0] - - ldr r0, =FMCR - ldr r1, =CONFIG_SYS_FMCR_VAL - str r1, [r0] - - ldr r0, =CS0U - ldr r1, =CONFIG_SYS_CS0U_VAL - str r1, [r0] - - ldr r0, =CS0L - ldr r1, =CONFIG_SYS_CS0L_VAL - str r1, [r0] - - ldr r0, =CS1U - ldr r1, =CONFIG_SYS_CS1U_VAL - str r1, [r0] - - ldr r0, =CS1L - ldr r1, =CONFIG_SYS_CS1L_VAL - str r1, [r0] - - ldr r0, =CS4U - ldr r1, =CONFIG_SYS_CS4U_VAL - str r1, [r0] - - ldr r0, =CS4L - ldr r1, =CONFIG_SYS_CS4L_VAL - str r1, [r0] - - ldr r0, =CS5U - ldr r1, =CONFIG_SYS_CS5U_VAL - str r1, [r0] - - ldr r0, =CS5L - ldr r1, =CONFIG_SYS_CS5L_VAL - str r1, [r0] - -/* SDRAM Setup */ - - ldr r1,=0x00221000 /* adr of SDCTRL0 */ - ldr r0,=0x92120200 - str r0,[r1,#0] /* put in precharge command mode */ - ldr r2,=0x08200000 /* adr for precharge cmd */ - ldr r0,[r2,#0] /* precharge */ - ldr r0,=0xA2120200 - ldr r2,=0x08000000 /* start of SDRAM */ - str r0,[r1,#0] /* put in auto-refresh mode */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,=0xB2120200 - ldr r2,=0x08111800 - str r0,[r1,#0] /* setup for mode register of SDRAM */ - ldr r0,[r2,#0] /* program mode register */ - ldr r0,=0x82124267 - str r0,[r1,#0] /* back to normal operation */ - - mov pc,r10 diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c deleted file mode 100644 index 90a33c2499..0000000000 --- a/board/mx1fs2/mx1fs2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) - -extern void imx_gpio_mode(int gpio_mode); - -static void logo_init(void) -{ - imx_gpio_mode(PD15_PF_LD0); - imx_gpio_mode(PD16_PF_LD1); - imx_gpio_mode(PD17_PF_LD2); - imx_gpio_mode(PD18_PF_LD3); - imx_gpio_mode(PD19_PF_LD4); - imx_gpio_mode(PD20_PF_LD5); - imx_gpio_mode(PD21_PF_LD6); - imx_gpio_mode(PD22_PF_LD7); - imx_gpio_mode(PD23_PF_LD8); - imx_gpio_mode(PD24_PF_LD9); - imx_gpio_mode(PD25_PF_LD10); - imx_gpio_mode(PD26_PF_LD11); - imx_gpio_mode(PD27_PF_LD12); - imx_gpio_mode(PD28_PF_LD13); - imx_gpio_mode(PD29_PF_LD14); - imx_gpio_mode(PD30_PF_LD15); - imx_gpio_mode(PD14_PF_FLM_VSYNC); - imx_gpio_mode(PD13_PF_LP_HSYNC); - imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR); - imx_gpio_mode(PD11_PF_CONTRAST); - imx_gpio_mode(PD10_PF_SPL_SPR); - - LCDC_RMCR = 0x00000000; - LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5); - LCDC_HCR = HCR_H_WIDTH(2); - LCDC_VCR = VCR_V_WIDTH(2); - - LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */ - LCDC_SSA = 0x10040000; /* image in flash */ - - LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */ - - LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */ - LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ - - /* disable Cursor */ - LCDC_CPOS = 0x00000000; - - /* fixed burst length */ - LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2); - - /* enable LCD */ - DR(3) |= 0x00001000; - LCDC_RMCR = RMCR_LCDC_EN; - -} - -int -board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX1FS2; - gd->bd->bi_boot_params = 0x08000100; -serial_init(); - logo_init(); - return 0; -} - -int -dram_init(void) -{ -#if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1; - gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE; -#endif - return 0; -} - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - */ - -void -show_boot_progress(int status) -{ - /* We use this as a hook to disable serial ports just before booting - * This way we suppress the "uncompressing linux..." message - */ -#ifdef CONFIG_SILENT_CONSOLE - if( status == 8) { - if( getenv("silent") != NULL ) { - *(volatile unsigned long *)0x206080 &= ~1; - *(volatile unsigned long *)0x207080 &= ~1; - } - } -#endif - return; -} diff --git a/boards.cfg b/boards.cfg index a5af6bf8ac..6c7775d70e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -63,7 +63,6 @@ kb9202 arm arm920t - - m501sk arm arm920t - - at91rm9200 at91rm9200dk arm arm920t - atmel at91rm9200 mx1ads arm arm920t - - imx -mx1fs2 arm arm920t - - imx scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 4cf2717267..8d04db6b82 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +mx1fs2 arm arm920t - 2011-07-17 lpd7a404 arm lh7a40x - 2011-07-17 edb9301 arm arm920t - 2011-07-17 edb9302 arm arm920t - 2011-07-17 diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h deleted file mode 100644 index ddbc65afa2..0000000000 --- a/include/configs/mx1fs2.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ -#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */ -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ - -/* - * Select serial console configuration - */ -#undef _CONFIG_UART1 /* internal uart 1 */ -#define _CONFIG_UART2 /* internal uart 2 */ -#undef _CONFIG_UART3 /* internal uart 3 */ -#undef _CONFIG_UART4 /* internal uart 4 */ -#undef CONFIG_SILENT_CONSOLE /* use this to disable output */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 - -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING -#undef CONFIG_CMD_SOURCE - -/* - * Boot options. Setting delay to -1 stops autostart count down. - */ -#define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND "bootm 10080000" -#define CONFIG_SHOW_BOOT_PROGRESS - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CONFIG_SYS_LONGHELP /* undef saves memory */ -#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */ -#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 16 /* max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ - -#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0x08F00000 - -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* send initrd params */ - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) - -#define CONFIG_STACKSIZE (120<<10) /* stack size */ - -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ -#endif - -/* SDRAM Setup Values - * 0x910a8300 Precharge Command CAS 3 - * 0x910a8200 Precharge Command CAS 2 - * - * 0xa10a8300 AutoRefresh Command CAS 3 - * 0xa10a8200 Set AutoRefresh Command CAS 2 - */ -#define PRECHARGE_CMD 0x910a8300 -#define AUTOREFRESH_CMD 0xa10a8300 - -#define BUS32BIT_VERSION -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */ -#ifdef BUS32BIT_VERSION -#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */ -#else -#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */ -#endif -/* - * Flash Controller settings - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ - -#ifdef BUS32BIT_VERSION -#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ -#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ -#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/ -#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#else -#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/ -#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */ -#endif -#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */ -#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CONFIG_SYS_FLASH_CFI - -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ - -#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -/* -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00050000 -*/ - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=mx1fs2-0" - -#ifdef BUS32BIT_VERSION -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)" -#else -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)" -#endif - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -#define CONFIG_SYS_MONITOR_BASE 0x10000000 -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ - -/* Setup CS4 and CS5 */ -#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe - -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ - -#define CONFIG_SYS_CS0U_VAL 0x00008C00 -#define CONFIG_SYS_CS0L_VAL 0x22222601 -#define CONFIG_SYS_CS1U_VAL 0x00008C00 -#define CONFIG_SYS_CS1L_VAL 0x22222301 -#define CONFIG_SYS_CS4U_VAL 0x00008C00 -#define CONFIG_SYS_CS4L_VAL 0x22222301 -#define CONFIG_SYS_CS5U_VAL 0x00008C00 -#define CONFIG_SYS_CS5L_VAL 0x22222301 - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD -#define CONFIG_SYS_MPCTL1_VAL 0x00000040 -#define CONFIG_SYS_PCDR_VAL 0x00010005 -#define CONFIG_SYS_GPCR_VAL 0x00000FFB - -#define USE_16M_OSZI /* If you have one, you want to use it - The internal 32kHz oszillator jitters */ -#ifdef USE_16M_OSZI - -#define CONFIG_SYS_SPCTL0_VAL 0x04001401 -#define CONFIG_SYS_SPCTL1_VAL 0x0C000040 -#define CONFIG_SYS_CSCR_VAL 0x07030003 -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16000000 - -#else - -#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1 -#define CONFIG_SYS_CSCR_VAL 0x06000003 -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16780000 - -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CONFIG_SYS_LOAD_ADDR 0x08400000 - -#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */ - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef _CONFIG_UART1 -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL1 -#elif defined _CONFIG_UART2 -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL2 -#elif defined _CONFIG_UART3 | defined _CONFIG_UART4 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 3686400 -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_CONS_INDEX 1 -#ifdef _CONFIG_UART3 -#define CONFIG_SYS_NS16550_COM1 0x15000000 -#elif defined _CONFIG_UART4 -#define CONFIG_SYS_NS16550_COM1 0x16000000 -#endif -#endif - -#endif /* __CONFIG_H */ From 6ea24054897b5061efd9888989e6776b60d372af Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:38 +0000 Subject: [PATCH 066/145] ARM: remove broken "netstar" board Signed-off-by: Wolfgang Denk --- MAKEALL | 1 - Makefile | 1 - board/netstar/Makefile | 95 ------------- board/netstar/config.mk | 11 -- board/netstar/crcek.S | 241 -------------------------------- board/netstar/crcek.h | 3 - board/netstar/crcit.c | 87 ------------ board/netstar/eeprom.c | 218 ----------------------------- board/netstar/netstar.c | 129 ----------------- board/netstar/setup.S | 284 -------------------------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/netstar.h | 245 -------------------------------- 13 files changed, 1 insertion(+), 1316 deletions(-) delete mode 100644 board/netstar/Makefile delete mode 100644 board/netstar/config.mk delete mode 100644 board/netstar/crcek.S delete mode 100644 board/netstar/crcek.h delete mode 100644 board/netstar/crcit.c delete mode 100644 board/netstar/eeprom.c delete mode 100644 board/netstar/netstar.c delete mode 100644 board/netstar/setup.S delete mode 100644 include/configs/netstar.h diff --git a/MAKEALL b/MAKEALL index 8eaa0d5ac9..ce987e89cc 100755 --- a/MAKEALL +++ b/MAKEALL @@ -326,7 +326,6 @@ LIST_ARM9=" \ magnesium \ mv88f6281gtw_ge \ mx1ads \ - netstar \ nhk8815 \ nhk8815_onenand \ omap1510inn \ diff --git a/Makefile b/Makefile index 6cafb994a2..699a752b49 100644 --- a/Makefile +++ b/Makefile @@ -932,7 +932,6 @@ clean: $(obj)tools/ncb $(obj)tools/ubsha1 @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ $(obj)board/matrix_vision/*/bootscript.img \ - $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/voiceblue/eeprom \ $(obj)u-boot.lds \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ diff --git a/board/netstar/Makefile b/board/netstar/Makefile deleted file mode 100644 index 7230a2f88a..0000000000 --- a/board/netstar/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := netstar.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -LOAD_ADDR = 0x10400000 - -######################################################################### - -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -$(obj)eeprom_start.o: - echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - - -$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o - $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ - -L$(obj)../../examples/standalone -lstubs \ - $(PLATFORM_LIBS) - -$(obj)eeprom.srec: $(obj)eeprom - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)eeprom.bin: $(obj)eeprom - $(OBJCOPY) -S -O binary $< $@ - -$(obj)crcek.srec: $(obj)crcek.o - $(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^ - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)crcek.bin: $(obj)crcek.srec - $(OBJCOPY) -I srec -O binary $< $@ - -$(obj)crcit: $(obj)crcit.o $(obj)crc32.o - $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ - -$(obj)crcit.o: crcit.c - $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $< - -$(obj)crc32.o: $(SRCTREE)/lib/crc32.c - $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \ - -o $@ -c $< - -clean: - rm -f $(SOBJS) $(OBJS) \ - $(obj)eeprom_start.o $(obj)eeprom.o \ - $(obj)eeprom $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netstar/config.mk b/board/netstar/config.mk deleted file mode 100644 index 9e1446e4b6..0000000000 --- a/board/netstar/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Linux-Kernel is expected to be at 1000'8000, -# entry 1000'8000 (mem base + reserved) -# -# We load ourself to internal RAM at 2001'2000 -# Check map file when changing CONFIG_SYS_TEXT_BASE. -# Everything has fit into 192kB internal SRAM! -# - -# XXX CONFIG_SYS_TEXT_BASE = 0x20012000 -CONFIG_SYS_TEXT_BASE = 0x13FC0000 diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S deleted file mode 100644 index af35662187..0000000000 --- a/board/netstar/crcek.S +++ /dev/null @@ -1,241 +0,0 @@ -/** - * (C) Copyright 2005 - * 2N Telekomunikace, Ladislav Michl - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2. - * - * Image layout looks like following: - * u32 - size - * u32 - version - * ... - data - * u32 - crc32 - */ - -#include -#include "crcek.h" - -/** - * do_crc32 - calculate CRC32 of given buffer - * r0 - crc - * r1 - pointer to buffer - * r2 - buffer len - */ - .macro do_crc32 - ldr r5, FFFFFFFF - eor r0, r0, r5 - adr r3, CRC32_TABLE -1: - ldrb r4, [r1], #1 - eor r4, r4, r0 - and r4, r4, #0xff - ldr r4, [r3, r4, lsl#2] - eor r0, r4, r0, lsr#8 - subs r2, r2, #0x1 - bne 1b - eor r0, r0, r5 - .endm - - .macro crcuj, offset, size - mov r0, #0 - ldr r1, \offset - ldr r2, [r1], #4 - cmp r2, r0 @ no data, no problem - beq 2f - tst r2, #3 @ unaligned size - bne 2f - ldr r3, \size - cmp r2, r3 @ bogus size - bhi 2f - do_crc32 - ldr r1, [r1] -2: - cmp r0, r1 - .endm - - .macro wait, reg - mov \reg, #0x100000 -3: - subs \reg, \reg, #0x1 - bne 3b - .endm - -.text -.globl crcek -crcek: - /* Enable I-cache */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 -loop: - cmp r2, #1 @ this loop will wait for at least 100 cycles - streqh r1, [r0, #0x18] @ before issuing next request from MPU - add r2, r2, #1 @ on the 1st run code is loaded into I-cache - cmp r2, #16 @ and second run will set clocking mode - bne loop - nop - - /* Setup clock dividers */ - ldr r1, CKCTL_VAL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, EN_CLK_VAL - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) - - - mov r6, #0 - crcuj _LOADER1_OFFSET, _LOADER_SIZE - bne crc1_bad - orr r6, r6, #1 -crc1_bad: - crcuj _LOADER2_OFFSET, _LOADER_SIZE - bne crc2_bad - orr r6, r6, #2 -crc2_bad: - ldr r3, _LOADER1_OFFSET - ldr r4, _LOADER2_OFFSET - teq r6, #3 - bne one_is_bad @ one of them (or both) has bad crc - ldr r1, [r3, #4] - ldr r2, [r4, #4] - cmp r1, r2 @ boot 2nd loader if versions differ - beq boot_1st - b boot_2nd -one_is_bad: - tst r6, #1 - bne boot_1st - tst r6, #2 - bne boot_2nd -@ We are doomed, so let user know. -hell: - ldr r0, GPIO_BASE @ configure GPIO pins - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] -blink_loop: - mov r1, #0x08 - strh r1, [r0, #0x04] - wait r3 - mov r1, #0x10 - strh r1, [r0, #0x04] - wait r3 - b blink_loop -boot_1st: - add pc, r3, #8 -boot_2nd: - add pc, r4, #8 - -_LOADER_SIZE: - .word LOADER_SIZE - 8 @ minus size and crc32 -_LOADER1_OFFSET: - .word LOADER1_OFFSET -_LOADER2_OFFSET: - .word LOADER2_OFFSET - -FFFFFFFF: - .word 0xffffffff -CRC32_TABLE: - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b - .word 0x2d02ef8d - -GPIO_BASE: - .word 0xfffce000 -MPU_CLKM_BASE: - .word 0xfffece00 -DPLL1_BASE: - .word 0xfffecf00 - -CKCTL_VAL: - .word OMAP5910_ARM_CKCTL -EN_CLK_VAL: - .word OMAP5910_ARM_EN_CLK -GPIO_DIRECTION: - .word 0x0000ffe7 - -.end diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h deleted file mode 100644 index 30c08602f5..0000000000 --- a/board/netstar/crcek.h +++ /dev/null @@ -1,3 +0,0 @@ -#define LOADER_SIZE (448 * 1024) -#define LOADER1_OFFSET (128 * 1024) -#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c deleted file mode 100644 index a16264914c..0000000000 --- a/board/netstar/crcit.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2005 - * 2N Telekomunikace, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "crcek.h" - -extern uint32_t crc32(uint32_t, const unsigned char *, uint); - -static uint32_t data[LOADER_SIZE/4 + 3]; - -static int do_crc(char *path, unsigned version) -{ - uint32_t *p; - ssize_t size; - int fd; - - fd = open(path, O_RDONLY); - if (fd == -1) { - perror("Error opening file"); - return EXIT_FAILURE; - } - p = data + 2; - size = read(fd, p, LOADER_SIZE + 4); - if (size == -1) { - perror("Error reading file"); - return EXIT_FAILURE; - } - if (size > LOADER_SIZE) { - fprintf(stderr, "File too large\n"); - return EXIT_FAILURE; - } - size = (size + 3) & ~3; /* round up to 4 bytes */ - size += 4; /* add size of version field */ - data[0] = size; - data[1] = version; - data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size); - close(fd); - - if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) { - perror("Error writing file"); - return EXIT_FAILURE; - } - - return EXIT_SUCCESS; -} - -int main(int argc, char * const *argv) -{ - if (argc == 2) { - return do_crc(argv[1], 0); - } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { - char *endptr, *nptr = argv[2]; - unsigned ver = strtoul(nptr, &endptr, 0); - if (*nptr != '\0' && *endptr == '\0') - return do_crc(argv[3], ver); - } - fprintf(stderr, "Usage: crcit [-v version] \n"); - - return EXIT_FAILURE; -} diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c deleted file mode 100644 index aa375a4b1a..0000000000 --- a/board/netstar/eeprom.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Some code shamelessly stolen back from Robin Getz. - */ - -#include -#include -#include -#include -#include "../drivers/net/smc91111.h" - -static struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE -}; - -static u16 read_eeprom_reg(u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_RELOAD, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout reading register %02x\n", reg); - return 0; - } - - return SMC_inw(&dev, GP_REG); -} - -static int write_eeprom_reg(u16 value, u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - - SMC_outw(&dev, value, GP_REG); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_STORE, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout writing register %02x\n", reg); - return 0; - } - - return 1; -} - -static int write_data(u16 *buf, int len) -{ - u16 reg = 0x23; - - while (len--) - write_eeprom_reg(*buf++, reg++); - - return 0; -} - -static int verify_macaddr(char *s) -{ - u16 reg; - int i, err = 0; - - puts("HWaddr: "); - for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - if (s) - err |= reg != ((u16 *)s)[i]; - } - - return err ? 0 : 1; -} - -static int set_mac(char *s) -{ - int i; - char *e, eaddr[6]; - - /* turn string into mac value */ - for (i = 0; i < 6; i++) { - eaddr[i] = simple_strtoul(s, &e, 16); - s = (*e) ? e+1 : e; - } - - for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); - - return 0; -} - -static int parse_element(char *s, unsigned char *buf, int len) -{ - int cnt; - char *p, num[3]; - unsigned char id; - - id = simple_strtoul(s, &p, 16); - if (*p++ != ':') - return -1; - cnt = 2; - num[2] = 0; - for (; *p; p += 2) { - if (p[1] == 0) - return -2; - if (cnt + 3 > len) - return -3; - num[0] = p[0]; - num[1] = p[1]; - buf[cnt++] = simple_strtoul(num, NULL, 16); - } - buf[0] = id; - buf[1] = cnt - 2; - - return cnt; -} - -int eeprom(int argc, char * const argv[]) -{ - int i, len, ret; - unsigned char buf[58], *p; - - app_startup(argv); - i = get_version(); - if (i != XF_VERSION) { - printf("Using ABI version %d, but U-Boot provides %d\n", - XF_VERSION, i); - return 1; - } - - if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - puts("SMSC91111 not found\n"); - return 2; - } - - /* Called without parameters - print MAC address */ - if (argc < 2) { - verify_macaddr(NULL); - return 0; - } - - /* Print help message */ - if (argv[1][1] == 'h') { - puts("NetStar EEPROM writer\n" - "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" - "Usage:\n\t [] [<...>]\n"); - return 0; - } - - /* Try to parse information elements */ - len = sizeof(buf); - p = buf; - for (i = 2; i < argc; i++) { - ret = parse_element(argv[i], p, len); - switch (ret) { - case -1: - printf("Element %d: malformed\n", i - 1); - return 3; - case -2: - printf("Element %d: odd character count\n", i - 1); - return 3; - case -3: - puts("Out of EEPROM memory\n"); - return 3; - default: - p += ret; - len -= ret; - } - } - - /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - puts("*** HWaddr does not match! ***\n"); - return 4; - } - - while (len--) - *p++ = 0; - - write_data((u16 *)buf, sizeof(buf) >> 1); - - return 0; -} diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c deleted file mode 100644 index df1704be35..0000000000 --- a/board/netstar/netstar.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of NetStar board */ - gd->bd->bi_arch_number = MACH_TYPE_NETSTAR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before timer_init call */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; - udelay(500); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_RTC_DS1307) - /* enable trickle charge */ - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0x10, 0xaa); -#endif - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -#if defined(CONFIG_CMD_FLASH) -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info) -{ - if (banknum == 0) { /* AM29LV800 boot flash */ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; - } - - return 0; -} -#endif - -#if defined(CONFIG_CMD_NAND) -/* - * hardware specific access to control-lines - * - * NAND_NCE: bit 0 - don't care - * NAND_CLE: bit 1 -> bit 1 (0x0002) - * NAND_ALE: bit 2 -> bit 2 (0x0004) - */ -static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *chip = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)chip->IO_ADDR_W | mask); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->options = NAND_SAMSUNG_LP_OPTIONS; - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = netstar_nand_hwcontrol; - nand->chip_delay = 400; - return 0; -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/netstar/setup.S b/board/netstar/setup.S deleted file mode 100644 index 72e18112f6..0000000000 --- a/board/netstar/setup.S +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 Ales Jindra - * (C) Copyright 2005 Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */ - -OMAP5910_LPG1_BASE: .word 0xfffbd000 -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 -OMAP5910_MPU_TC_BASE: .word 0xfffecc00 -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 -OMAP5910_DPLL1_BASE: .word 0xfffecf00 -OMAP5910_GPIO_BASE: .word 0xfffce000 -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 -OMAP5910_MPUI_BASE: .word 0xfffec900 - -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK - -OMAP5910_MPUI_CTRL: .word 0x0000ff1b - -VAL_EMIFS_CS0_CONFIG: .word 0x00009090 -VAL_EMIFS_CS1_CONFIG: .word 0x00003031 -VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 -VAL_EMIFS_DYN_WAIT: .word 0x00000000 -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ - -#if (PHYS_SDRAM_1_SIZE == SZ_32M) -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -#else -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -#endif - -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 -VAL_EMIFF_MRS: .word 0x00000037 - -/* - * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) - * GPIO07 - LAN91C111 reset - */ -GPIO_DIRECTION: - .word 0x0000ff6f -/* - * Disable everything (green LED is connected via invertor) - */ -GPIO_OUTPUT: - .word 0x00000010 - -MUX_CONFIG_BASE: - .word 0xfffe1000 - -MUX_CONFIG_VALUES: - .align 4 - .word 0x00000000 @ FUNC_MUX_CTRL_0 - .word 0x00000000 @ FUNC_MUX_CTRL_1 - .word 0x00000000 @ FUNC_MUX_CTRL_2 - .word 0x00000000 @ FUNC_MUX_CTRL_3 - .word 0x00000000 @ FUNC_MUX_CTRL_4 - .word 0x02080480 @ FUNC_MUX_CTRL_5 - .word 0x0100001c @ FUNC_MUX_CTRL_6 - .word 0x0004800b @ FUNC_MUX_CTRL_7 - .word 0x10001200 @ FUNC_MUX_CTRL_8 - .word 0x01201012 @ FUNC_MUX_CTRL_9 - .word 0x02082248 @ FUNC_MUX_CTRL_A - .word 0x00000248 @ FUNC_MUX_CTRL_B - .word 0x12240000 @ FUNC_MUX_CTRL_C - .word 0x00002000 @ FUNC_MUX_CTRL_D - .word 0x00000000 @ PULL_DWN_CTRL_0 - .word 0x00000800 @ PULL_DWN_CTRL_1 - .word 0x01801000 @ PULL_DWN_CTRL_2 - .word 0x00000000 @ PULL_DWN_CTRL_3 - .word 0x00000000 @ GATE_INH_CTRL_0 - .word 0x00000000 @ VOLTAGE_CTRL_0 - .word 0x00000000 @ TEST_DBG_CTRL_0 - .word 0x00000006 @ MOD_CONF_CTRL_0 - .word 0x0000eaef @ COMP_MODE_CTRL_0 - -MUX_CONFIG_OFFSETS: - .align 1 - .byte 0x00 @ FUNC_MUX_CTRL_0 - .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 - .byte 0x10 @ FUNC_MUX_CTRL_3 - .byte 0x14 @ FUNC_MUX_CTRL_4 - .byte 0x18 @ FUNC_MUX_CTRL_5 - .byte 0x1c @ FUNC_MUX_CTRL_6 - .byte 0x20 @ FUNC_MUX_CTRL_7 - .byte 0x24 @ FUNC_MUX_CTRL_8 - .byte 0x28 @ FUNC_MUX_CTRL_9 - .byte 0x2c @ FUNC_MUX_CTRL_A - .byte 0x30 @ FUNC_MUX_CTRL_B - .byte 0x34 @ FUNC_MUX_CTRL_C - .byte 0x38 @ FUNC_MUX_CTRL_D - .byte 0x40 @ PULL_DWN_CTRL_0 - .byte 0x44 @ PULL_DWN_CTRL_1 - .byte 0x48 @ PULL_DWN_CTRL_2 - .byte 0x4c @ PULL_DWN_CTRL_3 - .byte 0x50 @ GATE_INH_CTRL_0 - .byte 0x60 @ VOLTAGE_CTRL_0 - .byte 0x70 @ TEST_DBG_CTRL_0 - .byte 0x80 @ MOD_CONF_CTRL_0 - .byte 0x0c @ COMP_MODE_CTRL_0 - .byte 0xff - -.globl lowlevel_init -lowlevel_init: - /* Improve performance a bit... */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 -loop: - cmp r2, #1 @ this loop will wait for at least 100 cycles - streqh r1, [r0, #0x18] @ before issuing next request from MPU - add r2, r2, #1 @ on the 1st run code is loaded into I-cache - cmp r2, #16 @ and second run will set clocking mode - bne loop - nop - - /* Setup clock dividers */ - ldr r1, _OMAP5910_ARM_CKCTL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, _OMAP5910_ARM_EN_CLK - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) - - /* Configure 5910 pins functions to match our board. */ - ldr r0, MUX_CONFIG_BASE - adr r1, MUX_CONFIG_VALUES - adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: - ldrb r3, [r2], #1 - ldr r4, [r1], #4 - cmp r3, #0xff - strne r4, [r0, r3] - bne next_mux_cfg - - /* Configure GPIO pins (also disables Green LED) */ - ldr r0, OMAP5910_GPIO_BASE - ldr r1, GPIO_OUTPUT - strh r1, [r0, #0x04] - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] - - /* EnablePeripherals */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit - mov r1, #0x0001 @ Peripheral enable - strh r1, [r0, #0x14] - - /* Program LED Pulse Generator */ - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator - mov r1, #0x7F @ Set obscure frequency in - strb r1, [r0, #0x00] @ LCR - mov r1, #0x01 @ Enable clock (CLK_EN) in - strb r1, [r0, #0x04] @ PMR - - /* TIPB Lock UART1 */ - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches - mov r1, #1 @ ARM allocated - strh r1, [r0,#0x04] @ clear IRQ line and status bits - strh r1, [r0,#0x00] - ldrh r1, [r0,#0x04] - - /* Disable watchdog */ - ldr r0, OMAP5910_MPU_WD_TIMER_BASE - mov r1, #0xf5 - strh r1, [r0, #0x8] - mov r1, #0xa0 - strh r1, [r0, #0x8] - - /* Enable MCLK */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE - mov r1, #0x6 - strh r1, [r0, #0x34] - strh r1, [r0, #0x34] - - /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register - - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write - -ulocking: - ldrh r1, [r0] @ get DPLL value - tst r1, #1 - beq ulocking @ while LOCK not set - - /* EMIF init */ - ldr r0, OMAP5910_MPU_TC_BASE - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG - bic r1, r1, #0x0c @ pwr down disabled, flash WP - orr r1, r1, #0x01 - str r1, [r0, #0x0c] - - ldr r1, VAL_EMIFS_CS0_CONFIG - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG - ldr r1, VAL_EMIFS_CS1_CONFIG - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG - ldr r1, VAL_EMIFS_CS2_CONFIG - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG - ldr r1, VAL_EMIFS_CS3_CONFIG - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG - ldr r1, VAL_EMIFS_DYN_WAIT - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT - - /* Setup SDRAM */ - ldr r1, VAL_EMIFF_SDRAM_CONFIG - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG - ldr r1, VAL_EMIFF_SDRAM_CONFIG2 - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 - ldr r1, VAL_EMIFF_MRS - str r1, [r0, #0x24] @ EMIFF_MRS - /* SDRAM needs 100us to stabilize */ - mov r0, #0x4000 -sdelay: - subs r0, r0, #0x1 - bne sdelay - - /* back to arch calling code */ - mov pc, lr -.end diff --git a/boards.cfg b/boards.cfg index 6c7775d70e..86d31b76b6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -70,7 +70,6 @@ sbc2410x arm arm920t - - VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2400 arm arm920t - samsung s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 -netstar arm arm925t voiceblue arm arm925t omap1510inn arm arm925t - ti integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 8d04db6b82..df14b4e0e0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +netstar arm arm925t - 2011-07-17 mx1fs2 arm arm920t - 2011-07-17 lpd7a404 arm lh7a40x - 2011-07-17 edb9301 arm arm920t - 2011-07-17 diff --git a/include/configs/netstar.h b/include/configs/netstar.h deleted file mode 100644 index f159013934..0000000000 --- a/include/configs/netstar.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * Configuation settings for the TI OMAP NetStar board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 5910 */ - -/* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */ -#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R /* There is nothing to really init */ -#define BOARD_LATE_INIT /* but we flash the LEDs here */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x10000000 -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) -#define PHYS_FLASH_1 0x00000000 - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x4000 -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#define CONFIG_ENV_ADDR_REDUND 0x6000 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_OVERWRITE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * The stack size is set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (1 * 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) -#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE - -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 19 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) -#define NAND_ALLOW_ERASE_ALL 1 - -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Partitions (mtdparts command line support) - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "physmap-flash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ - "gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" - -/* - * Command line configuration - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_LOOPW - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ -#define CONFIG_BOOTCOMMAND "run fboot" -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autostart=yes\0" \ - "ospart=0\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0" \ - "setpart=" \ - "if test -n $swapos; then " \ - "setenv swapos; saveenv; " \ - "if test $ospart -eq 0; then " \ - "setenv ospart 1; " \ - "else " \ - "setenv ospart 0; " \ - "fi; " \ - "fi\0" \ - "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart;setenv bootargs $bootargs " \ - "root=mtd:rootfs$ospart ro " \ - "rootfstype=jffs2\0" \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs;nboot kernel$ospart\0" \ - "nboot=bootp;run nfsargs;tftp\0" - -#if 0 /* feel free to disable for development */ -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nNetStar PBX - boot in %d secs...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "# " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ - (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) - -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000) - -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE -#define CONFIG_SYS_PTV 7 -#define CONFIG_SYS_HZ 1000 - -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL \ - ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) - -#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ -#define OMAP5910_LCD_DIV 2 /* CKL/4 */ -#define OMAP5910_ARM_DIV 0 /* CKL/1 */ -#define OMAP5910_DSP_DIV 0 /* CKL/1 */ -#define OMAP5910_TC_DIV 1 /* CKL/2 */ -#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ -#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ - -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b */ -#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ - (OMAP5910_LCD_DIV << 2) | \ - (OMAP5910_ARM_DIV << 4) | \ - (OMAP5910_DSP_DIV << 6) | \ - (OMAP5910_TC_DIV << 8) | \ - (OMAP5910_DSP_MMU_DIV << 10) | \ - (OMAP5910_ARM_TIM_SEL << 12)) - -#endif /* __CONFIG_H */ From 1f7f0edd3c6722efda28b7680f67561cd008d1ca Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:39 +0000 Subject: [PATCH 067/145] ARM: remove broken "sbc2410x" board Signed-off-by: Wolfgang Denk --- MAKEALL | 1 - board/sbc2410x/Makefile | 51 ---- board/sbc2410x/config.mk | 23 -- board/sbc2410x/flash.c | 433 --------------------------------- board/sbc2410x/lowlevel_init.S | 163 ------------- board/sbc2410x/sbc2410x.c | 193 --------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/sbc2410x.h | 220 ----------------- 9 files changed, 1 insertion(+), 1085 deletions(-) delete mode 100644 board/sbc2410x/Makefile delete mode 100644 board/sbc2410x/config.mk delete mode 100644 board/sbc2410x/flash.c delete mode 100644 board/sbc2410x/lowlevel_init.S delete mode 100644 board/sbc2410x/sbc2410x.c delete mode 100644 include/configs/sbc2410x.h diff --git a/MAKEALL b/MAKEALL index ce987e89cc..a485b95b7d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -338,7 +338,6 @@ LIST_ARM9=" \ openrd_ultimate \ portl2 \ rd6281a \ - sbc2410x \ scb9328 \ sheevaplug \ smdk2400 \ diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile deleted file mode 100644 index 2b3b781eea..0000000000 --- a/board/sbc2410x/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sbc2410x.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sbc2410x/config.mk b/board/sbc2410x/config.mk deleted file mode 100644 index bc01a2d9f2..0000000000 --- a/board/sbc2410x/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SMDK2410 has 1 bank of 64 MB DRAM -# -# 3000'0000 to 3400'0000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3080'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3300'0000 - -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c deleted file mode 100644 index d209a6f9ac..0000000000 --- a/board/sbc2410x/flash.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush (void); - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - printf ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - printf ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done:; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - get_timer(start); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/sbc2410x/lowlevel_init.S b/board/sbc2410x/lowlevel_init.S deleted file mode 100644 index 3de91661d4..0000000000 --- a/board/sbc2410x/lowlevel_init.S +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * Modified for the friendly-arm SBC-2410X by - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -#define B0_Tacs 0x0 -#define B0_Tcos 0x0 -#define B0_Tacc 0x7 -#define B0_Tcoh 0x0 -#define B0_Tah 0x0 -#define B0_Tacp 0x0 -#define B0_PMC 0x0 - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0xc -#define B3_Tcos 0x7 -#define B3_Tacc 0xf -#define B3_Tcoh 0x1 -#define B3_Tah 0x0 -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x0 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x0 -#define B4_Tah 0x0 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0xc -#define B5_Tcos 0x7 -#define B5_Tacc 0xf -#define B5_Tcoh 0x1 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 -#define B6_SCAN 0x1 /* 9bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 0x0459 -/**************************************/ - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0xb2 - .word 0x30 - .word 0x30 diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c deleted file mode 100644 index c82382dc82..0000000000 --- a/board/sbc2410x/sbc2410x.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NAND) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0x5c -#define M_PDIV 0x4 -#define M_SDIV 0x0 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x00044556; - gpio->gpbup = 0x000007FF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x0000FFFF; - gpio->gpfcon = 0x000055AA; - gpio->gpfup = 0x000000FF; - gpio->gpgcon = 0xFF95FF3A; - gpio->gpgup = 0x0000FFFF; - gpio->gphcon = 0x0016FAAA; - gpio->gphup = 0x000007FF; - - gpio->extint0 = 0x22222222; - gpio->extint1 = 0x22222222; - gpio->extint2 = 0x22222222; - - /* arch number of SMDK2410-Board */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#if defined(CONFIG_CMD_NAND) -extern ulong nand_probe(ulong physadr); - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - -static inline void NF_Init(void) -{ -#if 1 -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 86d31b76b6..967af2e735 100644 --- a/boards.cfg +++ b/boards.cfg @@ -66,7 +66,6 @@ mx1ads arm arm920t - - scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 -sbc2410x arm arm920t - - s3c24x0 VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2400 arm arm920t - samsung s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index df14b4e0e0..ef5ee75db2 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +sbc2410x arm arm920t - 2011-07-17 netstar arm arm925t - 2011-07-17 mx1fs2 arm arm920t - 2011-07-17 lpd7a404 arm lh7a40x - 2011-07-17 diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h deleted file mode 100644 index f0f19b2712..0000000000 --- a/include/configs/sbc2410x.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * Modified for the friendly-arm SBC-2410X by - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, - * - * Configuation settings for the friendly-arm SBC-2410X board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ - - -#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x19000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */ - -/************************************************************ - * RTC - ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \ - "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \ - "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.69 -#define CONFIG_SERVERIP 192.168.0.1 -/*#define CONFIG_BOOTFILE "elinos-lart" */ -#define CONFIG_BOOTCOMMAND "dhcp; bootm" - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */ - -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif - -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * NAND flash settings - */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_S3C2410 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_CMDLINE_EDITING - -#ifdef CONFIG_CMDLINE_EDITING -#undef CONFIG_AUTO_COMPLETE -#else -#define CONFIG_AUTO_COMPLETE -#endif - -#endif /* __CONFIG_H */ From ad218a868b57a69f189a6dfb438c77f46563431d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:40 +0000 Subject: [PATCH 068/145] ARM: remove broken "smdk2400" board Signed-off-by: Wolfgang Denk Cc: Gary Jennejohn --- MAINTAINERS | 4 - MAKEALL | 1 - board/samsung/smdk2400/Makefile | 51 --- board/samsung/smdk2400/config.mk | 25 -- board/samsung/smdk2400/flash.c | 492 ------------------------- board/samsung/smdk2400/lowlevel_init.S | 163 -------- board/samsung/smdk2400/smdk2400.c | 125 ------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/smdk2400.h | 189 ---------- 10 files changed, 1 insertion(+), 1051 deletions(-) delete mode 100644 board/samsung/smdk2400/Makefile delete mode 100644 board/samsung/smdk2400/config.mk delete mode 100644 board/samsung/smdk2400/flash.c delete mode 100644 board/samsung/smdk2400/lowlevel_init.S delete mode 100644 board/samsung/smdk2400/smdk2400.c delete mode 100644 include/configs/smdk2400.h diff --git a/MAINTAINERS b/MAINTAINERS index 322334dd5e..167b304730 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -685,10 +685,6 @@ Grazvydas Ignotas omap3_pandora ARM ARMV7 (OMAP3xx SoC) -Gary Jennejohn - - smdk2400 ARM920T - Matthias Kaehlcke edb9301 ARM920T (EP9301) edb9302 ARM920T (EP9302) diff --git a/MAKEALL b/MAKEALL index a485b95b7d..73a053da24 100755 --- a/MAKEALL +++ b/MAKEALL @@ -340,7 +340,6 @@ LIST_ARM9=" \ rd6281a \ scb9328 \ sheevaplug \ - smdk2400 \ smdk2410 \ spear300 \ spear310 \ diff --git a/board/samsung/smdk2400/Makefile b/board/samsung/smdk2400/Makefile deleted file mode 100644 index 0c45d02a65..0000000000 --- a/board/samsung/smdk2400/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := smdk2400.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk2400/config.mk b/board/samsung/smdk2400/config.mk deleted file mode 100644 index 4c27dc3044..0000000000 --- a/board/samsung/smdk2400/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SAMSUNG board with S3C2400X (ARM920T) CPU -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SAMSUNG has 1 bank of 32 MB DRAM -# -# 0C00'0000 to 0E00'0000 -# -# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000 -# optionally with a ramdisk at 0c80'0000 -# -# we load ourself to 0CF80000 (must be high enough not to be -# overwritten by the uncompessing Linux kernel) -# -# download area is 0C80'0000 -# - - -CONFIG_SYS_TEXT_BASE = 0x0CF80000 diff --git a/board/samsung/smdk2400/flash.c b/board/samsung/smdk2400/flash.c deleted file mode 100644 index 47382fe8f2..0000000000 --- a/board/samsung/smdk2400/flash.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#define FLASH_BANK_SIZE 0x1000000 /* 2 x 8 MB */ -#define MAIN_SECT_SIZE 0x40000 /* 2 x 128 kB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/samsung/smdk2400/lowlevel_init.S b/board/samsung/smdk2400/lowlevel_init.S deleted file mode 100644 index c275c07e7c..0000000000 --- a/board/samsung/smdk2400/lowlevel_init.S +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung development board by - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S - * - * Copyright (C) 2001 Samsung Electronics by chc, 010406 - * - * S3C2400 specific tweaks. - * - */ - -/* memory controller */ -#define BWSCON 0x14000000 -#define BANKCON3 0x14000010 /* for cs8900, ethernet */ - -/* Bank0 */ -#define B0_Tacs 0x0 /* 0 clk */ -#define B0_Tcos 0x0 /* 0 clk */ -#define B0_Tacc 0x7 /* 14 clk */ -#define B0_Tcoh 0x0 /* 0 clk */ -#define B0_Tah 0x0 /* 0 clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* Bank1 */ -#define B1_Tacs 0x0 /* 0 clk */ -#define B1_Tcos 0x0 /* 0 clk */ -#define B1_Tacc 0x7 /* 14 clk */ -#define B1_Tcoh 0x0 /* 0 clk */ -#define B1_Tah 0x0 /* 0 clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 /* normal */ - -/* Bank2 */ -#define B2_Tacs 0x0 /* 0 clk */ -#define B2_Tcos 0x0 /* 0 clk */ -#define B2_Tacc 0x7 /* 14 clk */ -#define B2_Tcoh 0x0 /* 0 clk */ -#define B2_Tah 0x0 /* 0 clk */ -#define B2_Tacp 0x0 -#define B2_PMC 0x0 /* normal */ - -/* Bank3 - setup for the cs8900 */ -#define B3_Tacs 0x0 /* 0 clk */ -#define B3_Tcos 0x3 /* 4 clk */ -#define B3_Tacc 0x7 /* 14 clk */ -#define B3_Tcoh 0x1 /* 1 clk */ -#define B3_Tah 0x0 /* 0 clk */ -#define B3_Tacp 0x3 /* 6 clk */ -#define B3_PMC 0x0 /* normal */ - -/* Bank4 */ -#define B4_Tacs 0x0 /* 0 clk */ -#define B4_Tcos 0x0 /* 0 clk */ -#define B4_Tacc 0x7 /* 14 clk */ -#define B4_Tcoh 0x0 /* 0 clk */ -#define B4_Tah 0x0 /* 0 clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -/* Bank5 */ -#define B5_Tacs 0x0 /* 0 clk */ -#define B5_Tcos 0x0 /* 0 clk */ -#define B5_Tacc 0x7 /* 14 clk */ -#define B5_Tcoh 0x0 /* 0 clk */ -#define B5_Tah 0x0 /* 0 clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ -#define B6_SCAN 0x1 /* 9 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9 bit */ - -/* refresh parameter */ -#define REFEN 0x1 /* enable refresh */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ -#define Trp 0x0 /* 2 clk */ -#define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ - -#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #52 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ - .word 0x30 /* MRSR6, CL=3clk */ - .word 0x30 /* MRSR7 */ diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c deleted file mode 100644 index 895bd7789a..0000000000 --- a/board/samsung/smdk2400/smdk2400.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -int mdm_init (bd_t *); -extern void disable_putc(void); -extern void enable_putc(void); -extern int hwflow_onoff(int); -extern int do_mdm_init; /* defined in common/main.c */ -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* memory and cpu-speed are setup before relocation */ - /* change the clock to be 50 MHz 1:1:1 */ - clk_power->mpllcon = 0x5c042; - clk_power->clkdivn = 0; - /* set up the I/O ports */ - gpio->pacon = 0x3ffff; - gpio->pbcon = 0xaaaaaaaa; - gpio->pbup = 0xffff; - gpio->pecon = 0x0; - gpio->peup = 0x0; -#ifdef CONFIG_HWFLOW - /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->pfcon = 0xa22; - /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->pfup = 0x35; -#else - /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->pfcon = 0x22; - /* Disable pull-up on Rx and Tx pins */ - gpio->pfup = 0x5; -#endif /* CONFIG_HWFLOW */ - gpio->pgcon = 0x0; - gpio->pgup = 0x0; - gpio->opencr = 0x0; - - /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x0C000100; - -#ifdef CONFIG_MODEM_SUPPORT - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - do_mdm_init = 1; - } -#endif /* CONFIG_MODEM_SUPPORT */ - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - int rc; - if (1) { /* check for button push here, now just return 1 */ - rc = 1; - } - - return rc; -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 967af2e735..02b8c8c25b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -67,7 +67,6 @@ scb9328 arm arm920t - - cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 VCMA9 arm arm920t vcma9 mpl s3c24x0 -smdk2400 arm arm920t - samsung s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 voiceblue arm arm925t omap1510inn arm arm925t - ti diff --git a/doc/README.scrapyard b/doc/README.scrapyard index ef5ee75db2..8444ed2ac5 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +smdk2400 arm arm920t - 2011-07-17 Gary Jennejohn sbc2410x arm arm920t - 2011-07-17 netstar arm arm925t - 2011-07-17 mx1fs2 arm arm920t - 2011-07-17 diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h deleted file mode 100644 index 064749e2d6..0000000000 --- a/include/configs/smdk2400.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * - * Configuation settings for the SAMSUNG board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ -#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */ - -#undef CONFIG_HWFLOW /* include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* enable modem initialization stuff */ - -/* - * The following enables modem debugging stuff. The dbg() and - * 'char screen[1024]' are used for debug printfs. Unfortunately, - * it is usable only from BDI - */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* Use s3c2400's RTC */ -#define CONFIG_RTC_S3C24X0 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_HWFLOW) - #define CONFIG_CONFIG_HWFLOW -#endif - -#if !defined(USE_920T_MMU) - #undef CONFIG_CMD_CACHE -#endif - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 134.98.93.36 -#define CONFIG_SERVERIP 134.98.93.22 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SMDK2400 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0c000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x0cf00000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x40000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#endif /* __CONFIG_H */ From 1b793a472eeabb4e6bead63c4125e5188630affb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:42 +0000 Subject: [PATCH 069/145] ARM: remove broken "voiceblue" board Signed-off-by: Wolfgang Denk --- MAKEALL | 1 - board/voiceblue/Makefile | 74 ---------- board/voiceblue/config.mk | 1 - board/voiceblue/eeprom.c | 218 ---------------------------- board/voiceblue/setup.S | 280 ------------------------------------ board/voiceblue/voiceblue.c | 80 ----------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/voiceblue.h | 241 ------------------------------- 9 files changed, 1 insertion(+), 896 deletions(-) delete mode 100644 board/voiceblue/Makefile delete mode 100644 board/voiceblue/config.mk delete mode 100644 board/voiceblue/eeprom.c delete mode 100644 board/voiceblue/setup.S delete mode 100644 board/voiceblue/voiceblue.c delete mode 100644 include/configs/voiceblue.h diff --git a/MAKEALL b/MAKEALL index 73a053da24..e72a019cea 100755 --- a/MAKEALL +++ b/MAKEALL @@ -349,7 +349,6 @@ LIST_ARM9=" \ versatile \ versatileab \ versatilepb \ - voiceblue \ davinci_dvevm \ davinci_schmoogie \ davinci_sffsdr \ diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile deleted file mode 100644 index e16b195c3c..0000000000 --- a/board/voiceblue/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# (C) Copyright 2005 -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License version 2 as -# published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := voiceblue.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -LOAD_ADDR = 0x10400000 - -######################################################################### - -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -$(obj)eeprom_start.o: - echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - - -$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o - $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ - -L$(obj)../../examples/standalone -lstubs \ - $(PLATFORM_LIBS) - -$(obj)eeprom.srec: $(obj)eeprom - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)eeprom.bin: $(obj)eeprom - $(OBJCOPY) -S -O binary $< $@ - -clean: - rm -f $(SOBJS) $(OBJS) $(obj)eeprom \ - $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)eeprom.o $(obj)eeprom_start.o - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk deleted file mode 100644 index 412b57d27e..0000000000 --- a/board/voiceblue/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x13FD0000 diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c deleted file mode 100644 index aa6baca645..0000000000 --- a/board/voiceblue/eeprom.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Some code shamelessly stolen back from Robin Getz. - */ - -#include -#include -#include -#include -#include "../drivers/net/smc91111.h" - -static struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE -}; - -static u16 read_eeprom_reg(u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_RELOAD, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout reading register %02x\n", reg); - return 0; - } - - return SMC_inw(&dev, GP_REG); -} - -static int write_eeprom_reg(u16 value, u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - - SMC_outw(&dev, value, GP_REG); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_STORE, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout writing register %02x\n", reg); - return 0; - } - - return 1; -} - -static int write_data(u16 *buf, int len) -{ - u16 reg = 0x23; - - while (len--) - write_eeprom_reg(*buf++, reg++); - - return 0; -} - -static int verify_macaddr(char *s) -{ - u16 reg; - int i, err = 0; - - puts("HWaddr: "); - for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - if (s) - err |= reg != ((u16 *)s)[i]; - } - - return err ? 0 : 1; -} - -static int set_mac(char *s) -{ - int i; - char *e, eaddr[6]; - - /* turn string into mac value */ - for (i = 0; i < 6; i++) { - eaddr[i] = simple_strtoul(s, &e, 16); - s = (*e) ? e+1 : e; - } - - for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); - - return 0; -} - -static int parse_element(char *s, unsigned char *buf, int len) -{ - int cnt; - char *p, num[3]; - unsigned char id; - - id = simple_strtoul(s, &p, 16); - if (*p++ != ':') - return -1; - cnt = 2; - num[2] = 0; - for (; *p; p += 2) { - if (p[1] == 0) - return -2; - if (cnt + 3 > len) - return -3; - num[0] = p[0]; - num[1] = p[1]; - buf[cnt++] = simple_strtoul(num, NULL, 16); - } - buf[0] = id; - buf[1] = cnt - 2; - - return cnt; -} - -int eeprom(int argc, char * const argv[]) -{ - int i, len, ret; - unsigned char buf[58], *p; - - app_startup(argv); - i = get_version(); - if (i != XF_VERSION) { - printf("Using ABI version %d, but U-Boot provides %d\n", - XF_VERSION, i); - return 1; - } - - if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - puts("SMSC91111 not found\n"); - return 2; - } - - /* Called without parameters - print MAC address */ - if (argc < 2) { - verify_macaddr(NULL); - return 0; - } - - /* Print help message */ - if (argv[1][1] == 'h') { - puts("VoiceBlue EEPROM writer\n" - "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" - "Usage:\n\t [] [<...>]\n"); - return 0; - } - - /* Try to parse information elements */ - len = sizeof(buf); - p = buf; - for (i = 2; i < argc; i++) { - ret = parse_element(argv[i], p, len); - switch (ret) { - case -1: - printf("Element %d: malformed\n", i - 1); - return 3; - case -2: - printf("Element %d: odd character count\n", i - 1); - return 3; - case -3: - puts("Out of EEPROM memory\n"); - return 3; - default: - p += ret; - len -= ret; - } - } - - /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - puts("*** HWaddr does not match! ***\n"); - return 4; - } - - while (len--) - *p++ = 0; - - write_data((u16 *)buf, sizeof(buf) >> 1); - - return 0; -} diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S deleted file mode 100644 index 6dddd6bdcf..0000000000 --- a/board/voiceblue/setup.S +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 Ales Jindra - * (C) Copyright 2005 Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */ - -OMAP5910_LPG1_BASE: .word 0xfffbd000 -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 -OMAP5910_MPU_TC_BASE: .word 0xfffecc00 -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 -OMAP5910_DPLL1_BASE: .word 0xfffecf00 -OMAP5910_GPIO_BASE: .word 0xfffce000 -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 -OMAP5910_MPUI_BASE: .word 0xfffec900 - -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK - -OMAP5910_MPUI_CTRL: .word 0x0000ff1b - -VAL_EMIFS_CS0_CONFIG: .word 0x00009090 -VAL_EMIFS_CS1_CONFIG: .word 0x00003031 -VAL_EMIFS_CS2_CONFIG: .word 0x00003031 -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 -VAL_EMIFS_DYN_WAIT: .word 0x00000000 -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 -VAL_EMIFF_MRS: .word 0x00000037 - -/* - * GPIO04 - D4 (Onboard LED) - * GPIO07 - LAN91C111 reset - */ -GPIO_DIRECTION: - .word 0x0000ff6f -/* - * Disable everything, but D4 LED (connected through invertor) - */ -GPIO_OUTPUT: - .word 0x00000010 - -MUX_CONFIG_BASE: - .word 0xfffe1000 - -MUX_CONFIG_VALUES: - .align 4 - .word 0x00000000 @ FUNC_MUX_CTRL_0 - .word 0x00000000 @ FUNC_MUX_CTRL_1 - .word 0x00000000 @ FUNC_MUX_CTRL_2 - .word 0x00000000 @ FUNC_MUX_CTRL_3 - .word 0x00000000 @ FUNC_MUX_CTRL_4 - .word 0x12082480 @ FUNC_MUX_CTRL_5 - .word 0x0000001c @ FUNC_MUX_CTRL_6 - .word 0x00000003 @ FUNC_MUX_CTRL_7 - .word 0x10001200 @ FUNC_MUX_CTRL_8 - .word 0x01201012 @ FUNC_MUX_CTRL_9 - .word 0x02081248 @ FUNC_MUX_CTRL_A - .word 0x00001248 @ FUNC_MUX_CTRL_B - .word 0x12240000 @ FUNC_MUX_CTRL_C - .word 0x00002000 @ FUNC_MUX_CTRL_D - .word 0x00000000 @ PULL_DWN_CTRL_0 - .word 0x0000085f @ PULL_DWN_CTRL_1 - .word 0x01001000 @ PULL_DWN_CTRL_2 - .word 0x00000000 @ PULL_DWN_CTRL_3 - .word 0x00000000 @ GATE_INH_CTRL_0 - .word 0x00000000 @ VOLTAGE_CTRL_0 - .word 0x00000000 @ TEST_DBG_CTRL_0 - .word 0x00000006 @ MOD_CONF_CTRL_0 - .word 0x0000eaef @ COMP_MODE_CTRL_0 - -MUX_CONFIG_OFFSETS: - .align 1 - .byte 0x00 @ FUNC_MUX_CTRL_0 - .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 - .byte 0x10 @ FUNC_MUX_CTRL_3 - .byte 0x14 @ FUNC_MUX_CTRL_4 - .byte 0x18 @ FUNC_MUX_CTRL_5 - .byte 0x1c @ FUNC_MUX_CTRL_6 - .byte 0x20 @ FUNC_MUX_CTRL_7 - .byte 0x24 @ FUNC_MUX_CTRL_8 - .byte 0x28 @ FUNC_MUX_CTRL_9 - .byte 0x2c @ FUNC_MUX_CTRL_A - .byte 0x30 @ FUNC_MUX_CTRL_B - .byte 0x34 @ FUNC_MUX_CTRL_C - .byte 0x38 @ FUNC_MUX_CTRL_D - .byte 0x40 @ PULL_DWN_CTRL_0 - .byte 0x44 @ PULL_DWN_CTRL_1 - .byte 0x48 @ PULL_DWN_CTRL_2 - .byte 0x4c @ PULL_DWN_CTRL_3 - .byte 0x50 @ GATE_INH_CTRL_0 - .byte 0x60 @ VOLTAGE_CTRL_0 - .byte 0x70 @ TEST_DBG_CTRL_0 - .byte 0x80 @ MOD_CONF_CTRL_0 - .byte 0x0c @ COMP_MODE_CTRL_0 - .byte 0xff - -.globl lowlevel_init -lowlevel_init: - /* Improve performance a bit... */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit - ldrh r1, [r0, #0x18] @ get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 @ set wait counter to 100 clock cycles - -icache_loop: - cmp r2, #0x01 - streqh r1, [r0, #0x18] - add r2, r2, #0x01 - cmp r2, #0x10 - bne icache_loop - nop - - /* Setup clock divisors */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - ldr r1, _OMAP5910_ARM_CKCTL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0, #0x00] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, _OMAP5910_ARM_EN_CLK - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - @ max delayed ( 32 x CLKIN ) - strh r1, [r0, #0x0c] - - /* Configure 5910 pins functions to match our board. */ - ldr r0, MUX_CONFIG_BASE - adr r1, MUX_CONFIG_VALUES - adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: - ldrb r3, [r2], #1 - ldr r4, [r1], #4 - cmp r3, #0xff - strne r4, [r0, r3] - bne next_mux_cfg - - /* Configure GPIO pins (also enables onboard LED) */ - ldr r0, OMAP5910_GPIO_BASE - ldr r1, GPIO_OUTPUT - strh r1, [r0, #0x04] - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] - - /* EnablePeripherals */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit - mov r1, #0x0001 @ Peripheral enable - strh r1, [r0, #0x14] - - /* Program LED Pulse Generator */ - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator - mov r1, #0x7F @ Set obscure frequency in - strb r1, [r0, #0x00] @ LCR - mov r1, #0x01 @ Enable clock (CLK_EN) in - strb r1, [r0, #0x04] @ PMR - - /* TIPB Lock UART1 */ - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches - mov r1, #1 @ ARM allocated - strh r1, [r0,#0x04] @ clear IRQ line and status bits - strh r1, [r0,#0x00] - ldrh r1, [r0,#0x04] - - /* Disable watchdog */ - ldr r0, OMAP5910_MPU_WD_TIMER_BASE - mov r1, #0xf5 - strh r1, [r0, #0x8] - mov r1, #0xa0 - strh r1, [r0, #0x8] - - /* Enable MCLK */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE - mov r1, #0x6 - strh r1, [r0, #0x34] - strh r1, [r0, #0x34] - - /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register - - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write - -ulocking: - ldrh r1, [r0] @ get DPLL value - tst r1, #1 - beq ulocking @ while LOCK not set - - /* EMIF init */ - ldr r0, OMAP5910_MPU_TC_BASE - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG - bic r1, r1, #0x0c @ pwr down disabled, flash WP - orr r1, r1, #0x01 - str r1, [r0, #0x0c] - - ldr r1, VAL_EMIFS_CS0_CONFIG - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG - ldr r1, VAL_EMIFS_CS1_CONFIG - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG - ldr r1, VAL_EMIFS_CS2_CONFIG - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG - ldr r1, VAL_EMIFS_CS3_CONFIG - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG - ldr r1, VAL_EMIFS_DYN_WAIT - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT - - /* Setup SDRAM */ - ldr r1, VAL_EMIFF_SDRAM_CONFIG - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG - ldr r1, VAL_EMIFF_SDRAM_CONFIG2 - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 - ldr r1, VAL_EMIFF_MRS - str r1, [r0, #0x24] @ EMIFF_MRS - /* SDRAM needs 100us to stabilize */ - mov r0, #0x4000 -sdelay: - subs r0, r0, #0x1 - bne sdelay - - /* back to arch calling code */ - mov pc, lr -.end diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c deleted file mode 100644 index 5f8af2bd24..0000000000 --- a/board/voiceblue/voiceblue.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; - - /* arch number of VoiceBlue board */ - gd->bd->bi_arch_number = MACH_TYPE_VOICEBLUE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - return 0; -} - -int dram_init(void) -{ - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; - - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before timer_init call */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; - udelay(500); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -int misc_init_r(void) -{ - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; - - return 0; -} - -int board_late_init(void) -{ - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 02b8c8c25b..ee7ba86914 100644 --- a/boards.cfg +++ b/boards.cfg @@ -68,7 +68,6 @@ cm4008 arm arm920t - - cm41xx arm arm920t - - ks8695 VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 -voiceblue arm arm925t omap1510inn arm arm925t - ti integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 8444ed2ac5..40cda23c6a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +voiceblue arm arm925t - 2011-07-17 smdk2400 arm arm920t - 2011-07-17 Gary Jennejohn sbc2410x arm arm920t - 2011-07-17 netstar arm arm925t - 2011-07-17 diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h deleted file mode 100644 index c258030e29..0000000000 --- a/include/configs/voiceblue.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * Configuation settings for the TI OMAP VoiceBlue board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 5910 */ - -/* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */ -#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R /* There is nothing to really init */ -#define BOARD_LATE_INIT /* but we flash the LEDs here */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x10000000 -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) -#define PHYS_FLASH_1 0x0000000 - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE - -/* - * Size of malloc() pool and stack - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_STACKSIZE (1 * 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) -#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE - -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE 0x08000300 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Command line configuration - */ -#include - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_LOOPW - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_SYS_AUTOLOAD "n" -#define CONFIG_BOOTCOMMAND "run nboot" -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "silent=1\0" \ - "ospart=0\0" \ - "bootfile=/boot/uImage\0" \ - "setpart=" \ - "if test -n $swapos; then " \ - "setenv swapos; saveenv; " \ - "if test $ospart -eq 0; then " \ - "setenv ospart 1; " \ - "else " \ - "setenv ospart 0; " \ - "fi; " \ - "fi\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "mtdparts=$mtdparts\0" \ - "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart; setenv bootargs $bootargs " \ - "root=mtd:data$ospart ro " \ - "rootfstype=jffs2\0" \ - "initrdargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \ - "mboot=bootp; run initrdargs; tftp; bootm\0" \ - "nboot=bootp; run nfsargs; tftp; bootm\0" - -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ - -#if 1 /* feel free to disable for development */ -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ -#endif - -/* - * Partitions (mtdparts command line support) - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ - "256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "# " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ - (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)) -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000) - -/* - * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ 1000 - -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL \ - ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) - -#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ -#define OMAP5910_LCD_DIV 2 /* CKL/4 */ -#define OMAP5910_ARM_DIV 0 /* CKL/1 */ -#define OMAP5910_DSP_DIV 0 /* CKL/1 */ -#define OMAP5910_TC_DIV 1 /* CKL/2 */ -#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ -#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ - -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ -#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ - (OMAP5910_LCD_DIV << 2) | \ - (OMAP5910_ARM_DIV << 4) | \ - (OMAP5910_DSP_DIV << 6) | \ - (OMAP5910_TC_DIV << 8) | \ - (OMAP5910_DSP_MMU_DIV << 10) | \ - (OMAP5910_ARM_TIM_SEL << 12)) - -#define VOICEBLUE_LED_REG 0x04030000 - -#endif /* __CONFIG_H */ From b5508344581d785b495df6e2b9cb94a13360afb5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:43 +0000 Subject: [PATCH 070/145] ARM: remove broken "at91cap9adk" board Signed-off-by: Wolfgang Denk Cc: Stelian Pop --- MAINTAINERS | 1 - board/atmel/at91cap9adk/Makefile | 56 ---- board/atmel/at91cap9adk/at91cap9adk.c | 352 -------------------------- board/atmel/at91cap9adk/config.mk | 1 - board/atmel/at91cap9adk/led.c | 43 ---- board/atmel/at91cap9adk/partition.c | 39 --- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/at91cap9adk.h | 218 ---------------- 9 files changed, 1 insertion(+), 711 deletions(-) delete mode 100644 board/atmel/at91cap9adk/Makefile delete mode 100644 board/atmel/at91cap9adk/at91cap9adk.c delete mode 100644 board/atmel/at91cap9adk/config.mk delete mode 100644 board/atmel/at91cap9adk/led.c delete mode 100644 board/atmel/at91cap9adk/partition.c delete mode 100644 include/configs/at91cap9adk.h diff --git a/MAINTAINERS b/MAINTAINERS index 167b304730..09fa789a0e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -788,7 +788,6 @@ Manikandan Pillai Stelian Pop - at91cap9adk ARM926EJS (AT91CAP9 SoC) at91sam9260ek ARM926EJS (AT91SAM9260 SoC) at91sam9261ek ARM926EJS (AT91SAM9261 SoC) at91sam9263ek ARM926EJS (AT91SAM9263 SoC) diff --git a/board/atmel/at91cap9adk/Makefile b/board/atmel/at91cap9adk/Makefile deleted file mode 100644 index 2eec0ce231..0000000000 --- a/board/atmel/at91cap9adk/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Lead Tech Design -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91cap9adk.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c deleted file mode 100644 index 2ab8bc2c43..0000000000 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include - -#define MP_BLOCK_3_BASE 0xFDF00000 - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -static void at91cap9_slowclock_hw_init(void) -{ - /* - * On AT91CAP9 revC CPUs, the slow clock can be based on an - * internal impreciseRC oscillator or an external 32kHz oscillator. - * Switch to the latter. - */ -#define ARCH_ID_AT91CAP9_REVB 0x399 -#define ARCH_ID_AT91CAP9_REVC 0x601 - if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) { - unsigned i, tmp = at91_sys_read(AT91_SCKCR); - if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) { - timer_init(); - tmp |= AT91CAP9_SCKCR_OSC32EN; - at91_sys_write(AT91_SCKCR, tmp); - for (i = 0; i < 1200; i++) - udelay(1000); - tmp |= AT91CAP9_SCKCR_OSCSEL_32; - at91_sys_write(AT91_SCKCR, tmp); - udelay(200); - tmp &= ~AT91CAP9_SCKCR_RCEN; - at91_sys_write(AT91_SCKCR, tmp); - } - } -} - -static void at91cap9_nor_hw_init(void) -{ - unsigned long csa; - - /* Ensure EBI supply is 3.3V */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - /* Configure SMC CS0 for parallel flash */ - at91_sys_write(AT91_SMC_SETUP(0), - AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) | - AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2)); - at91_sys_write(AT91_SMC_PULSE(0), - AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) | - AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10)); - at91_sys_write(AT91_SMC_CYCLE(0), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(0), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | - AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); -} - -#ifdef CONFIG_CMD_NAND -static void at91cap9_nand_hw_init(void) -{ - unsigned long csa; - - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | - AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - - /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | -#endif - AT91_SMC_TDF_(1)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); - - /* RDY/BSY is not connected */ - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void at91cap9_macb_hw_init(void) -{ - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PB22) => PHY normal mode (not Test mode) - * ERX0 (PB25) => PHY ADDR0 - * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PB22) | - pin_to_mask(AT91_PIN_PB25) | - pin_to_mask(AT91_PIN_PB26), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); - - /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); - - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); - - /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); - - /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0 << 8)) | - AT91_RSTC_URSTEN); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PB22) | - pin_to_mask(AT91_PIN_PB25) | - pin_to_mask(AT91_PIN_PB26), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); - - at91_macb_hw_init(); - - /* Unlock EMAC, 3 0 2 1 sequence */ -#define MP_MAC_KEY0 0x5969cb2a -#define MP_MAC_KEY1 0xb4a1872e -#define MP_MAC_KEY2 0x05683fbc -#define MP_MAC_KEY3 0x3634fba4 -#define UNLOCK_MAC 0x00000008 - writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c); - writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30); - writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38); - writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34); - writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40); -} -#endif - -#ifdef CONFIG_USB_OHCI_NEW -static void at91cap9_uhp_hw_init(void) -{ - /* Unlock USB OHCI, 3 2 0 1 sequence */ -#define MP_OHCI_KEY0 0x896c11ca -#define MP_OHCI_KEY1 0x68ebca21 -#define MP_OHCI_KEY2 0x4823efbc -#define MP_OHCI_KEY3 0x8651aae4 -#define UNLOCK_OHCI 0x00000010 - writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c); - writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38); - writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30); - writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34); - writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40); -} -#endif - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: AT91CAP9_LCDC_BASE, -}; - -void lcd_enable(void) -{ - at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */ -} - -void lcd_disable(void) -{ - at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */ -} - -static void at91cap9_lcd_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC); - - gd->fb_base = 0; -} - -#ifdef CONFIG_LCD_INFO -#include -#include - -void lcd_show_board_info(void) -{ - ulong dram_size, nand_size; - int i; - char temp[32]; - - lcd_printf ("%s\n", U_BOOT_VERSION); - lcd_printf ("(C) 2008 ATMEL Corp\n"); - lcd_printf ("at91support@atmel.com\n"); - lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, - strmhz(temp, get_cpu_clk_rate())); - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - nand_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; - lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", - dram_size >> 20, - nand_size >> 20 ); -} -#endif /* CONFIG_LCD_INFO */ -#endif - -int board_init(void) -{ - /* Enable Ctrlc */ - console_init_f(); - - /* arch number of AT91CAP9ADK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - at91_serial_hw_init(); - at91cap9_slowclock_hw_init(); - at91cap9_nor_hw_init(); -#ifdef CONFIG_CMD_NAND - at91cap9_nand_hw_init(); -#endif -#ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); -#endif -#ifdef CONFIG_MACB - at91cap9_macb_hw_init(); -#endif -#ifdef CONFIG_USB_OHCI_NEW - at91cap9_uhp_hw_init(); -#endif -#ifdef CONFIG_LCD - at91cap9_lcd_hw_init(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00); -#endif - return rc; -} diff --git a/board/atmel/at91cap9adk/config.mk b/board/atmel/at91cap9adk/config.mk deleted file mode 100644 index 797da0eafe..0000000000 --- a/board/atmel/at91cap9adk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x73000000 diff --git a/board/atmel/at91cap9adk/led.c b/board/atmel/at91cap9adk/led.c deleted file mode 100644 index 14aea994e9..0000000000 --- a/board/atmel/at91cap9adk/led.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -void coloured_LED_init(void) -{ - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); - - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - - at91_set_gpio_output(CONFIG_RED_LED, 0); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); -} diff --git a/board/atmel/at91cap9adk/partition.c b/board/atmel/at91cap9adk/partition.c deleted file mode 100644 index 7e1d46f530..0000000000 --- a/board/atmel/at91cap9adk/partition.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2008 - * Ulf Samuelsson - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#include -#include -#include -#include - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, -}; diff --git a/boards.cfg b/boards.cfg index ee7ba86914..174242291e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -77,7 +77,6 @@ versatileab arm arm926ejs versatile armltd aspenite arm arm926ejs - Marvell armada100 gplugd arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 -at91cap9adk arm arm926ejs - atmel at91 at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 40cda23c6a..847d02c8f0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +at91cap9adk arm arm926ejs - 2011-07-17 Stelian Pop voiceblue arm arm925t - 2011-07-17 smdk2400 arm arm920t - 2011-07-17 Gary Jennejohn sbc2410x arm arm920t - 2011-07-17 diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h deleted file mode 100644 index 49c923f163..0000000000 --- a/include/configs/at91cap9adk.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91CAP9ADK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */ -#define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */ -#define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ - -/* LCD */ -#define CONFIG_LCD 1 -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PC29 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PA10 /* this is the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIN_PA11 /* this is the user1 led */ - -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 - -/* - * Command line configuration. - */ -#include -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE - -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 - -/* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x70000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -/* DataFlash */ -#define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -/* NOR flash */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 - -#endif - -/* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91cap9" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 - -#define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x73e00000 - -#define CONFIG_SYS_USE_DATAFLASH 1 -#undef CONFIG_SYS_USE_NORFLASH - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env + linux in dataflash */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 " \ - "mtdparts=physmap-flash.0:-(nor);" \ - "atmel_nand:-(root) " \ - "rw rootfstype=jffs2" - -#else - -/* bootstrap + u-boot + env + linux in norflash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_SYS_MONITOR_BASE (PHYS_FLASH_1 + 0x8000) -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock4 " \ - "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\ - "16k(env),224k(uboot)ro,-(linux);" \ - "atmel_nand:-(root) " \ - "rw rootfstype=jffs2" - -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif From 37a9b4d0b7457f6d1c1998fff2372b7f92bc1d8c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:44 +0000 Subject: [PATCH 071/145] ARM: remove broken "cmc_pu2" board Signed-off-by: Wolfgang Denk --- board/cmc_pu2/Makefile | 50 --- board/cmc_pu2/cmc_pu2.c | 192 ------------ board/cmc_pu2/config.mk | 3 - board/cmc_pu2/flash.c | 469 ---------------------------- board/cmc_pu2/load_sernum_ethaddr.c | 113 ------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/cmc_pu2.h | 238 -------------- 8 files changed, 1 insertion(+), 1066 deletions(-) delete mode 100644 board/cmc_pu2/Makefile delete mode 100644 board/cmc_pu2/cmc_pu2.c delete mode 100644 board/cmc_pu2/config.mk delete mode 100644 board/cmc_pu2/flash.c delete mode 100644 board/cmc_pu2/load_sernum_ethaddr.c delete mode 100644 include/configs/cmc_pu2.h diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile deleted file mode 100644 index a60f2e9612..0000000000 --- a/board/cmc_pu2/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c deleted file mode 100644 index 0ac851c97f..0000000000 --- a/board/cmc_pu2/cmc_pu2.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn - * (2004) garyj@denx.de - * - * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ -#define CMC_HP_BASIC 1 -#define CMC_PU2 2 -#define CMC_BASIC 4 - -int hw_detect (void); - -int board_init (void) -{ - AT91PS_PIO piob = AT91C_BASE_PIOB; - AT91PS_PIO pioc = AT91C_BASE_PIOC; - - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - /* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */ - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - /* - * configure PC0-PC3 as input without pull ups, so RS485 driver enable - * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated. - */ - pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - - /* - * On CMC-PU2 board configure PB3-PB6 to input without pull ups to - * clear the duo LEDs (the external pull downs assure a proper - * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and - * drive it high, to configure current measurement on AINx. - */ - if (hw_detect() & CMC_PU2) { - piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) { - piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - - /* - * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in - * the linuxarm kernel, yet. - */ - /* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */ - gd->bd->bi_arch_number = 251; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -int checkboard (void) -{ - if (hw_detect() & CMC_PU2) - puts ("Board: CMC-PU2 (Rittal GmbH)\n"); - else if (hw_detect() & CMC_BASIC) - puts ("Board: CMC-BASIC (Rittal GmbH)\n"); - else if (hw_detect() & CMC_HP_BASIC) - puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n"); - else - puts ("Board: unknown\n"); - return 0; -} - -int hw_detect (void) -{ - AT91PS_PIO pio = AT91C_BASE_PIOB; - - /* PIOB clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - - /* configure PB12 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB12; - pio->PIO_PPUDR = AT91C_PIO_PB12; - pio->PIO_PER = AT91C_PIO_PB12; - - /* configure PB13 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB13; - pio->PIO_PPUDR = AT91C_PIO_PB13; - pio->PIO_PER = AT91C_PIO_PB13; - - /* read board identification pin */ - if (pio->PIO_PDSR & AT91C_PIO_PB12) - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_PU2 : 0); - else - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_HP_BASIC : CMC_BASIC); -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/board/cmc_pu2/config.mk b/board/cmc_pu2/config.mk deleted file mode 100644 index cdb8a5f571..0000000000 --- a/board/cmc_pu2/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x20F00000 -## For testing: load at 0x20100000 and "go" at 0x201000A4 -#CONFIG_SYS_TEXT_BASE = 0x20100000 diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c deleted file mode 100644 index d10faab52a..0000000000 --- a/board/cmc_pu2/flash.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn - * garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02AA - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_short *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - vu_short *base = (vu_short *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = 0x00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = 0x00F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - info = NULL; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_S29GL064M: - printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - int i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command sequence */ - addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */ - - /* read Manufacturer ID */ - udelay(100); - value = addr[0]; - debug ("Manufacturer ID: %04X\n", value); - - switch (value) { - - case (AMD_MANUFACT & 0xFFFF): - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (INTEL_MANUFACT & 0xFFFF): - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - printf ("Unknown Manufacturer ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - goto out; - } - - value = addr[1]; - debug ("Device ID: %04X\n", value); - - switch (addr[1]) { - - case (AMD_ID_MIRROR & 0xFFFF): - debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n", - addr[14], addr[15]); - - switch(addr[14]) { - case (AMD_ID_GL064M_2 & 0xFFFF): - if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) { - printf ("Chip: S29GLxxxM -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } else { - debug ("Chip: S29GL064M-R6\n"); - info->flash_id += FLASH_S29GL064M; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x10000; - } - } - break; /* => 16 MB */ - default: - printf ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - break; - - default: - printf ("Unknown Device ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - -out: - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short *)(info->start[0]); - int flag, prot, sect, ssect, l_sect; - ulong now, last, start; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* - * Start erase on unprotected sectors. - * Since the flash can erase multiple sectors with one command - * we take advantage of that by doing the erase in chunks of - * 3 sectors. - */ - for (sect = s_first; sect <= s_last; ) { - l_sect = -1; - - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - addr[FLASH_CYCLE1] = 0x0080; - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - - /* do the erase in chunks of at most 3 sectors */ - for (ssect = 0; ssect < 3; ssect++) { - if ((sect + ssect) > s_last) - break; - if (info->protect[sect + ssect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect + ssect]); - addr[0] = 0x0030; - l_sect = sect + ssect; - } - } - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = 0; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - sect += ssect; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((vu_short *)src); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (ERR_OK); - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) -{ - int flag; - vu_short *base; /* first address in flash bank */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (vu_short *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = 0x00AA; /* unlock */ - base[FLASH_CYCLE2] = 0x0055; /* unlock */ - base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = 0x00F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c deleted file mode 100644 index 6f85dd95b3..0000000000 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */ -#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */ -#define I2C_OFFSET 0x0 /* start address of manufacturere data block - * in EEPROM */ - -/* 64 Byte manufacturer data block in EEPROM */ -struct manufacturer_data { - unsigned int serial_number; /* serial number (0...999999) */ - unsigned short hardware; /* hardware version (e.g. V1.02) */ - unsigned short manuf_date; /* manufacture date (e.g. 25/02) */ - unsigned char name[20]; /* device name (in CHIP.INI) */ - unsigned char macadr[6]; /* MAC address */ - signed char a_kal[4]; /* calibration value for U */ - signed char i_kal[4]; /* calibration value for I */ - unsigned char reserve[18]; /* reserved */ - unsigned short save_nr; /* save count */ - unsigned short chksum; /* checksum */ -}; - - -int i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); - -/*----------------------------------------------------------------------- - * Process manufacturer data block in EEPROM: - * - * If we boot on a system fresh from factory, check if the manufacturer data - * in the EEPROM is valid and save some information it contains. - * - * CMC manufacturer data is defined as follows: - * - * - located in the onboard EEPROM - * - starts at offset 0x0 - * - size 0x00000040 - * - * Internal structure: see struct definition - */ - -int misc_init_r(void) -{ - struct manufacturer_data data; - char serial [9]; - unsigned short chksum; - unsigned char *p; - unsigned short i; - -#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) -#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) -#endif - if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, - sizeof(data)) != 0) { - puts ("Error reading manufacturer data from EEPROM\n"); - return -1; - } - - /* check if manufacturer data block is valid */ - p = (unsigned char *)&data; - chksum = 0; - for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++) - chksum += *p++; - - debug ("checksum of manufacturer data block: %#.4x\n", chksum); - - if (chksum != data.chksum) { - puts ("Error: manufacturer data block has invalid checksum\n"); - return -1; - } - - /* copy serial number */ - sprintf (serial, "%d", data.serial_number); - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ("serial#", serial); - } - - if (getenv("ethaddr") == NULL) { - eth_setenv_enetaddr("ethaddr", data.macadr); - } - - return 0; -} diff --git a/boards.cfg b/boards.cfg index 174242291e..61397fdade 100644 --- a/boards.cfg +++ b/boards.cfg @@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel eb_cpux9k2 arm arm920t - BuS at91 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -cmc_pu2 arm arm920t - - at91rm9200 csb637 arm arm920t - - at91rm9200 kb9202 arm arm920t - - at91rm9200 m501sk arm arm920t - - at91rm9200 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 847d02c8f0..f2b8ab18f0 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +cmc_pu2 arm arm920t - 2011-07-17 at91cap9adk arm arm926ejs - 2011-07-17 Stelian Pop voiceblue arm arm925t - 2011-07-17 smdk2400 arm arm920t - 2011-07-17 Gary Jennejohn diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h deleted file mode 100644 index a1976350e4..0000000000 --- a/include/configs/cmc_pu2.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * 2004-2005 Gary Jennejohn - * - * Configuration settings for the CMC PU2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_BAUDRATE 9600 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#undef CONFIG_DBGU -#define CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#else -#define CONFIG_TIMESTAMP -#endif -/* still about 20 kB free with this defined */ -#define CONFIG_SYS_LONGHELP - -#define CONFIG_BOOTDELAY 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC - -#if defined(CONFIG_HARD_I2C) - #define CONFIG_CMD_DATE - #define CONFIG_CMD_EEPROM - #define CONFIG_CMD_I2C -#endif - - -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_LONGHELP - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ -#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */ - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } - -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ - "addmtd;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ - "addcons addmtd; bootm\0" \ - "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}::off\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ - "64k(environment),768k(linux),4096k(root),-\0" \ - "load=tftp ${loadaddr} ${loadfile}\0" \ - "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ - "cp.b ${loadaddr} 10000000 ${filesize};" \ - "protect on 10000000 1001ffff\0" \ - "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ - "cp.b ${loadaddr} 10030000 ${filesize}\0" \ - "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ - "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ - "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ - "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ - "cramfsimage=cramfs_cmc-pu2.img\0" \ - "jffsimage=jffs2_cmc-pu2.img\0" \ - "loadfile=u-boot_cmc-pu2.bin\0" \ - "bootfile=uImage_cmc-pu2\0" \ - "loadaddr=0x20800000\0" \ - "hostname=CMC-TC-PU2\0" \ - "bootcmd=run dhcp_start;run flash_cramfs\0" \ - "autoload=n\0" \ - "dhcp_start=echo no DHCP\0" \ - "ipaddr=192.168.0.190\0" -#endif /* __CONFIG_H */ From d14af084669774fdd10ca7c8d3bcbb4856c08966 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:45 +0000 Subject: [PATCH 072/145] ARM: remove broken "csb637" board Signed-off-by: Wolfgang Denk --- board/csb637/Makefile | 50 ---------- board/csb637/config.mk | 1 - board/csb637/csb637.c | 94 ------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/csb637.h | 196 --------------------------------------- 6 files changed, 1 insertion(+), 342 deletions(-) delete mode 100644 board/csb637/Makefile delete mode 100644 board/csb637/config.mk delete mode 100644 board/csb637/csb637.c delete mode 100644 include/configs/csb637.h diff --git a/board/csb637/Makefile b/board/csb637/Makefile deleted file mode 100644 index a5484ae35d..0000000000 --- a/board/csb637/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := csb637.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/csb637/config.mk b/board/csb637/config.mk deleted file mode 100644 index e2cc8a6eea..0000000000 --- a/board/csb637/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23fc0000 diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c deleted file mode 100644 index d7fdcc4f73..0000000000 --- a/board/csb637/csb637.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of CSB637-Board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB637; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = bcm5221_InitPhy; - p_phyops->IsPhyConnected = bcm5221_IsPhyConnected; - p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed; - p_phyops->AutoNegotiate = bcm5221_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 61397fdade..e8be2caaff 100644 --- a/boards.cfg +++ b/boards.cfg @@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel eb_cpux9k2 arm arm920t - BuS at91 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -csb637 arm arm920t - - at91rm9200 kb9202 arm arm920t - - at91rm9200 m501sk arm arm920t - - at91rm9200 at91rm9200dk arm arm920t - atmel at91rm9200 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index f2b8ab18f0..e9d71a97bc 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +csb637 arm arm920t - 2011-07-17 cmc_pu2 arm arm920t - 2011-07-17 at91cap9adk arm arm926ejs - 2011-07-17 Stelian Pop voiceblue arm arm925t - 2011-07-17 diff --git a/include/configs/csb637.h b/include/configs/csb637.h deleted file mode 100644 index 7a85d65302..0000000000 --- a/include/configs/csb637.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * Configuation settings for the Cogent CSB637 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ -#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_CSB637 1 /* on a CSB637 board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PING - - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4 - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_AT91C_USE_RMII - -#undef CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 0 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -/* - * FLASH Device configuration - */ -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 - -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 3 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#undef CONFIG_ENV_IS_IN_DATAFLASH - -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ -#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ -#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ - - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } - -#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif From 5bd3814bb7abe1372c812c1628a753f8d60ec918 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:46 +0000 Subject: [PATCH 073/145] ARM: remove broken "kb9202" board Signed-off-by: Wolfgang Denk --- board/kb9202/Makefile | 53 ----------- board/kb9202/config.mk | 1 - board/kb9202/kb9202.c | 107 --------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/kb9202.h | 196 --------------------------------------- 6 files changed, 1 insertion(+), 358 deletions(-) delete mode 100644 board/kb9202/Makefile delete mode 100644 board/kb9202/config.mk delete mode 100644 board/kb9202/kb9202.c delete mode 100644 include/configs/kb9202.h diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile deleted file mode 100644 index 49be161fa2..0000000000 --- a/board/kb9202/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Adapted for KwikByte KB920x boards - APR2005 -# -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := kb9202.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/kb9202/config.mk b/board/kb9202/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/kb9202/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c deleted file mode 100644 index 3164cc5ac4..0000000000 --- a/board/kb9202/kb9202.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005 - */ - -#include -#include -#include -#include -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -void lowlevel_init(void) { - /* Required by assembly functions - do nothing */ -} - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_KB9200; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac); -UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac); -UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac); -UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status); - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = lxt972_InitPhy; - p_phyops->IsPhyConnected = lxt972_IsPhyConnected; - p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed; - p_phyops->AutoNegotiate = lxt972_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index e8be2caaff..35afd73f40 100644 --- a/boards.cfg +++ b/boards.cfg @@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel eb_cpux9k2 arm arm920t - BuS at91 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -kb9202 arm arm920t - - at91rm9200 m501sk arm arm920t - - at91rm9200 at91rm9200dk arm arm920t - atmel at91rm9200 mx1ads arm arm920t - - imx diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e9d71a97bc..88a5c1ce7e 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +kb9202 arm arm920t - 2011-07-17 csb637 arm arm920t - 2011-07-17 cmc_pu2 arm arm920t - 2011-07-17 at91cap9adk arm arm926ejs - 2011-07-17 Stelian Pop diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h deleted file mode 100644 index cfb7ceacc1..0000000000 --- a/include/configs/kb9202.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Rick Bronson - * - * Configuation settings for the AT91RM9200DK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ -#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -/* Only define one of the following, based on board type */ -/* #define CONFIG_KB9200 1 KwikByte KB9202 board */ -/* #define CONFIG_KB9201 1 KwikByte KB9202 board */ -#define CONFIG_KB9202 1 /* KwikByte KB9202 board */ - -#define CONFIG_KB920x 1 /* Any KB920x board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_SYS_LONGHELP - -#ifndef roundup -#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) -#endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (roundup(CONFIG_ENV_SIZE,4096) + 128*1024) - -#define CONFIG_BAUDRATE 115200 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_OVERWRITE 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC - - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 - -#define CONFIG_SYS_FLASH_BASE 0x10000000 - -#ifdef CONFIG_KB9202 -#define PHYS_FLASH_SIZE 0x1000000 -#else -#define PHYS_FLASH_SIZE 0x200000 -#endif - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_HARD_I2C - -#define CONFIG_ENV_IS_IN_EEPROM - -#ifdef CONFIG_KB9202 -#define CONFIG_ENV_OFFSET 0x3E00 -#define CONFIG_ENV_SIZE 0x0200 -#else -#define CONFIG_ENV_OFFSET 0x1000 -#define CONFIG_ENV_SIZE 0x1000 -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - -#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif From b1a2bd4bb3c23e48d60c4352b1c62037fd11435f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:47 +0000 Subject: [PATCH 074/145] ARM: remove broken "m501sk" board Signed-off-by: Wolfgang Denk --- board/m501sk/Makefile | 50 --------- board/m501sk/config.mk | 1 - board/m501sk/eeprom.c | 102 ------------------ board/m501sk/m501sk.c | 203 ---------------------------------- board/m501sk/m501sk.h | 167 ---------------------------- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/m501sk.h | 228 --------------------------------------- 8 files changed, 1 insertion(+), 752 deletions(-) delete mode 100644 board/m501sk/Makefile delete mode 100644 board/m501sk/config.mk delete mode 100644 board/m501sk/eeprom.c delete mode 100644 board/m501sk/m501sk.c delete mode 100644 board/m501sk/m501sk.h delete mode 100644 include/configs/m501sk.h diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile deleted file mode 100644 index 439e99f673..0000000000 --- a/board/m501sk/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := m501sk.o eeprom.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/m501sk/config.mk b/board/m501sk/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/m501sk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/m501sk/eeprom.c b/board/m501sk/eeprom.c deleted file mode 100644 index d1a46f348b..0000000000 --- a/board/m501sk/eeprom.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Add by Alan Lu, 07-29-2005 - * For ATMEL AT24C16 EEPROM - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#ifdef CONFIG_SYS_EEPROM_AT24C16 -#undef DEBUG - -void eeprom_init(void) -{ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif -} - -int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) -{ - int page, count = 0, i = 0; - page = offset / 0x100; - i = offset % 0x100; - - while (count < cnt) { - if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0) - return 1; - if (i > 0xff) { - page++; - i = 0; - } - } - - return 0; -} - -/* - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is - * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. - * - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is - * 0x00000nxx for EEPROM address selectors and page number at n. - */ -int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) -{ - int page, i = 0, count = 0; - - page = offset / 0x100; - i = offset % 0x100; - - while (count < cnt) { - if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0) - return 1; - if (i > 0xff) { - page++; - i = 0; - } - } - -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - - return 0; -} - -#ifndef CONFIG_SPI -int eeprom_probe(unsigned dev_addr, unsigned offset) -{ - unsigned char chip; - - /* Probe the chip address */ -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) - chip = offset >> 8; /* block number */ -#else - chip = offset >> 16; /* block number */ -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ - - chip |= dev_addr; /* insert device address */ - return (i2c_probe(chip)); -} -#endif -#endif diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c deleted file mode 100644 index c9957684b1..0000000000 --- a/board/m501sk/m501sk.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2008 - * Based on modifications by Alan Lu / Artila - * Author : Timo Tuunainen / Sysart - Kimmo Leppala / Sysart - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif - -#include "m501sk.h" -#include "net.h" - -#ifdef CONFIG_M501SK - -void m501sk_gpio_init(void) -{ - AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) | - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); - - AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) | - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); - - AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96); - AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96); - AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32); - AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32); - AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8); - - /* Power OFF all USART's LEDs */ - AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; - AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; - AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; -} - -uchar m501sk_gpio_set(M501SK_PIO io) -{ - uchar status = 0xff; - switch (io) { - case M501SK_DEBUG_LED1: - case M501SK_DEBUG_LED2: - case M501SK_DEBUG_LED3: - case M501SK_DEBUG_LED4: - case M501SK_READY_LED: - AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96); - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); - break; - case M501SK_BUZZER: - AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32); - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); - break; - } - return status; -} - -uchar m501sk_gpio_clear(M501SK_PIO io) -{ - uchar status = 0xff; - switch (io) { - case M501SK_DEBUG_LED1: - case M501SK_DEBUG_LED2: - case M501SK_DEBUG_LED3: - case M501SK_DEBUG_LED4: - case M501SK_READY_LED: - AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96); - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); - break; - case M501SK_BUZZER: - AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32); - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); - break; - } - return status; -} - -/* - * Miscelaneous platform dependent initialisations - */ -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* Enable Ctrlc */ - console_init_f(); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - ((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - gd->bd->bi_arch_number = MACH_TYPE_M501; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - m501sk_gpio_init(); - - /* Do interrupt init here, because flash needs timers */ - timer_init(); - flash_init(); - - return 0; -} - -int dram_init(void) -{ - int i = 0; - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - - for (i = 0; i < 500; i++) { - m501sk_gpio_clear(M501SK_DEBUG_LED3); - m501sk_gpio_clear(M501SK_BUZZER); - udelay(250); - m501sk_gpio_set(M501SK_DEBUG_LED3); - m501sk_gpio_set(M501SK_BUZZER); - udelay(80); - } - m501sk_gpio_clear(M501SK_BUZZER); - m501sk_gpio_clear(M501SK_DEBUG_LED3); - - return 0; -} - -int board_late_init(void) -{ -#if defined(CONFIG_CMD_NET) - eth_init(gd->bd); - eth_halt(); -#endif - - /* Protect U-Boot, kernel & ramdisk memory addresses */ - run_command("protect on 10000000 1041ffff", 0); - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif -#endif /* CONFIG_M501SK */ diff --git a/board/m501sk/m501sk.h b/board/m501sk/m501sk.h deleted file mode 100644 index 51d10f58a9..0000000000 --- a/board/m501sk/m501sk.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * linux/include/asm/arch-at91/hardware.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __M501SK_H -#define __M501SK_H - -#ifndef __ASSEMBLY__ -#include -#else -#include -#endif - -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */ -#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */ -#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 TxD */ -#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */ - -/* ========== Register definition for PIOD peripheral ========== */ -#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */ -#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */ -#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */ -#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */ -#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */ -#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */ -#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */ -#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */ -#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */ -#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */ -#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */ -#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */ -#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */ -#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */ -#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */ -#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */ -#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */ -#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */ -#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */ -#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */ -#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */ -#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */ -#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */ -#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */ -#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */ -#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */ -#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */ -#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */ -#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */ - -#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */ -#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Enet MAC Tx Data 0*/ -#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */ -#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Enet MAC Tx Data 1*/ -#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */ -#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/ -#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */ -#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */ -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */ -#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */ -#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */ -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */ -#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */ -#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */ -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */ -#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */ -#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */ -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */ -#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */ -#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */ -#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */ -#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */ -#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */ -#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */ -#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */ -#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */ -#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */ -#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */ -#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */ -#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Perip CS 1 */ -#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */ -#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */ -#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Perip CS 2 */ -#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */ -#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */ -#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC TxD 2 */ -#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */ -#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */ -#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */ -#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */ -#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */ -#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */ -#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */ -#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 RTS */ -#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */ -#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */ -#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */ -#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */ -#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */ -#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 RTS */ -#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */ -#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */ -#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */ -#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */ -#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */ -#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */ -#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */ -#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */ -#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */ -#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Enet MAC TxD 3 */ -#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */ -#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */ -#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */ -#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Enet MAC TxCE */ -#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */ -#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */ -#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */ -#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/ -#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */ -#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */ -#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/ -#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */ -#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */ -#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */ -#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ -#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) -#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) - -typedef enum { - M501SK_BUZZER = 38, - M501SK_DEBUG_LED1 = 96, - M501SK_DEBUG_LED2, - M501SK_DEBUG_LED3, - M501SK_DEBUG_LED4, - M501SK_READY_LED = 102, -} M501SK_PIO; - -void m501sk_gpio_init(void); -uchar m501sk_gpio_set(M501SK_PIO io); -uchar m501sk_gpio_clear(M501SK_PIO io); - -#endif diff --git a/boards.cfg b/boards.cfg index 35afd73f40..331267dc20 100644 --- a/boards.cfg +++ b/boards.cfg @@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel eb_cpux9k2 arm arm920t - BuS at91 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -m501sk arm arm920t - - at91rm9200 at91rm9200dk arm arm920t - atmel at91rm9200 mx1ads arm arm920t - - imx scb9328 arm arm920t - - imx diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 88a5c1ce7e..e49d1f78ce 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +m501sk arm arm920t - 2011-07-17 kb9202 arm arm920t - 2011-07-17 csb637 arm arm920t - 2011-07-17 cmc_pu2 arm arm920t - 2011-07-17 diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h deleted file mode 100644 index 68f0415a37..0000000000 --- a/include/configs/m501sk.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Based on Modifications by Alan Lu / Artila and - * Rick Bronson - * - * Configuration settings for the Artila M-501 starter kit, - * with V02 processor card. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -/* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MAIN_CLOCK 179712000 -/* Perip clock (AT91C_MASTER_CLOCK / 3) */ -#define AT91C_MASTER_CLOCK 59904000 -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_MENUPROMPT "." -/* - * LowLevel Init - */ -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_BAUDRATE 115200 - -/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 - -/* - * Hardware drivers - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100 -#define CONFIG_SYS_I2C_SLAVE 0 -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#undef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_AT24C16 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#undef CONFIG_RTC_DS1338 -#define CONFIG_RTC_RS5C372A -#undef CONFIG_POST -#define CONFIG_M501SK -#define CONFIG_CMC_PU2 - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \ - "initrd=0x20800000,8192000 ramdisk_size=15360 " \ - "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \ - "128k(loader)ro,128k(reserved)ro,1408k(linux)" \ - "ro,2560k(ramdisk)ro,-(userdisk)" -#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000" -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.254 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_BOOTFILE uImage -#define CONFIG_ETHADDR 00:13:48:aa:bb:cc -#define CONFIG_ENV_OVERWRITE 1 -#define BOARD_LATE_INIT - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "unlock=yes\0" - -#define CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_EEPROM -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_POST -#define CONFIG_CMD_MISC -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_IMI -#define CONFIG_CMD_NFS -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>" - -#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */ - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */ -/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000) -#define CONFIG_ENV_SIZE 2048 -#endif - -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 1024 -#define CONFIG_ENV_SIZE 1024 -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -/* use for protect flash sectors */ -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 } - -#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif From 1c8575225825b507573d0cac9c51b3611949ba01 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 26 Aug 2011 02:25:48 +0000 Subject: [PATCH 075/145] ARM: remove broken "at91rm9200dk" board Signed-off-by: Wolfgang Denk --- board/atmel/at91rm9200dk/Makefile | 56 --- board/atmel/at91rm9200dk/at91rm9200dk.c | 167 -------- board/atmel/at91rm9200dk/config.mk | 1 - board/atmel/at91rm9200dk/flash.c | 504 ------------------------ board/atmel/at91rm9200dk/led.c | 80 ---- board/atmel/at91rm9200dk/mux.c | 29 -- board/atmel/at91rm9200dk/partition.c | 40 -- boards.cfg | 1 - doc/README.scrapyard | 1 + include/configs/at91rm9200dk.h | 202 ---------- 10 files changed, 1 insertion(+), 1080 deletions(-) delete mode 100644 board/atmel/at91rm9200dk/Makefile delete mode 100644 board/atmel/at91rm9200dk/at91rm9200dk.c delete mode 100644 board/atmel/at91rm9200dk/config.mk delete mode 100644 board/atmel/at91rm9200dk/flash.c delete mode 100644 board/atmel/at91rm9200dk/led.c delete mode 100644 board/atmel/at91rm9200dk/mux.c delete mode 100644 board/atmel/at91rm9200dk/partition.c delete mode 100644 include/configs/at91rm9200dk.h diff --git a/board/atmel/at91rm9200dk/Makefile b/board/atmel/at91rm9200dk/Makefile deleted file mode 100644 index bc3dbc609d..0000000000 --- a/board/atmel/at91rm9200dk/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += flash.o -COBJS-y += led.o -ifdef CONFIG_HAS_DATAFLASH -COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o -COBJS-y += partition.o -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atmel/at91rm9200dk/at91rm9200dk.c b/board/atmel/at91rm9200dk/at91rm9200dk.c deleted file mode 100644 index 49b5fe3203..0000000000 --- a/board/atmel/at91rm9200dk/at91rm9200dk.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of AT91RM9200DK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -void board_reset (void) -{ - AT91PS_PIO pio = AT91C_BASE_PIOA; - - /* Clear PA19 to trigger the hard reset */ - writel(0x00080000, pio->PIO_CODR); - writel(0x00080000, pio->PIO_OER); - writel(0x00080000, pio->PIO_PER); -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if defined(CONFIG_CMD_NAND) -extern ulong nand_probe (ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void nand_init (void) -{ - /* Setup Smart Media, fitst enable the address range of CS3 */ - *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; - /* set the bus interface characteristics based on - tDS Data Set up Time 30 - ns - tDH Data Hold Time 20 - ns - tALS ALE Set up Time 20 - ns - 16ns at 60 MHz ~= 3 */ -/*memory mapping structures */ -#define SM_ID_RWH (5 << 28) -#define SM_RWH (1 << 28) -#define SM_RWS (0 << 24) -#define SM_TDF (1 << 8) -#define SM_NWS (3) - AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | - AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | - SM_TDF | AT91C_SMC2_WSEN | SM_NWS); - - /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ - *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - - /* Configure PC2 as input (signal READY of the SmartMedia) */ - *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ - *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ - - /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ - *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ - *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) - printf (" No SmartMedia card inserted\n"); -#ifdef DEBUG - printf (" SmartMedia card inserted\n"); - - printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); -#endif - printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); -} -#endif diff --git a/board/atmel/at91rm9200dk/config.mk b/board/atmel/at91rm9200dk/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/atmel/at91rm9200dk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c deleted file mode 100644 index be2274362c..0000000000 --- a/board/atmel/at91rm9200dk/flash.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush(void); - - -/* Flash Organization Structure */ -typedef struct OrgDef -{ - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgAT49BV16x4[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ - { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV16x4A[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV6416[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ -}; - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* AT49BV1614A Codes */ -#define FLASH_CODE1 0xAA -#define FLASH_CODE2 0x55 -#define ID_IN_CODE 0x90 -#define ID_OUT_CODE 0xF0 - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 -#define CMD_SECTOR_UNLOCK 0x0070 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ -void flash_identification (flash_info_t * info) -{ - volatile u16 manuf_code, device_code, add_device_code; - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_IN_CODE; - - manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE; - device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2); - add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1)); - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_OUT_CODE; - - /* Vendor type */ - info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; - printf ("Atmel: "); - - if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - if ((add_device_code & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; - printf ("AT49BV1614A (16Mbit)\n"); - } else { /* AT49BV1614 Flash */ - info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; - printf ("AT49BV1614 (16Mbit)\n"); - } - - } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; - printf ("AT49BV6416 (64Mbit)\n"); - } -} - -ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) -{ - int i, nb_sectors = 0; - - for (i=0; istart[sector]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - *addr = CMD_SECTOR_UNLOCK; -} - - -ulong flash_init (void) -{ - int i, j, k; - unsigned int flash_nb_blocks, sector; - unsigned int start_address; - OrgDef *pOrgDef; - - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_identification (&flash_info[i]); - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - pOrgDef = OrgAT49BV16x4; - flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ - - pOrgDef = OrgAT49BV16x4A; - flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - pOrgDef = OrgAT49BV6416; - flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); - } else { - flash_nb_blocks = 0; - pOrgDef = OrgAT49BV16x4; - } - - flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); - memset (flash_info[i].protect, 0, flash_info[i].sector_count); - - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - - sector = 0; - start_address = flashbase; - flash_info[i].size = 0; - - for (j = 0; j < flash_nb_blocks; j++) { - for (k = 0; k < pOrgDef[j].sector_number; k++) { - flash_info[i].start[sector++] = start_address; - start_address += pOrgDef[j].sector_size; - flash_info[i].size += pOrgDef[j].sector_size; - } - } - - size += flash_info[i].size; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - /* Unlock all sectors at reset */ - for (j=0; jflash_id & FLASH_VENDMASK) { - case (ATM_MANUFACT & FLASH_VENDMASK): - printf ("Atmel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (ATM_ID_BV1614 & FLASH_TYPEMASK): - printf ("AT49BV1614 (16Mbit)\n"); - break; - case (ATM_ID_BV1614A & FLASH_TYPEMASK): - printf ("AT49BV1614A (16Mbit)\n"); - break; - case (ATM_ID_BV6416 & FLASH_TYPEMASK): - printf ("AT49BV6416 (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (ATM_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << - 8); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - }; - - return ERR_OK; -} diff --git a/board/atmel/at91rm9200dk/led.c b/board/atmel/at91rm9200dk/led.c deleted file mode 100644 index 47a3bfce68..0000000000 --- a/board/atmel/at91rm9200dk/led.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB - * Ulf Samuelsson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define GREEN_LED AT91C_PIO_PB0 -#define YELLOW_LED AT91C_PIO_PB1 -#define RED_LED AT91C_PIO_PB2 - -void green_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = GREEN_LED; -} - -void yellow_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = YELLOW_LED; -} - -void red_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = RED_LED; -} - -void green_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = GREEN_LED; -} - -void yellow_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = YELLOW_LED; -} - -void red_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = RED_LED; -} - - -void coloured_LED_init (void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - AT91PS_PMC PMC = AT91C_BASE_PMC; - PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */ - /* Disable peripherals on LEDs */ - PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - /* Enable pins as outputs */ - PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - /* Turn all LEDs OFF */ - PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; -} diff --git a/board/atmel/at91rm9200dk/mux.c b/board/atmel/at91rm9200dk/mux.c deleted file mode 100644 index a00563ede8..0000000000 --- a/board/atmel/at91rm9200dk/mux.c +++ /dev/null @@ -1,29 +0,0 @@ -#include -#include -#include -#include - -int AT91F_GetMuxStatus(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - - - if(AT91C_BASE_PIOB->PIO_ODSR & CONFIG_SYS_DATAFLASH_MMC_PIO) - return 1; - - return 0; -} - -void AT91F_SelectMMC(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - /* Set Output */ - AT91C_BASE_PIOB->PIO_SODR = CONFIG_SYS_DATAFLASH_MMC_PIO; -} - -void AT91F_SelectSPI(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = CONFIG_SYS_DATAFLASH_MMC_PIO; -} diff --git a/board/atmel/at91rm9200dk/partition.c b/board/atmel/at91rm9200dk/partition.c deleted file mode 100644 index c739b116bf..0000000000 --- a/board/atmel/at91rm9200dk/partition.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2008 - * Ulf Samuelsson - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#include -#include -#include -#include - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3} -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, -}; diff --git a/boards.cfg b/boards.cfg index 331267dc20..12c82df77b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -57,7 +57,6 @@ at91rm9200ek_ram arm arm920t at91rm9200ek atmel eb_cpux9k2 arm arm920t - BuS at91 cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT -at91rm9200dk arm arm920t - atmel at91rm9200 mx1ads arm arm920t - - imx scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e49d1f78ce..8da6db6a45 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +at91rm9200dk arm arm920t - 2011-07-17 m501sk arm arm920t - 2011-07-17 kb9202 arm arm920t - 2011-07-17 csb637 arm arm920t - 2011-07-17 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h deleted file mode 100644 index 15de310304..0000000000 --- a/include/configs/at91rm9200dk.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Rick Bronson - * - * Configuration settings for the AT91RM9200DK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_BAUDRATE 115200 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII - -#include /* needed for port definitions */ - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif - -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#undef CONFIG_ENV_IS_IN_DATAFLASH - -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -#define CONFIG_ENV_OFFSET 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ -#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ - - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#else -#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 -#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } - -#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif From 39d3416f0afc43d56fc47b74c75388580033c3bb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 30 Aug 2011 06:23:12 +0000 Subject: [PATCH 076/145] Tegra2: Add microsecond timer function These functions provide access to the high resolution microsecond timer and tidy up a global variable in the code. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/timer.c | 18 +++++++++----- arch/arm/include/asm/arch-tegra2/timer.h | 30 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/timer.h diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c index 0b9fa6418c..b12b12cc30 100644 --- a/arch/arm/cpu/armv7/tegra2/timer.c +++ b/arch/arm/cpu/armv7/tegra2/timer.c @@ -38,13 +38,12 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; - /* counter runs at 1MHz */ -#define TIMER_CLK (1000000) +#define TIMER_CLK 1000000 #define TIMER_LOAD_VAL 0xffffffff /* timer without interrupts */ @@ -57,10 +56,10 @@ ulong get_timer(ulong base) void __udelay(unsigned long usec) { long tmo = usec * (TIMER_CLK / 1000) / 1000; - unsigned long now, last = readl(&timer_base->cntr_1us); + unsigned long now, last = timer_get_us(); while (tmo > 0) { - now = readl(&timer_base->cntr_1us); + now = timer_get_us(); if (last > now) /* count up timer overflow */ tmo -= TIMER_LOAD_VAL - last + now; else @@ -74,7 +73,7 @@ ulong get_timer_masked(void) ulong now; /* current tick value */ - now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ); + now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ); if (now >= gd->lastinc) /* normal mode (non roll) */ /* move stamp forward with absolute diff ticks */ @@ -103,3 +102,10 @@ ulong get_tbclk(void) { return CONFIG_SYS_HZ; } + +unsigned long timer_get_us(void) +{ + struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; + + return readl(&timer_base->cntr_1us); +} diff --git a/arch/arm/include/asm/arch-tegra2/timer.h b/arch/arm/include/asm/arch-tegra2/timer.h new file mode 100644 index 0000000000..adefa2c6c1 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/timer.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 timer functions */ + +#ifndef _TEGRA2_TIMER_H +#define _TEGRA2_TIMER_H + +/* returns the current monotonic timer value in microseconds */ +unsigned long timer_get_us(void); + +#endif From b4ba2be8dc2711ad2219186e89b4e10648d52af9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 30 Aug 2011 06:23:13 +0000 Subject: [PATCH 077/145] Tegra2: Add more clock support This adds functions to enable/disable clocks and reset to on-chip peripherals. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/Makefile | 2 +- arch/arm/cpu/armv7/tegra2/ap20.c | 52 ++-- arch/arm/cpu/armv7/tegra2/clock.c | 158 +++++++++++++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 112 +++++---- arch/arm/include/asm/arch-tegra2/clock.h | 263 +++++++++++++++++++++ board/nvidia/common/board.c | 79 ++----- 6 files changed, 524 insertions(+), 142 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/clock.c create mode 100644 arch/arm/include/asm/arch-tegra2/clock.h diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f1ea915851..b35764c321 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o sys_info.o timer.o +COBJS := ap20.o board.o clock.o sys_info.o timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 60dd5dfc08..e3832e23f3 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -35,33 +36,34 @@ u32 s_first_boot = 1; void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU]; u32 reg; /* If PLLX is already enabled, just return */ - reg = readl(&clkrst->crc_pllx_base); + reg = readl(&pll->pll_base); if (reg & PLL_ENABLE) return; /* Set PLLX_MISC */ reg = CPCON; /* CPCON[11:8] = 0001 */ - writel(reg, &clkrst->crc_pllx_misc); + writel(reg, &pll->pll_misc); /* Use 12MHz clock here */ - reg = (PLL_BYPASS | PLL_DIVM); + reg = (PLL_BYPASS | PLL_DIVM_VALUE); reg |= (1000 << 8); /* DIVN = 0x3E8 */ - writel(reg, &clkrst->crc_pllx_base); + writel(reg, &pll->pll_base); reg |= PLL_ENABLE; - writel(reg, &clkrst->crc_pllx_base); + writel(reg, &pll->pll_base); reg &= ~PLL_BYPASS; - writel(reg, &clkrst->crc_pllx_base); + writel(reg, &pll->pll_base); } static void enable_cpu_clock(int enable) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 reg, clk; + u32 clk; /* * NOTE: @@ -83,10 +85,6 @@ static void enable_cpu_clock(int enable) writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); } - /* Fetch the register containing the main CPU complex clock enable */ - reg = readl(&clkrst->crc_clk_out_enb_l); - reg |= CLK_ENB_CPU; - /* * Read the register containing the individual CPU clock enables and * always stop the clock to CPU 1. @@ -103,7 +101,8 @@ static void enable_cpu_clock(int enable) } writel(clk, &clkrst->crc_clk_cpu_cmplx); - writel(reg, &clkrst->crc_clk_out_enb_l); + + clock_enable(PERIPH_ID_CPU); } static int is_cpu_powered(void) @@ -179,7 +178,7 @@ static void enable_cpu_power_rail(void) static void reset_A9_cpu(int reset) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 reg, cpu; + u32 cpu; /* * NOTE: Regardless of whether the request is to hold the CPU in reset @@ -193,44 +192,27 @@ static void reset_A9_cpu(int reset) cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; writel(cpu, &clkrst->crc_cpu_cmplx_set); - reg = readl(&clkrst->crc_rst_dev_l); if (reset) { /* Now place CPU0 into reset */ cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; writel(cpu, &clkrst->crc_cpu_cmplx_set); - - /* Enable master CPU reset */ - reg |= SWR_CPU_RST; } else { /* Take CPU0 out of reset */ cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; writel(cpu, &clkrst->crc_cpu_cmplx_clr); - - /* Disable master CPU reset */ - reg &= ~SWR_CPU_RST; } - writel(reg, &clkrst->crc_rst_dev_l); + /* Enable/Disable master CPU reset */ + reset_set_enable(PERIPH_ID_CPU, reset); } static void clock_enable_coresight(int enable) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 rst, clk, src; + u32 rst, src; - rst = readl(&clkrst->crc_rst_dev_u); - clk = readl(&clkrst->crc_clk_out_enb_u); - - if (enable) { - rst &= ~SWR_CSITE_RST; - clk |= CLK_ENB_CSITE; - } else { - rst |= SWR_CSITE_RST; - clk &= ~CLK_ENB_CSITE; - } - - writel(clk, &clkrst->crc_clk_out_enb_u); - writel(rst, &clkrst->crc_rst_dev_u); + clock_set_enable(PERIPH_ID_CORESIGHT, enable); + reset_set_enable(PERIPH_ID_CORESIGHT, !enable); if (enable) { /* diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c new file mode 100644 index 0000000000..67eed14044 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 Clock control functions */ + +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define assert(x) \ + ({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \ + #x, __FILE__, __LINE__); }) +#else +#define assert(x) +#endif + +/* + * Get the oscillator frequency, from the corresponding hardware configuration + * field. + */ +enum clock_osc_freq clock_get_osc_freq(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + reg = readl(&clkrst->crc_osc_ctrl); + return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; +} + +unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, + u32 divp, u32 cpcon, u32 lfcon) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 data; + struct clk_pll *pll; + + assert(clock_pll_id_isvalid(clkid)); + pll = &clkrst->crc_pll[clkid]; + + /* + * We cheat by treating all PLL (except PLLU) in the same fashion. + * This works only because: + * - same fields are always mapped at same offsets, except DCCON + * - DCCON is always 0, doesn't conflict + * - M,N, P of PLLP values are ignored for PLLP + */ + data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); + writel(data, &pll->pll_misc); + + data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | + (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); + + if (clkid == CLOCK_PLL_ID_USB) + data |= divp << PLLU_VCO_FREQ_SHIFT; + else + data |= divp << PLL_DIVP_SHIFT; + writel(data, &pll->pll_base); + + /* calculate the stable time */ + return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; +} + +void clock_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; + u32 reg; + + /* Enable/disable the clock to this peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + reg = readl(clk); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, clk); +} + +void clock_enable(enum periph_id clkid) +{ + clock_set_enable(clkid, 1); +} + +void clock_disable(enum periph_id clkid) +{ + clock_set_enable(clkid, 0); +} + +void reset_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; + u32 reg; + + /* Enable/disable reset to the peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + reg = readl(reset); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, reset); +} + +void reset_periph(enum periph_id periph_id, int us_delay) +{ + /* Put peripheral into reset */ + reset_set_enable(periph_id, 1); + udelay(us_delay); + + /* Remove reset */ + reset_set_enable(periph_id, 0); + + udelay(us_delay); +} + +void reset_cmplx_set_enable(int cpu, int which, int reset) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 mask; + + /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */ + assert(cpu >= 0 && cpu < 2); + mask = which << cpu; + + /* either enable or disable those reset for that CPU */ + if (reset) + writel(mask, &clkrst->crc_cpu_cmplx_set); + else + writel(mask, &clkrst->crc_cpu_cmplx_clr); +} diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 36e27b5f3f..a574c5355d 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -24,15 +24,34 @@ #ifndef _CLK_RST_H_ #define _CLK_RST_H_ +/* PLL registers - there are several PLLs in the clock controller */ +struct clk_pll { + uint pll_base; /* the control register */ + uint pll_out; /* output control */ + uint reserved; + uint pll_misc; /* other misc things */ +}; + +/* PLL registers - there are several PLLs in the clock controller */ +struct clk_pll_simple { + uint pll_base; /* the control register */ + uint pll_misc; /* other misc things */ +}; + +/* + * Most PLLs use the clk_pll structure, but some have a simpler two-member + * structure for which we use clk_pll_simple. The reason for this non- + * othogonal setup is not stated. + */ +#define TEGRA_CLK_PLLS 6 +#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */ +#define TEGRA_CLK_REGS 3 /* Number of clock enable registers */ + /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ struct clk_rst_ctlr { - uint crc_rst_src; /* _RST_SOURCE_0, 0x00 */ - uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04 */ - uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08 */ - uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C */ - uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10 */ - uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14 */ - uint crc_clk_out_enb_u; /* _CLK_OUT_ENB_U_0, 0x18 */ + uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ + uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ + uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ uint crc_reserved0; /* reserved_0, 0x1C */ uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ @@ -52,44 +71,11 @@ struct clk_rst_ctlr { uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - uint crc_pllc_base; /* _PLLC_BASE_0, 0x80 */ - uint crc_pllc_out; /* _PLLC_OUT_0, 0x84 */ - uint crc_reserved3; /* reserved_3, 0x88 */ - uint crc_pllc_misc; /* _PLLC_MISC_0, 0x8C */ + struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - uint crc_pllm_base; /* _PLLM_BASE_0, 0x90 */ - uint crc_pllm_out; /* _PLLM_OUT_0, 0x94 */ - uint crc_reserved4; /* reserved_4, 0x98 */ - uint crc_pllm_misc; /* _PLLM_MISC_0, 0x9C */ + /* PLLs from 0xe0 to 0xf4 */ + struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0 */ - uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4 */ - uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8 */ - uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC */ - - uint crc_plla_base; /* _PLLA_BASE_0, 0xB0 */ - uint crc_plla_out; /* _PLLA_OUT_0, 0xB4 */ - uint crc_reserved5; /* reserved_5, 0xB8 */ - uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC */ - - uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0 */ - uint crc_reserved6; /* _reserved_6, 0xC4 */ - uint crc_reserved7; /* _reserved_7, 0xC8 */ - uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC */ - - uint crc_plld_base; /* _PLLD_BASE_0, 0xD0 */ - uint crc_reserved8; /* _reserved_8, 0xD4 */ - uint crc_reserved9; /* _reserved_9, 0xD8 */ - uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC */ - - uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0 */ - uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4 */ - - uint crc_plle_base; /* _PLLE_BASE_0, 0xE8 */ - uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC */ - - uint crc_plls_base; /* _PLLS_BASE_0, 0xF0 */ - uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4 */ uint crc_reserved10; /* _reserved_10, 0xF8 */ uint crc_reserved11; /* _reserved_11, 0xFC */ @@ -157,8 +143,8 @@ struct clk_rst_ctlr { #define PLL_BYPASS (1 << 31) #define PLL_ENABLE (1 << 30) #define PLL_BASE_OVRRIDE (1 << 28) -#define PLL_DIVP (1 << 20) /* post divider, b22:20 */ -#define PLL_DIVM 0x0C /* input divider, b4:0 */ +#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */ +#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */ #define SWR_UARTD_RST (1 << 1) #define CLK_ENB_UARTD (1 << 1) @@ -191,9 +177,37 @@ struct clk_rst_ctlr { #define CPCON (1 << 8) -#define SWR_SDMMC4_RST (1 << 15) -#define CLK_ENB_SDMMC4 (1 << 15) -#define SWR_SDMMC3_RST (1 << 5) -#define CLK_ENB_SDMMC3 (1 << 5) +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ +#define CPU1_CLK_STP_SHIFT 9 + +#define CPU0_CLK_STP_SHIFT 8 +#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) + +/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ +#define PLL_BYPASS_SHIFT 31 +#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) + +#define PLL_ENABLE_SHIFT 30 +#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) + +#define PLL_BASE_OVRRIDE_MASK (1U << 28) + +#define PLL_DIVP_SHIFT 20 + +#define PLL_DIVN_SHIFT 8 + +#define PLL_DIVM_SHIFT 0 + +/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ +#define PLL_CPCON_SHIFT 8 +#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) + +#define PLL_LFCON_SHIFT 4 + +#define PLLU_VCO_FREQ_SHIFT 20 + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 30 +#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h new file mode 100644 index 0000000000..d01aec825d --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 clock control functions */ + +#ifndef _CLOCK_H + + +/* Set of oscillator frequencies supported in the internal API. */ +enum clock_osc_freq { + /* All in MHz, so 13_0 is 13.0MHz */ + CLOCK_OSC_FREQ_13_0, + CLOCK_OSC_FREQ_19_2, + CLOCK_OSC_FREQ_12_0, + CLOCK_OSC_FREQ_26_0, + + CLOCK_OSC_FREQ_COUNT, +}; + +/* The PLLs supported by the hardware */ +enum clock_pll_id { + CLOCK_PLL_ID_FIRST, + CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST, + CLOCK_PLL_ID_MEMORY, + CLOCK_PLL_ID_PERIPH, + CLOCK_PLL_ID_AUDIO, + CLOCK_PLL_ID_USB, + CLOCK_PLL_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_PLL_ID_FIRST_SIMPLE, + CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE, + CLOCK_PLL_ID_EPCI, + CLOCK_PLL_ID_SFROM32KHZ, + + CLOCK_PLL_ID_COUNT, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_RESERVED1, + PERIPH_ID_RESERVED2, + PERIPH_ID_AC97, + PERIPH_ID_RTC, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S1, + PERIPH_ID_I2C1, + PERIPH_ID_NDFLASH, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TWC, + PERIPH_ID_PWC, + PERIPH_ID_I2S2, + PERIPH_ID_EPP, + PERIPH_ID_VI, + PERIPH_ID_2D, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_3D, + PERIPH_ID_IDE, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_RESERVED30, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_KBC, + PERIPH_ID_STAT_MON, + PERIPH_ID_PMC, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_SPI1, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_DVC_I2C, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_TVO, + PERIPH_ID_MIPI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_TVDAC, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_RESERVED56, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_MPE, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 */ + PERIPH_ID_SPEEDO, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_RESERVED74, + PERIPH_ID_AVPUCQ, + PERIPH_ID_RESERVED76, + PERIPH_ID_RESERVED77, + PERIPH_ID_RESERVED78, + PERIPH_ID_RESERVED79, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_RESERVED81, + PERIPH_ID_RESERVED82, + PERIPH_ID_RESERVED83, + PERIPH_ID_IRAMA, + PERIPH_ID_IRAMB, + PERIPH_ID_IRAMC, + PERIPH_ID_IRAMD, + + /* 88 */ + PERIPH_ID_CRAM2, + + PERIPH_ID_COUNT, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ +#define PERIPH_REG(id) ((id) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \ + (id) < CLOCK_PLL_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +/* return the current oscillator clock frequency */ +enum clock_osc_freq clock_get_osc_freq(void); + +/* + * Start PLL using the provided configuration parameters. + * + * @param id clock id + * @param divm input divider + * @param divn feedback divider + * @param divp post divider 2^n + * @param cpcon charge pump setup control + * @param lfcon loop filter setup control + * + * @returns monotonic time in us that the PLL will be stable + */ +unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, + u32 divp, u32 cpcon, u32 lfcon); + +/* + * Enable a clock + * + * @param id clock id + */ +void clock_enable(enum periph_id clkid); + +/* + * Set whether a clock is enabled or disabled. + * + * @param id clock id + * @param enable 1 to enable, 0 to disable + */ +void clock_set_enable(enum periph_id clkid, int enable); + +/* + * Reset a peripheral. This puts it in reset, waits for a delay, then takes + * it out of reset and waits for th delay again. + * + * @param periph_id peripheral to reset + * @param us_delay time to delay in microseconds + */ +void reset_periph(enum periph_id periph_id, int us_delay); + +/* + * Put a peripheral into or out of reset. + * + * @param periph_id peripheral to reset + * @param enable 1 to put into reset, 0 to take out of reset + */ +void reset_set_enable(enum periph_id periph_id, int enable); + + +/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ +enum crc_reset_id { + /* Things we can hold in reset for each CPU */ + crc_rst_cpu = 1, + crc_rst_de = 1 << 2, /* What is de? */ + crc_rst_watchdog = 1 << 3, + crc_rst_debug = 1 << 4, +}; + +/* + * Put parts of the CPU complex into or out of reset.\ + * + * @param cpu cpu number (0 or 1 on Tegra2) + * @param which which parts of the complex to affect (OR of crc_reset_id) + * @param reset 1 to assert reset, 0 to de-assert + */ +void reset_cmplx_set_enable(int cpu, int which, int reset); + +#endif diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 5eca5eb344..945141e7d3 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include "board.h" @@ -76,33 +77,28 @@ int timer_init(void) static void clock_init_uart(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH]; u32 reg; - reg = readl(&clkrst->crc_pllp_base); + reg = readl(&pll->pll_base); if (!(reg & PLL_BASE_OVRRIDE)) { /* Override pllp setup for 216MHz operation. */ - reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP); - reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM); - writel(reg, &clkrst->crc_pllp_base); + reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE); + reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE); + writel(reg, &pll->pll_base); reg |= PLL_ENABLE; - writel(reg, &clkrst->crc_pllp_base); + writel(reg, &pll->pll_base); reg &= ~PLL_BYPASS; - writel(reg, &clkrst->crc_pllp_base); + writel(reg, &pll->pll_base); } /* Now do the UART reset/clock enable */ #if defined(CONFIG_TEGRA2_ENABLE_UARTA) - /* Assert Reset to UART */ - reg = readl(&clkrst->crc_rst_dev_l); - reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_l); - - /* Enable clk to UART */ - reg = readl(&clkrst->crc_clk_out_enb_l); - reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_l); + /* Assert UART reset and enable clock */ + reset_set_enable(PERIPH_ID_UART1, 1); + clock_enable(PERIPH_ID_UART1); /* Enable pllp_out0 to UART */ reg = readl(&clkrst->crc_clk_src_uarta); @@ -113,20 +109,12 @@ static void clock_init_uart(void) udelay(2); /* De-assert reset to UART */ - reg = readl(&clkrst->crc_rst_dev_l); - reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_l); + reset_set_enable(PERIPH_ID_UART1, 0); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) - /* Assert Reset to UART */ - reg = readl(&clkrst->crc_rst_dev_u); - reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_u); - - /* Enable clk to UART */ - reg = readl(&clkrst->crc_clk_out_enb_u); - reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_u); + /* Assert UART reset and enable clock */ + reset_set_enable(PERIPH_ID_UART4, 1); + clock_enable(PERIPH_ID_UART4); /* Enable pllp_out0 to UART */ reg = readl(&clkrst->crc_clk_src_uartd); @@ -137,9 +125,7 @@ static void clock_init_uart(void) udelay(2); /* De-assert reset to UART */ - reg = readl(&clkrst->crc_rst_dev_u); - reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_u); + reset_set_enable(PERIPH_ID_UART4, 0); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -183,16 +169,8 @@ static void clock_init_mmc(void) u32 reg; /* Do the SDMMC resets/clock enables */ - - /* Assert Reset to SDMMC4 */ - reg = readl(&clkrst->crc_rst_dev_l); - reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_l); - - /* Enable clk to SDMMC4 */ - reg = readl(&clkrst->crc_clk_out_enb_l); - reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_l); + reset_set_enable(PERIPH_ID_SDMMC4, 1); + clock_enable(PERIPH_ID_SDMMC4); /* Enable pllp_out0 to SDMMC4 */ reg = readl(&clkrst->crc_clk_src_sdmmc4); @@ -206,20 +184,10 @@ static void clock_init_mmc(void) */ udelay(2); - /* De-assert reset to SDMMC4 */ - reg = readl(&clkrst->crc_rst_dev_l); - reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_l); + reset_set_enable(PERIPH_ID_SDMMC4, 1); - /* Assert Reset to SDMMC3 */ - reg = readl(&clkrst->crc_rst_dev_u); - reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_u); - - /* Enable clk to SDMMC3 */ - reg = readl(&clkrst->crc_clk_out_enb_u); - reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_u); + reset_set_enable(PERIPH_ID_SDMMC3, 1); + clock_enable(PERIPH_ID_SDMMC3); /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */ reg = readl(&clkrst->crc_clk_src_sdmmc3); @@ -230,10 +198,7 @@ static void clock_init_mmc(void) /* wait for 2us */ udelay(2); - /* De-assert reset to SDMMC3 */ - reg = readl(&clkrst->crc_rst_dev_u); - reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_u); + reset_set_enable(PERIPH_ID_SDMMC3, 0); } /* From 858bd095e1583f86af93ac1ae8f9e28aebbd0aa5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 30 Aug 2011 06:23:14 +0000 Subject: [PATCH 078/145] Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/Makefile | 2 +- arch/arm/cpu/armv7/tegra2/pinmux.c | 52 +++++++ arch/arm/include/asm/arch-tegra2/pinmux.h | 161 ++++++++++++++++++++-- board/nvidia/common/board.c | 30 ++-- 4 files changed, 210 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/pinmux.c diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index b35764c321..f673f036f9 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o sys_info.o timer.o +COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/pinmux.c b/arch/arm/cpu/armv7/tegra2/pinmux.c new file mode 100644 index 0000000000..5594ab80f6 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/pinmux.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 pin multiplexing functions */ + +#include +#include +#include +#include + + +void pinmux_set_tristate(enum pmux_pin pin, int enable) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)]; + u32 reg; + + reg = readl(tri); + if (enable) + reg |= TRISTATE_MASK(pin); + else + reg &= ~TRISTATE_MASK(pin); + writel(reg, tri); +} + +void pinmux_tristate_enable(enum pmux_pin pin) +{ + pinmux_set_tristate(pin, 1); +} + +void pinmux_tristate_disable(enum pmux_pin pin) +{ + pinmux_set_tristate(pin, 0); +} diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index cce936ddc8..b8a4753c81 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -24,6 +24,142 @@ #ifndef _PINMUX_H_ #define _PINMUX_H_ +/* Pins which we can set to tristate or normal */ +enum pmux_pin { + /* APB_MISC_PP_TRISTATE_REG_A_0 */ + PIN_ATA, + PIN_ATB, + PIN_ATC, + PIN_ATD, + PIN_CDEV1, + PIN_CDEV2, + PIN_CSUS, + PIN_DAP1, + + PIN_DAP2, + PIN_DAP3, + PIN_DAP4, + PIN_DTA, + PIN_DTB, + PIN_DTC, + PIN_DTD, + PIN_DTE, + + PIN_GPU, + PIN_GPV, + PIN_I2CP, + PIN_IRTX, + PIN_IRRX, + PIN_KBCB, + PIN_KBCA, + PIN_PMC, + + PIN_PTA, + PIN_RM, + PIN_KBCE, + PIN_KBCF, + PIN_GMA, + PIN_GMC, + PIN_SDMMC1, + PIN_OWC, + + /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ + PIN_GME, + PIN_SDC, + PIN_SDD, + PIN_RESERVED0, + PIN_SLXA, + PIN_SLXC, + PIN_SLXD, + PIN_SLXK, + + PIN_SPDI, + PIN_SPDO, + PIN_SPIA, + PIN_SPIB, + PIN_SPIC, + PIN_SPID, + PIN_SPIE, + PIN_SPIF, + + PIN_SPIG, + PIN_SPIH, + PIN_UAA, + PIN_UAB, + PIN_UAC, + PIN_UAD, + PIN_UCA, + PIN_UCB, + + PIN_RESERVED1, + PIN_ATE, + PIN_KBCC, + PIN_RESERVED2, + PIN_RESERVED3, + PIN_GMB, + PIN_GMD, + PIN_DDC, + + /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ + PIN_LD0, + PIN_LD1, + PIN_LD2, + PIN_LD3, + PIN_LD4, + PIN_LD5, + PIN_LD6, + PIN_LD7, + + PIN_LD8, + PIN_LD9, + PIN_LD10, + PIN_LD11, + PIN_LD12, + PIN_LD13, + PIN_LD14, + PIN_LD15, + + PIN_LD16, + PIN_LD17, + PIN_LHP0, + PIN_LHP1, + PIN_LHP2, + PIN_LVP0, + PIN_LVP1, + PIN_HDINT, + + PIN_LM0, + PIN_LM1, + PIN_LVS, + PIN_LSC0, + PIN_LSC1, + PIN_LSCK, + PIN_LDC, + PIN_LCSN, + + /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ + PIN_LSPI, + PIN_LSDA, + PIN_LSDI, + PIN_LPW0, + PIN_LPW1, + PIN_LPW2, + PIN_LDI, + PIN_LHS, + + PIN_LPP, + PIN_RESERVED4, + PIN_KBCD, + PIN_GPU7, + PIN_DTF, + PIN_UDA, + PIN_CRTP, + PIN_SDB, +}; + + +#define TEGRA_TRISTATE_REGS 4 + /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ struct pmux_tri_ctlr { uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ @@ -31,10 +167,7 @@ struct pmux_tri_ctlr { uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */ - uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */ - uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */ - uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */ + uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ @@ -48,14 +181,16 @@ struct pmux_tri_ctlr { uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */ }; -#define Z_GMC (1 << 29) -#define Z_IRRX (1 << 20) -#define Z_IRTX (1 << 19) -#define Z_GMA (1 << 28) -#define Z_GME (1 << 0) -#define Z_ATB (1 << 1) -#define Z_SDB (1 << 15) -#define Z_SDC (1 << 1) -#define Z_SDD (1 << 2) +/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */ +#define TRISTATE_REG(id) ((id) >> 5) + +/* Mask value for a tristate (within TRISTATE_REG(id)) */ +#define TRISTATE_MASK(id) (1 << ((id) & 0x1f)) + +/* Set a pin to tristate */ +void pinmux_tristate_enable(enum pmux_pin pin); + +/* Set a pin to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pin pin); #endif /* PINMUX_H */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 945141e7d3..799dd3a629 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -143,19 +143,15 @@ static void pin_mux_uart(void) reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */ writel(reg, &pmt->pmt_ctl_c); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */ - reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */ - writel(reg, &pmt->pmt_tri_a); + pinmux_tristate_disable(PIN_IRRX); + pinmux_tristate_disable(PIN_IRTX); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) reg = readl(&pmt->pmt_ctl_b); reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */ writel(reg, &pmt->pmt_ctl_b); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_GMC; /* Z_GMC = normal (0) */ - writel(reg, &pmt->pmt_tri_a); + pinmux_tristate_disable(PIN_GMC); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -222,13 +218,9 @@ static void pin_mux_mmc(void) reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ writel(reg, &pmt->pmt_ctl_d); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_ATB; /* Z_ATB = normal (0) */ - reg &= ~Z_GMA; /* Z_GMA = normal (0) */ - writel(reg, &pmt->pmt_tri_a); - reg = readl(&pmt->pmt_tri_b); - reg &= ~Z_GME; /* Z_GME = normal (0) */ - writel(reg, &pmt->pmt_tri_b); + pinmux_tristate_disable(PIN_ATB); + pinmux_tristate_disable(PIN_GMA); + pinmux_tristate_disable(PIN_GME); /* SDMMC3 */ /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ @@ -239,13 +231,9 @@ static void pin_mux_mmc(void) reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ writel(reg, &pmt->pmt_ctl_d); - reg = readl(&pmt->pmt_tri_b); - reg &= ~Z_SDC; /* Z_SDC = normal (0) */ - reg &= ~Z_SDD; /* Z_SDD = normal (0) */ - writel(reg, &pmt->pmt_tri_b); - reg = readl(&pmt->pmt_tri_d); - reg &= ~Z_SDB; /* Z_SDB = normal (0) */ - writel(reg, &pmt->pmt_tri_d); + pinmux_tristate_disable(PIN_SDC); + pinmux_tristate_disable(PIN_SDD); + pinmux_tristate_disable(PIN_SDB); } /* From d07dc4993d646a1b1857a987f9145bf0a8c21370 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 30 Aug 2011 06:23:15 +0000 Subject: [PATCH 079/145] Tegra2: Use clock and pinmux functions to simplify code Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/ap20.c | 47 +++++++--------------- arch/arm/include/asm/arch-tegra2/clk_rst.h | 37 ----------------- board/nvidia/common/board.c | 12 +++--- 3 files changed, 20 insertions(+), 76 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index e3832e23f3..dc5f984d6f 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -40,23 +40,21 @@ void init_pllx(void) u32 reg; /* If PLLX is already enabled, just return */ - reg = readl(&pll->pll_base); - if (reg & PLL_ENABLE) + if (readl(&pll->pll_base) & PLL_ENABLE_MASK) return; /* Set PLLX_MISC */ - reg = CPCON; /* CPCON[11:8] = 0001 */ - writel(reg, &pll->pll_misc); + writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc); /* Use 12MHz clock here */ - reg = (PLL_BYPASS | PLL_DIVM_VALUE); - reg |= (1000 << 8); /* DIVN = 0x3E8 */ + reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT); + reg |= 1000 << PLL_DIVN_SHIFT; writel(reg, &pll->pll_base); - reg |= PLL_ENABLE; + reg |= PLL_ENABLE_MASK; writel(reg, &pll->pll_base); - reg &= ~PLL_BYPASS; + reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); } @@ -90,16 +88,11 @@ static void enable_cpu_clock(int enable) * always stop the clock to CPU 1. */ clk = readl(&clkrst->crc_clk_cpu_cmplx); - clk |= CPU1_CLK_STP; - - if (enable) { - /* Unstop the CPU clock */ - clk &= ~CPU0_CLK_STP; - } else { - /* Stop the CPU clock */ - clk |= CPU0_CLK_STP; - } + clk |= 1 << CPU1_CLK_STP_SHIFT; + /* Stop/Unstop the CPU clock */ + clk &= ~CPU0_CLK_STP_MASK; + clk |= !enable << CPU0_CLK_STP_SHIFT; writel(clk, &clkrst->crc_clk_cpu_cmplx); clock_enable(PERIPH_ID_CPU); @@ -177,9 +170,6 @@ static void enable_cpu_power_rail(void) static void reset_A9_cpu(int reset) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - u32 cpu; - /* * NOTE: Regardless of whether the request is to hold the CPU in reset * or take it out of reset, every processor in the CPU complex @@ -188,19 +178,10 @@ static void reset_A9_cpu(int reset) * are multiple processors in the CPU complex. */ - /* Hold CPU 1 in reset */ - cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; - writel(cpu, &clkrst->crc_cpu_cmplx_set); - - if (reset) { - /* Now place CPU0 into reset */ - cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; - writel(cpu, &clkrst->crc_cpu_cmplx_set); - } else { - /* Take CPU0 out of reset */ - cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; - writel(cpu, &clkrst->crc_cpu_cmplx_clr); - } + /* Hold CPU 1 in reset, and CPU 0 if asked */ + reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1); + reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug, + reset); /* Enable/Disable master CPU reset */ reset_set_enable(PERIPH_ID_CPU, reset); diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index a574c5355d..bd9d9ade90 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -140,43 +140,6 @@ struct clk_rst_ctlr { uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ }; -#define PLL_BYPASS (1 << 31) -#define PLL_ENABLE (1 << 30) -#define PLL_BASE_OVRRIDE (1 << 28) -#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */ -#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */ - -#define SWR_UARTD_RST (1 << 1) -#define CLK_ENB_UARTD (1 << 1) -#define SWR_UARTA_RST (1 << 6) -#define CLK_ENB_UARTA (1 << 6) - -#define SWR_CPU_RST (1 << 0) -#define CLK_ENB_CPU (1 << 0) -#define SWR_CSITE_RST (1 << 9) -#define CLK_ENB_CSITE (1 << 9) - -#define SET_CPURESET0 (1 << 0) -#define SET_DERESET0 (1 << 4) -#define SET_DBGRESET0 (1 << 12) - -#define SET_CPURESET1 (1 << 1) -#define SET_DERESET1 (1 << 5) -#define SET_DBGRESET1 (1 << 13) - -#define CLR_CPURESET0 (1 << 0) -#define CLR_DERESET0 (1 << 4) -#define CLR_DBGRESET0 (1 << 12) - -#define CLR_CPURESET1 (1 << 1) -#define CLR_DERESET1 (1 << 5) -#define CLR_DBGRESET1 (1 << 13) - -#define CPU0_CLK_STP (1 << 8) -#define CPU1_CLK_STP (1 << 9) - -#define CPCON (1 << 8) - /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ #define CPU1_CLK_STP_SHIFT 9 diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 799dd3a629..160dac8e1c 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -81,20 +81,20 @@ static void clock_init_uart(void) u32 reg; reg = readl(&pll->pll_base); - if (!(reg & PLL_BASE_OVRRIDE)) { + if (!(reg & PLL_BASE_OVRRIDE_MASK)) { /* Override pllp setup for 216MHz operation. */ - reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE); - reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE); + reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK | + (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT); + reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT; writel(reg, &pll->pll_base); - reg |= PLL_ENABLE; + reg |= PLL_ENABLE_MASK; writel(reg, &pll->pll_base); - reg &= ~PLL_BYPASS; + reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); } - /* Now do the UART reset/clock enable */ #if defined(CONFIG_TEGRA2_ENABLE_UARTA) /* Assert UART reset and enable clock */ reset_set_enable(PERIPH_ID_UART1, 1); From 9f15bc0c1cc1a88ee655ea2dc3dd56caf8e5de79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Mon, 22 Aug 2011 22:34:58 +0000 Subject: [PATCH 080/145] i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c) This patch adds support for software I2C for GONI and Universal C210 reference targets. It adds support for access to GPIOs by number, not as it is present, by bank and offset. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang Cc: Heiko Schocher --- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 13 +++++++ arch/arm/include/asm/arch-s5pc2xx/gpio.h | 29 ++++++++++++++++ drivers/gpio/s5p_gpio.c | 44 ++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 903de9c337..76b901b397 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -134,6 +134,19 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 + +static inline unsigned int s5p_gpio_base(int nr) +{ + return S5PC110_GPIO_BASE; +} + +#define s5pc110_gpio_get_nr(bank, pin) \ + ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ + - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) #endif /* Pin configurations */ diff --git a/arch/arm/include/asm/arch-s5pc2xx/gpio.h b/arch/arm/include/asm/arch-s5pc2xx/gpio.h index 8db5895b86..8be620cae6 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc2xx/gpio.h @@ -88,6 +88,35 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 + +#define s5pc210_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \ + S5PC210_GPIO_PART1_BASE)->bank)) \ + - S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define s5pc210_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \ + S5PC210_GPIO_PART2_BASE)->bank)) \ + - S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX) + +static inline unsigned int s5p_gpio_base(int nr) +{ + if (nr < GPIO_PART1_MAX) + return S5PC210_GPIO_PART1_BASE; + else + return S5PC210_GPIO_PART2_BASE; + + return 0; +} + #endif /* Pin configurations */ diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 2043859906..1edf9a26a2 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -141,3 +141,47 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } + +struct s5p_gpio_bank *s5p_gpio_get_bank(int nr) +{ + int bank = nr / GPIO_PER_BANK; + bank *= sizeof(struct s5p_gpio_bank); + + return (struct s5p_gpio_bank *) (s5p_gpio_base(nr) + bank); +} + +int s5p_gpio_get_pin(int nr) +{ + return nr % GPIO_PER_BANK; +} + +int gpio_request(int gpio, const char *label) +{ + return 0; +} + +int gpio_direction_input(int nr) +{ + s5p_gpio_direction_input(s5p_gpio_get_bank(nr), + s5p_gpio_get_pin(nr)); + return 0; +} + +int gpio_direction_output(int nr, int value) +{ + s5p_gpio_direction_output(s5p_gpio_get_bank(nr), + s5p_gpio_get_pin(nr), value); + return 0; +} + +int gpio_get_value(int nr) +{ + return (int) s5p_gpio_get_value(s5p_gpio_get_bank(nr), + s5p_gpio_get_pin(nr)); +} + +void gpio_set_value(int nr, int value) +{ + s5p_gpio_set_value(s5p_gpio_get_bank(nr), + s5p_gpio_get_pin(nr), value); +} From 85776b02143ef8bbf5cc54e09ff1b4f020be11a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Mon, 22 Aug 2011 22:34:59 +0000 Subject: [PATCH 081/145] i2c:gpio:s5p: Enable I2C GPIO on the GONI target This patch enables the software I2C for GONI reference target. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang Cc: Heiko Schocher --- include/configs/s5p_goni.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index a5aa859c0c..6d0058f8e8 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -220,4 +220,16 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) +#include +/* + * I2C Settings + */ +#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) +#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) + +#define CONFIG_SOFT_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 7 + #endif /* __CONFIG_H */ From b9a1ef219e12c08b2af695dd5355d6352b8ffc08 Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Thu, 18 Aug 2011 22:37:19 +0000 Subject: [PATCH 082/145] ARMV7: Add support for Samsung ORIGEN board Origen board is based upon S5PV310 SoC which is similiar to S5PC210 SoC. Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- MAINTAINERS | 1 + board/samsung/origen/Makefile | 46 +++ board/samsung/origen/lowlevel_init.S | 357 ++++++++++++++++++ board/samsung/origen/mem_setup.S | 421 +++++++++++++++++++++ board/samsung/origen/origen.c | 109 ++++++ board/samsung/origen/origen_setup.h | 546 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/origen.h | 160 ++++++++ 8 files changed, 1641 insertions(+) create mode 100644 board/samsung/origen/Makefile create mode 100644 board/samsung/origen/lowlevel_init.S create mode 100644 board/samsung/origen/mem_setup.S create mode 100644 board/samsung/origen/origen.c create mode 100644 board/samsung/origen/origen_setup.h create mode 100644 include/configs/origen.h diff --git a/MAINTAINERS b/MAINTAINERS index 09fa789a0e..84faea2f25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -707,6 +707,7 @@ Minkyu Kang Chander Kashyap + origen ARM ARMV7 (S5PC210 SoC) SMDKV310 ARM ARMV7 (S5PC210 SoC) Torsten Koschorrek diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile new file mode 100644 index 0000000000..65eff91c91 --- /dev/null +++ b/board/samsung/origen/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2011 Samsung Electronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +SOBJS := mem_setup.o +SOBJS += lowlevel_init.o +COBJS += origen.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S new file mode 100644 index 0000000000..ddca1e21fc --- /dev/null +++ b/board/samsung/origen/lowlevel_init.S @@ -0,0 +1,357 @@ +/* + * Lowlevel setup for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "origen_setup.h" +/* + * Register usages: + * + * r5 has zero always + * r7 has GPIO part1 base 0x11400000 + * r6 has GPIO part2 base 0x11000000 + */ + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + push {lr} + + /* r5 has always zero */ + mov r5, #0 + ldr r7, =S5PC210_GPIO_PART1_BASE + ldr r6, =S5PC210_GPIO_PART2_BASE + + /* check reset status */ + ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET) + ldr r1, [r0] + + /* AFTR wakeup reset */ + ldr r2, =S5P_CHECK_DIDLE + cmp r1, r2 + beq exit_wakeup + + /* LPA wakeup reset */ + ldr r2, =S5P_CHECK_LPA + cmp r1, r2 + beq exit_wakeup + + /* Sleep wakeup reset */ + ldr r2, =S5P_CHECK_SLEEP + cmp r1, r2 + beq wakeup_reset + + /* + * If U-boot is already running in ram, no need to relocate U-Boot. + * Memory controller must be configured before relocating U-Boot + * in ram. + */ + ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ + bic r1, pc, r0 /* pc <- current addr of code */ + /* r1 <- unmasked bits of pc */ + ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ + bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ + cmp r1, r2 /* compare r1, r2 */ + beq 1f /* r0 == r1 then skip sdram init */ + + /* init system clock */ + bl system_clock_init + + /* Memory initialize */ + bl mem_ctrl_asm_init + +1: + /* for UART */ + bl uart_asm_init + bl tzpc_init + pop {pc} + +wakeup_reset: + bl system_clock_init + bl mem_ctrl_asm_init + bl tzpc_init + +exit_wakeup: + /* Load return address and jump to kernel */ + ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET) + + /* r1 = physical address of s5pc210_cpu_resume function */ + ldr r1, [r0] + + /* Jump to kernel*/ + mov pc, r1 + nop + nop + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + push {lr} + ldr r0, =S5PC210_CLOCK_BASE + + /* APLL(1), MPLL(1), CORE(0), HPM(0) */ + ldr r1, =CLK_SRC_CPU_VAL + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x10000 +2: subs r1, r1, #1 + bne 2b + + ldr r1, =CLK_SRC_TOP0_VAL + ldr r2, =CLK_SRC_TOP0_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_TOP1_VAL + ldr r2, =CLK_SRC_TOP1_OFFSET + str r1, [r0, r2] + + /* DMC */ + ldr r1, =CLK_SRC_DMC_VAL + ldr r2, =CLK_SRC_DMC_OFFSET + str r1, [r0, r2] + + /*CLK_SRC_LEFTBUS */ + ldr r1, =CLK_SRC_LEFTBUS_VAL + ldr r2, =CLK_SRC_LEFTBUS_OFFSET + str r1, [r0, r2] + + /*CLK_SRC_RIGHTBUS */ + ldr r1, =CLK_SRC_RIGHTBUS_VAL + ldr r2, =CLK_SRC_RIGHTBUS_OFFSET + str r1, [r0, r2] + + /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ + ldr r1, =CLK_SRC_FSYS_VAL + ldr r2, =CLK_SRC_FSYS_OFFSET + str r1, [r0, r2] + + /* UART[0:4] */ + ldr r1, =CLK_SRC_PERIL0_VAL + ldr r2, =CLK_SRC_PERIL0_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x10000 +3: subs r1, r1, #1 + bne 3b + + /* CLK_DIV_CPU0 */ + ldr r1, =CLK_DIV_CPU0_VAL + ldr r2, =CLK_DIV_CPU0_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_CPU1 */ + ldr r1, =CLK_DIV_CPU1_VAL + ldr r2, =CLK_DIV_CPU1_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_DMC0 */ + ldr r1, =CLK_DIV_DMC0_VAL + ldr r2, =CLK_DIV_DMC0_OFFSET + str r1, [r0, r2] + + /*CLK_DIV_DMC1 */ + ldr r1, =CLK_DIV_DMC1_VAL + ldr r2, =CLK_DIV_DMC1_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_LEFTBUS */ + ldr r1, =CLK_DIV_LEFTBUS_VAL + ldr r2, =CLK_DIV_LEFTBUS_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_RIGHTBUS */ + ldr r1, =CLK_DIV_RIGHTBUS_VAL + ldr r2, =CLK_DIV_RIGHTBUS_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_TOP */ + ldr r1, =CLK_DIV_TOP_VAL + ldr r2, =CLK_DIV_TOP_OFFSET + str r1, [r0, r2] + + /* MMC[0:1] */ + ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS1_OFFSET + str r1, [r0, r2] + + /* MMC[2:3] */ + ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS2_OFFSET + str r1, [r0, r2] + + /* MMC4 */ + ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS3_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_PERIL0: UART Clock Divisors */ + ldr r1, =CLK_DIV_PERIL0_VAL + ldr r2, =CLK_DIV_PERIL0_OFFSET + str r1, [r0, r2] + + /* Set PLL locktime */ + ldr r1, =PLL_LOCKTIME + ldr r2, =APLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =MPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =EPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =VPLL_LOCK_OFFSET + str r1, [r0, r2] + + /* APLL_CON1 */ + ldr r1, =APLL_CON1_VAL + ldr r2, =APLL_CON1_OFFSET + str r1, [r0, r2] + + /* APLL_CON0 */ + ldr r1, =APLL_CON0_VAL + ldr r2, =APLL_CON0_OFFSET + str r1, [r0, r2] + + /* MPLL_CON1 */ + ldr r1, =MPLL_CON1_VAL + ldr r2, =MPLL_CON1_OFFSET + str r1, [r0, r2] + + /* MPLL_CON0 */ + ldr r1, =MPLL_CON0_VAL + ldr r2, =MPLL_CON0_OFFSET + str r1, [r0, r2] + + /* EPLL */ + ldr r1, =EPLL_CON1_VAL + ldr r2, =EPLL_CON1_OFFSET + str r1, [r0, r2] + + /* EPLL_CON0 */ + ldr r1, =EPLL_CON0_VAL + ldr r2, =EPLL_CON0_OFFSET + str r1, [r0, r2] + + /* VPLL_CON1 */ + ldr r1, =VPLL_CON1_VAL + ldr r2, =VPLL_CON1_OFFSET + str r1, [r0, r2] + + /* VPLL_CON0 */ + ldr r1, =VPLL_CON0_VAL + ldr r2, =VPLL_CON0_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x30000 +4: subs r1, r1, #1 + bne 4b + + pop {pc} +/* + * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. + * void uart_asm_init(void) + */ + .globl uart_asm_init +uart_asm_init: + + /* setup UART0-UART3 GPIOs (part1) */ + mov r0, r7 + ldr r1, =S5PC210_GPIO_A0_CON_VAL + str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET] + ldr r1, =S5PC210_GPIO_A1_CON_VAL + str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET] + + ldr r0, =S5PC210_UART_BASE + add r0, r0, #S5PC210_DEFAULT_UART_OFFSET + + ldr r1, =ULCON_VAL + str r1, [r0, #ULCON_OFFSET] + ldr r1, =UCON_VAL + str r1, [r0, #UCON_OFFSET] + ldr r1, =UFCON_VAL + str r1, [r0, #UFCON_OFFSET] + ldr r1, =UBRDIV_VAL + str r1, [r0, #UBRDIV_OFFSET] + ldr r1, =UFRACVAL_VAL + str r1, [r0, #UFRACVAL_OFFSET] + mov pc, lr + nop + nop + nop + +/* Setting TZPC[TrustZone Protection Controller] */ +tzpc_init: + ldr r0, =TZPC0_BASE + mov r1, #R0SIZE + str r1, [r0] + mov r1, #DECPROTXSET + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + mov pc, lr diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S new file mode 100644 index 0000000000..a798848ba1 --- /dev/null +++ b/board/samsung/origen/mem_setup.S @@ -0,0 +1,421 @@ +/* + * Memory setup for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "origen_setup.h" +#define SET_MIU + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + /* + * Async bridge configuration at CPU_core: + * 1: half_sync + * 0: full_sync + */ + ldr r0, =ASYNC_CONFIG + mov r1, #1 + str r1, [r0] + +#ifdef SET_MIU + ldr r0, =S5PC210_MIU_BASE + /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */ + ldr r1, =0x20001507 + str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET] + + /* Update MIU Configuration */ + ldr r1, =0x00000001 + str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET] +#endif + /* DREX0 */ + ldr r0, =S5PC210_DMC0_BASE + + /* + * DLL Parameter Setting: + * Termination: Enable R/W + * Phase Delay for DQS Cleaning: 180' Shift + */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* + * ZQ Calibration + * Termination: Disable + * Auto Calibration Start: Enable + */ + ldr r1, =0xE3855703 + str r1, [r0, #DMC_PHYZQCONTROL] + + /* Wait ?us*/ + mov r2, #0x100000 +1: subs r2, r2, #1 + bne 1b + + /* + * Update DLL Information: + * Force DLL Resyncronization + */ + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + + /* Reset Force DLL Resyncronization */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Enable Differential DQS, DLL Off*/ + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + /* Activate PHY DLL: DLL On */ + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + /* Set DLL Parameters */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* DLL Start */ + ldr r1, =0x7110100B + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + /* Set Clock Ratio of Bus clock to Memory Clock */ + ldr r1, =0x0FFF301a + str r1, [r0, #DMC_CONCONTROL] + + /* + * Memor Burst length: 8 + * Number of chips: 2 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 1 Cycle + */ + ldr r1, =0x00312640 + str r1, [r0, #DMC_MEMCONTROL] + + /* + * Memory Configuration Chip 0 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x20e01323 + str r1, [r0, #DMC_MEMCONFIG0] + + /* + * Memory Configuration Chip 1 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x40e01323 + str r1, [r0, #DMC_MEMCONFIG1] + + /* Config Precharge Policy */ + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + /* + * TimingAref, TimingRow, TimingData, TimingPower Setting: + * Values as per Memory AC Parameters + */ + ldr r1, =0x000000BB + str r1, [r0, #DMC_TIMINGAREF] + ldr r1, =0x4046654f + str r1, [r0, #DMC_TIMINGROW] + ldr r1, =0x46400506 + str r1, [r0, #DMC_TIMINGDATA] + ldr r1, =0x52000A3C + str r1, [r0, #DMC_TIMINGPOWER] + + /* Chip0: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +2: subs r2, r2, #1 + bne 2b + + /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00020000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00030000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00010002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +3: subs r2, r2, #1 + bne 3b + + /* Chip0: ZQINIT */ + ldr r1, =0x0a000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +4: subs r2, r2, #1 + bne 4b + + /* Chip1: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +5: subs r2, r2, #1 + bne 5b + + /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00120000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00130000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00110002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00100328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +6: subs r2, r2, #1 + bne 6b + + /* Chip1: ZQINIT */ + ldr r1, =0x0a100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +7: subs r2, r2, #1 + bne 7b + + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Wait ?us*/ + mov r2, #0x100000 +8: subs r2, r2, #1 + bne 8b + + /* DREX1 */ + ldr r0, =S5PC210_DMC1_BASE @0x10410000 + + /* + * DLL Parameter Setting: + * Termination: Enable R/W + * Phase Delay for DQS Cleaning: 180' Shift + */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* + * ZQ Calibration: + * Termination: Disable + * Auto Calibration Start: Enable + */ + ldr r1, =0xE3855703 + str r1, [r0, #DMC_PHYZQCONTROL] + + /* Wait ?us*/ + mov r2, #0x100000 +1: subs r2, r2, #1 + bne 1b + + /* + * Update DLL Information: + * Force DLL Resyncronization + */ + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + + /* Reset Force DLL Resyncronization */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Enable Differential DQS, DLL Off*/ + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + /* Activate PHY DLL: DLL On */ + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + /* Set DLL Parameters */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* DLL Start */ + ldr r1, =0x7110100B + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + /* Set Clock Ratio of Bus clock to Memory Clock */ + ldr r1, =0x0FFF301a + str r1, [r0, #DMC_CONCONTROL] + + /* + * Memor Burst length: 8 + * Number of chips: 2 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 1 Cycle + */ + ldr r1, =0x00312640 + str r1, [r0, #DMC_MEMCONTROL] + + /* + * Memory Configuration Chip 0 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x20e01323 + str r1, [r0, #DMC_MEMCONFIG0] + + /* + * Memory Configuration Chip 1 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x40e01323 + str r1, [r0, #DMC_MEMCONFIG1] + + /* Config Precharge Policy */ + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + /* + * TimingAref, TimingRow, TimingData, TimingPower Setting: + * Values as per Memory AC Parameters + */ + ldr r1, =0x000000BB + str r1, [r0, #DMC_TIMINGAREF] + ldr r1, =0x4046654f + str r1, [r0, #DMC_TIMINGROW] + ldr r1, =0x46400506 + str r1, [r0, #DMC_TIMINGDATA] + ldr r1, =0x52000A3C + str r1, [r0, #DMC_TIMINGPOWER] + + /* Chip0: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +2: subs r2, r2, #1 + bne 2b + + /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00020000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00030000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00010002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +3: subs r2, r2, #1 + bne 3b + + /* Chip 0: ZQINIT */ + ldr r1, =0x0a000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +4: subs r2, r2, #1 + bne 4b + + /* Chip1: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +5: subs r2, r2, #1 + bne 5b + + /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00120000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00130000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00110002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00100328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +6: subs r2, r2, #1 + bne 6b + + /* Chip1: ZQINIT */ + ldr r1, =0x0a100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +7: subs r2, r2, #1 + bne 7b + + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Wait ?us*/ + mov r2, #0x100000 +8: subs r2, r2, #1 + bne 8b + + /* turn on DREX0, DREX1 */ + ldr r0, =S5PC210_DMC0_BASE + ldr r1, =0x0FFF303a + str r1, [r0, #DMC_CONCONTROL] + + ldr r0, =S5PC210_DMC1_BASE + ldr r1, =0x0FFF303a + str r1, [r0, #DMC_CONCONTROL] + + mov pc, lr diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c new file mode 100644 index 0000000000..8882646eca --- /dev/null +++ b/board/samsung/origen/origen.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +struct s5pc210_gpio_part1 *gpio1; +struct s5pc210_gpio_part2 *gpio2; + +int board_init(void) +{ + gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE; + gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE; + + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ + PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ + PHYS_SDRAM_2_SIZE); + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ + PHYS_SDRAM_3_SIZE); + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ + PHYS_SDRAM_4_SIZE); +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: ORIGEN\n"); + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int i, err; + + /* + * MMC2 SD card GPIO: + * + * GPK2[0] SD_2_CLK(2) + * GPK2[1] SD_2_CMD(2) + * GPK2[2] SD_2_CDn + * GPK2[3:6] SD_2_DATA[0:3](2) + */ + for (i = 0; i < 7; i++) { + /* GPK2[0:6] special function 2 */ + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + + /* GPK2[0:6] drv 4x */ + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + + /* GPK2[0:1] pull disable */ + if (i == 0 || i == 1) { + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + continue; + } + + /* GPK2[2:6] pull up */ + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + } + + err = s5p_mmc_init(2, 4); + return err; +} +#endif diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h new file mode 100644 index 0000000000..63d85d8a8c --- /dev/null +++ b/board/samsung/origen/origen_setup.h @@ -0,0 +1,546 @@ +/* + * Machine Specific Values for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ORIGEN_SETUP_H +#define _ORIGEN_SETUP_H + +#include +#include +#include + +/* Offsets of clock registers (sources and dividers) */ +#define CLK_SRC_CPU_OFFSET 0x14200 +#define CLK_DIV_CPU0_OFFSET 0x14500 +#define CLK_DIV_CPU1_OFFSET 0x14504 + +#define CLK_SRC_DMC_OFFSET 0x10200 +#define CLK_DIV_DMC0_OFFSET 0x10500 +#define CLK_DIV_DMC1_OFFSET 0x10504 + +#define CLK_SRC_TOP0_OFFSET 0xC210 +#define CLK_SRC_TOP1_OFFSET 0xC214 +#define CLK_DIV_TOP_OFFSET 0xC510 + +#define CLK_SRC_LEFTBUS_OFFSET 0x4200 +#define CLK_DIV_LEFTBUS_OFFSET 0x4500 + +#define CLK_SRC_RIGHTBUS_OFFSET 0x8200 +#define CLK_DIV_RIGHTBUS_OFFSET 0x8500 + +#define CLK_SRC_FSYS_OFFSET 0xC240 +#define CLK_DIV_FSYS1_OFFSET 0xC544 +#define CLK_DIV_FSYS2_OFFSET 0xC548 +#define CLK_DIV_FSYS3_OFFSET 0xC54C + +#define CLK_SRC_PERIL0_OFFSET 0xC250 +#define CLK_DIV_PERIL0_OFFSET 0xC550 + +#define APLL_LOCK_OFFSET 0x14000 +#define MPLL_LOCK_OFFSET 0x14008 +#define APLL_CON0_OFFSET 0x14100 +#define APLL_CON1_OFFSET 0x14104 +#define MPLL_CON0_OFFSET 0x14108 +#define MPLL_CON1_OFFSET 0x1410C + +#define EPLL_LOCK_OFFSET 0xC010 +#define VPLL_LOCK_OFFSET 0xC020 +#define EPLL_CON0_OFFSET 0xC110 +#define EPLL_CON1_OFFSET 0xC114 +#define VPLL_CON0_OFFSET 0xC120 +#define VPLL_CON1_OFFSET 0xC124 + +/* DMC: DRAM Controllor Register offsets */ +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PHYCONTROL1 0x1C +#define DMC_PHYCONTROL2 0x20 +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYZQCONTROL 0x44 + +/* Bus Configuration Register Address */ +#define ASYNC_CONFIG 0x10010350 + +/* MIU Config Register Offsets*/ +#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 +#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 + +/* GPIO Offsets for UART: GPIO Contol Register */ +#define S5PC210_GPIO_A0_CON_OFFSET 0x00 +#define S5PC210_GPIO_A1_CON_OFFSET 0x20 + +/* UART Register offsets */ +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UBRDIV_OFFSET 0x28 +#define UFRACVAL_OFFSET 0x2C + +/* TZPC : Register Offsets */ +#define TZPC0_BASE 0x10110000 +#define TZPC1_BASE 0x10120000 +#define TZPC2_BASE 0x10130000 +#define TZPC3_BASE 0x10140000 +#define TZPC4_BASE 0x10150000 +#define TZPC5_BASE 0x10160000 + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* CLK_SRC_CPU */ +#define MUX_HPM_SEL_MOUTAPLL 0x0 +#define MUX_HPM_SEL_SCLKMPLL 0x1 +#define MUX_CORE_SEL_MOUTAPLL 0x0 +#define MUX_CORE_SEL_SCLKMPLL 0x1 +#define MUX_MPLL_SEL_FILPLL 0x0 +#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 +#define MUX_APLL_SEL_FILPLL 0x0 +#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL << 16) \ + | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ + | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x0 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define PERIPH_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define COREM0_RATIO 0x3 +#define CORE_RATIO 0x0 +#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (COREM1_RATIO << 8) \ + | (COREM0_RATIO << 4) \ + | (CORE_RATIO << 0)) + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x3 +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL_XXTI 0x0 +#define MUX_PWI_SEL_XUSBXTI 0x1 +#define MUX_PWI_SEL_SCLK_HDMI24M 0x2 +#define MUX_PWI_SEL_SCLK_USBPHY0 0x3 +#define MUX_PWI_SEL_SCLK_USBPHY1 0x4 +#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5 +#define MUX_PWI_SEL_SCLKMPLL 0x6 +#define MUX_PWI_SEL_SCLKEPLL 0x7 +#define MUX_PWI_SEL_SCLKVPLL 0x8 +#define MUX_DPHY_SEL_SCLKMPLL 0x0 +#define MUX_DPHY_SEL_SCLKAPLL 0x1 +#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0 +#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \ + | (MUX_DPHY_SEL_SCLKMPLL << 8) \ + | (MUX_DMC_BUS_SEL_SCLKMPLL << 4)) + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x1 +#define COPY2_RATIO 0x3 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#define DMC_RATIO 0x1 +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + | (COPY2_RATIO << 24) \ + | (DMCP_RATIO << 20) \ + | (DMCD_RATIO << 16) \ + | (DMC_RATIO << 12) \ + | (DPHY_RATIO << 8) \ + | (ACP_PCLK_RATIO << 4) \ + | (ACP_RATIO << 0)) + +/* CLK_DIV_DMC1 */ +#define DPM_RATIO 0x1 +#define DVSEM_RATIO 0x1 +#define PWI_RATIO 0x1 +#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ + | (DVSEM_RATIO << 16) \ + | (PWI_RATIO << 8)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL_ACLK_133 0x0 +#define MUX_ONENAND_SEL_ACLK_160 0x1 +#define MUX_ACLK_133_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_133_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_160_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_160_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_100_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_100_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_200_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_200_SEL_SCLKAPLL 0x1 +#define MUX_VPLL_SEL_FINPLL 0x0 +#define MUX_VPLL_SEL_FOUTVPLL 0x1 +#define MUX_EPLL_SEL_FINPLL 0x0 +#define MUX_EPLL_SEL_FOUTEPLL 0x1 +#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 +#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \ + | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ + | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ + | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ + | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ + | (MUX_VPLL_SEL_FINPLL << 8) \ + | (MUX_EPLL_SEL_FINPLL << 4)\ + | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL_FINPLL 0x0 +#define VPLLSRC_SEL_SCLKHDMI24M 0x1 +#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL) + +/* CLK_DIV_TOP */ +#define ONENAND_RATIO 0x0 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x3 +#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ + | (ACLK_133_RATIO << 12)\ + | (ACLK_160_RATIO << 8) \ + | (ACLK_100_RATIO << 4) \ + | (ACLK_200_RATIO << 0)) + +/* CLK_SRC_LEFTBUS */ +#define MUX_GDL_SEL_SCLKMPLL 0x0 +#define MUX_GDL_SEL_SCLKAPLL 0x1 +#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL) + +/* CLK_DIV_LEFTBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define MUX_GDR_SEL_SCLKMPLL 0x0 +#define MUX_GDR_SEL_SCLKAPLL 0x1 +#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) + +/* CLK_SRS_FSYS: 6 = SCLKMPLL */ +#define SATA_SEL_SCLKMPLL 0 +#define SATA_SEL_SCLKAPLL 1 + +#define MMC_SEL_XXTI 0 +#define MMC_SEL_XUSBXTI 1 +#define MMC_SEL_SCLK_HDMI24M 2 +#define MMC_SEL_SCLK_USBPHY0 3 +#define MMC_SEL_SCLK_USBPHY1 4 +#define MMC_SEL_SCLK_HDMIPHY 5 +#define MMC_SEL_SCLKMPLL 6 +#define MMC_SEL_SCLKEPLL 7 +#define MMC_SEL_SCLKVPLL 8 + +#define MMCC0_SEL MMC_SEL_SCLKMPLL +#define MMCC1_SEL MMC_SEL_SCLKMPLL +#define MMCC2_SEL MMC_SEL_SCLKMPLL +#define MMCC3_SEL MMC_SEL_SCLKMPLL +#define MMCC4_SEL MMC_SEL_SCLKMPLL +#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ + | (MMCC4_SEL << 16) \ + | (MMCC3_SEL << 12) \ + | (MMCC2_SEL << 8) \ + | (MMCC1_SEL << 4) \ + | (MMCC0_SEL << 0)) + +/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO 0xF +#define MMC0_PRE_RATIO 0x0 +#define MMC1_RATIO 0xF +#define MMC1_PRE_RATIO 0x0 +#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ + | (MMC1_RATIO << 16) \ + | (MMC0_PRE_RATIO << 8) \ + | (MMC0_RATIO << 0)) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO 0xF +#define MMC2_PRE_RATIO 0x0 +#define MMC3_RATIO 0xF +#define MMC3_PRE_RATIO 0x0 +#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ + | (MMC3_RATIO << 16) \ + | (MMC2_PRE_RATIO << 8) \ + | (MMC2_RATIO << 0)) + +/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO 0xF +#define MMC4_PRE_RATIO 0x0 +#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ + | (MMC4_RATIO << 0)) + +/* CLK_SRC_PERIL0 */ +#define UART_SEL_XXTI 0 +#define UART_SEL_XUSBXTI 1 +#define UART_SEL_SCLK_HDMI24M 2 +#define UART_SEL_SCLK_USBPHY0 3 +#define UART_SEL_SCLK_USBPHY1 4 +#define UART_SEL_SCLK_HDMIPHY 5 +#define UART_SEL_SCLKMPLL 6 +#define UART_SEL_SCLKEPLL 7 +#define UART_SEL_SCLKVPLL 8 + +#define UART0_SEL UART_SEL_SCLKMPLL +#define UART1_SEL UART_SEL_SCLKMPLL +#define UART2_SEL UART_SEL_SCLKMPLL +#define UART3_SEL UART_SEL_SCLKMPLL +#define UART4_SEL UART_SEL_SCLKMPLL +#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL << 0)) + +/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */ +/* CLK_DIV_PERIL0 */ +#define UART0_RATIO 7 +#define UART1_RATIO 7 +#define UART2_RATIO 7 +#define UART3_RATIO 7 +#define UART4_RATIO 7 +#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ + | (UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO << 0)) + +/* Required period to generate a stable clock output */ +/* PLL_LOCK_TIME */ +#define PLL_LOCKTIME 0x1C20 + +/* PLL Values */ +#define DISABLE 0 +#define ENABLE 1 +#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ + | (mdiv << 16) \ + | (pdiv << 8) \ + | (sdiv << 0)) + +/* APLL_CON0 */ +#define APLL_MDIV 0xFA +#define APLL_PDIV 0x6 +#define APLL_SDIV 0x1 +#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) + +/* APLL_CON1 */ +#define APLL_AFC_ENB 0x1 +#define APLL_AFC 0xC +#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) + +/* MPLL_CON0 */ +#define MPLL_MDIV 0xC8 +#define MPLL_PDIV 0x6 +#define MPLL_SDIV 0x1 +#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) + +/* MPLL_CON1 */ +#define MPLL_AFC_ENB 0x0 +#define MPLL_AFC 0x1C +#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) + +/* EPLL_CON0 */ +#define EPLL_MDIV 0x30 +#define EPLL_PDIV 0x3 +#define EPLL_SDIV 0x2 +#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) + +/* EPLL_CON1 */ +#define EPLL_K 0x0 +#define EPLL_CON1_VAL (EPLL_K >> 0) + +/* VPLL_CON0 */ +#define VPLL_MDIV 0x35 +#define VPLL_PDIV 0x3 +#define VPLL_SDIV 0x2 +#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) + +/* VPLL_CON1 */ +#define VPLL_SSCG_EN DISABLE +#define VPLL_SEL_PF_DN_SPREAD 0x0 +#define VPLL_MRR 0x11 +#define VPLL_MFR 0x0 +#define VPLL_K 0x400 +#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ + | (VPLL_SEL_PF_DN_SPREAD << 29) \ + | (VPLL_MRR << 24) \ + | (VPLL_MFR << 16) \ + | (VPLL_K << 0)) +/* + * UART GPIO_A0/GPIO_A1 Control Register Value + * 0x2: UART Function + */ +#define S5PC210_GPIO_A0_CON_VAL 0x22222222 +#define S5PC210_GPIO_A1_CON_VAL 0x222222 + +/* ULCON: UART Line Control Value 8N1 */ +#define WORD_LEN_5_BIT 0x00 +#define WORD_LEN_6_BIT 0x01 +#define WORD_LEN_7_BIT 0x02 +#define WORD_LEN_8_BIT 0x03 + +#define STOP_BIT_1 0x00 +#define STOP_BIT_2 0x01 + +#define NO_PARITY 0x00 +#define ODD_PARITY 0x4 +#define EVEN_PARITY 0x5 +#define FORCED_PARITY_CHECK_AS_1 0x6 +#define FORCED_PARITY_CHECK_AS_0 0x7 + +#define INFRAMODE_NORMAL 0x00 +#define INFRAMODE_INFRARED 0x01 + +#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \ + | (NO_PARITY << 3) \ + | (STOP_BIT_1 << 2) \ + | (WORD_LEN_8_BIT << 0)) + +/* + * UCON: UART Control Value + * Tx_interrupt Type: Level + * Rx_interrupt Type: Level + * Rx Timeout Enabled: Yes + * Rx-Error Atatus_Int Enable: Yes + * Loop_Back: No + * Break Signal: No + * Transmit mode : Interrupt request/polling + * Receive mode : Interrupt request/polling + */ +#define TX_PULSE_INTERRUPT 0 +#define TX_LEVEL_INTERRUPT 1 +#define RX_PULSE_INTERRUPT 0 +#define RX_LEVEL_INTERRUPT 1 + +#define RX_TIME_OUT ENABLE +#define RX_ERROR_STATE_INT_ENB ENABLE +#define LOOP_BACK DISABLE +#define BREAK_SIGNAL DISABLE + +#define TX_MODE_DISABLED 0X00 +#define TX_MODE_IRQ_OR_POLL 0X01 +#define TX_MODE_DMA 0X02 + +#define RX_MODE_DISABLED 0X00 +#define RX_MODE_IRQ_OR_POLL 0X01 +#define RX_MODE_DMA 0X02 + +#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \ + | (RX_LEVEL_INTERRUPT << 8) \ + | (RX_TIME_OUT << 7) \ + | (RX_ERROR_STATE_INT_ENB << 6) \ + | (LOOP_BACK << 5) \ + | (BREAK_SIGNAL << 4) \ + | (TX_MODE_IRQ_OR_POLL << 2) \ + | (RX_MODE_IRQ_OR_POLL << 0)) + +/* + * UFCON: UART FIFO Control Value + * Tx FIFO Trigger LEVEL: 2 Bytes (001) + * Rx FIFO Trigger LEVEL: 2 Bytes (001) + * Tx Fifo Reset: No + * Rx Fifo Reset: No + * FIFO Enable: Yes + */ +#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00 +#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1 +#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2 +#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3 +#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4 +#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5 +#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6 +#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7 + +#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0 +#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1 +#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2 +#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3 +#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4 +#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5 +#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6 +#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7 + +#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES +#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES +#define TX_FIFO_RESET DISABLE +#define RX_FIFO_RESET DISABLE +#define FIFO_ENABLE ENABLE +#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \ + | (RX_FIFO_TRIGGER_LEVEL << 4) \ + | (TX_FIFO_RESET << 2) \ + | (RX_FIFO_RESET << 1) \ + | (FIFO_ENABLE << 0)) +/* + * Baud Rate Division Value + * 115200 BAUD: + * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1) + * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1) + */ +#define UBRDIV_VAL 0x35 + +/* + * Fractional Part of Baud Rate Divisor: + * 115200 BAUD: + * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10) + * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10) + */ +#define UFRACVAL_VAL 0x4 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF +#endif diff --git a/boards.cfg b/boards.cfg index 12c82df77b..734ea8e0c0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -186,6 +186,7 @@ omap4_panda arm armv7 panda ti omap4_sdp4430 arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsung s5pc1xx smdkc100 arm armv7 smdkc100 samsung s5pc1xx +origen arm armv7 origen samsung s5pc2xx s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx smdkv310 arm armv7 smdkv310 samsung s5pc2xx harmony arm armv7 harmony nvidia tegra2 diff --git a/include/configs/origen.h b/include/configs/origen.h new file mode 100644 index 0000000000..e8252cc311 --- /dev/null +++ b/include/configs/origen.h @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Configuration settings for the SAMSUNG ORIGEN (S5PV310) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG 1 /* SAMSUNG core */ +#define CONFIG_S5P 1 /* S5P Family */ +#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */ +#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ + +#include /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Keep L2 Cache Disabled */ +#define CONFIG_L2_OFF 1 +#define CONFIG_SYS_DCACHE_OFF 1 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* input clock of PLL: ORIGEN has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */ +#define MACH_TYPE_ORIGEN 3455 +#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ +#define CONFIG_BAUDRATE 115200 +#define S5PC210_DEFAULT_UART_OFFSET 0x020000 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_MMC 1 +#define CONFIG_S5P_MMC 1 + +/* PWM */ +#define CONFIG_PWM 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "ORIGEN # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Stack sizes */ +#define CONFIG_STACKSIZE (256 << 10) /* 256KB */ + +/* ORIGEN has 4 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH 1 +#undef CONFIG_CMD_IMLS +#define CONFIG_IDENT_STRING " for ORIGEN" + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +#define CONFIG_CLK_1000_400_200 + +/* MIU (Memory Interleaving Unit) */ +#define CONFIG_MIU_2BIT_21_7_INTERLEAVED + +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ +#define RESERVE_BLOCK_SIZE (512) +#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +#endif /* __CONFIG_H */ From 98a48c5de545e5a5eedba0a868024ef0d4ae5347 Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Thu, 18 Aug 2011 22:37:20 +0000 Subject: [PATCH 083/145] ORIGEN: Add MMC SPL support Adds mmc boot support. Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang --- board/samsung/origen/Makefile | 20 +++- board/samsung/origen/mmc_boot.c | 58 ++++++++++ board/samsung/origen/tools/mkv310_image.c | 126 ++++++++++++++++++++++ include/configs/origen.h | 8 ++ spl/Makefile | 10 ++ 5 files changed, 221 insertions(+), 1 deletion(-) create mode 100644 board/samsung/origen/mmc_boot.c create mode 100644 board/samsung/origen/tools/mkv310_image.c diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 65eff91c91..f5c6507337 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -26,16 +26,34 @@ LIB = $(obj)lib$(BOARD).o SOBJS := mem_setup.o SOBJS += lowlevel_init.o + +ifndef CONFIG_SPL_BUILD COBJS += origen.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS += mmc_boot.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -all: $(obj).depend $(LIB) +ALL +=$(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL += tools/mk$(BOARD)spl.exe +endif + +all: $(ALL) $(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) +ifdef CONFIG_SPL_BUILD +tools/mk$(BOARD)spl.exe: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c new file mode 100644 index 0000000000..072f16146c --- /dev/null +++ b/board/samsung/origen/mmc_boot.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* +* Copy U-boot from mmc to RAM: +* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains +* Pointer to API (Data transfer from mmc to ram) +*/ +void copy_uboot_to_ram(void) +{ + u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + + copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + copy_uboot_to_ram(); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* Function attribute is no-return */ + /* This Function never executes */ + while (1) + ; +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkv310_image.c new file mode 100644 index 0000000000..158aab5cf9 --- /dev/null +++ b/board/samsung/origen/tools/mkv310_image.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#define BUFSIZE (16*1024) +#define IMG_SIZE (16*1024) +#define SPL_HEADER_SIZE 16 +#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ + | S_IWGRP | S_IROTH | S_IWOTH) +#define SPL_HEADER "S5PC210 HEADER " +/* +* Requirement: +* IROM code reads first 14K bytes from boot device. +* It then calculates the checksum of 14K-4 bytes and compare with data at +* 14K-4 offset. +* +* This function takes two filenames: +* IN "u-boot-spl.bin" and +* OUT "$(BOARD)-spl.bin as filenames. +* It reads the "u-boot-spl.bin" in 16K buffer. +* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. +* It writes the buffer to "$(BOARD)-spl.bin" file. +*/ + +int main(int argc, char **argv) +{ + int i, len; + unsigned char buffer[BUFSIZE] = {0}; + int ifd, ofd; + unsigned int checksum = 0, count; + + if (argc != 3) { + printf(" %d Wrong number of arguments\n", argc); + exit(EXIT_FAILURE); + } + + ifd = open(argv[1], O_RDONLY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[1], strerror(errno)); + exit(EXIT_FAILURE); + } + + ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[2], strerror(errno)); + if (ifd) + close(ifd); + exit(EXIT_FAILURE); + } + + len = lseek(ifd, 0, SEEK_END); + lseek(ifd, 0, SEEK_SET); + + memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE); + + count = (len < (IMG_SIZE - SPL_HEADER_SIZE)) + ? len : (IMG_SIZE - SPL_HEADER_SIZE); + + if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) { + fprintf(stderr, "%s: Can't read %s: %s\n", + argv[0], argv[1], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++) + checksum += buffer[i+16]; + + *(ulong *)buffer ^= 0x1f; + *(ulong *)(buffer+4) ^= checksum; + + for (i = 1; i < SPL_HEADER_SIZE; i++) + buffer[i] ^= buffer[i-1]; + + if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { + fprintf(stderr, "%s: Can't write %s: %s\n", + argv[0], argv[2], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + return EXIT_SUCCESS; +} diff --git a/include/configs/origen.h b/include/configs/origen.h index e8252cc311..889d5fc727 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -94,6 +94,9 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK +/* MMC SPL */ +#define CONFIG_SPL +#define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" @@ -157,4 +160,9 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define COPY_BL2_SIZE 0x80000 +#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) +#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) #endif /* __CONFIG_H */ diff --git a/spl/Makefile b/spl/Makefile index 87f13f600f..95ecce1563 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -93,8 +93,18 @@ endif ALL-y += $(obj)u-boot-spl.bin +ifdef CONFIG_SAMSUNG +ALL-y += $(obj)$(BOARD)-spl.bin +endif + all: $(ALL-y) +ifdef CONFIG_SAMSUNG +$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin + $(TOPDIR)/board/$(BOARDDIR)/tools/mk$(BOARD)spl.exe \ + $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin +endif + $(obj)u-boot-spl.bin: $(obj)u-boot-spl $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ From cba4b1809f043bf85c806e5a4e342f62bd5ded45 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Tue, 16 Aug 2011 04:33:05 +0000 Subject: [PATCH 084/145] arm: do not force d-cache enable on all boards c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() to board_init_r(). This enables d-cache for all ARM boards. As a result some of the arm boards that are not cache-ready are broken. Revert this change and allow platform code to take the decision on d-cache enabling. Also add some documentation for cache usage in ARM. Signed-off-by: Aneesh V --- arch/arm/lib/board.c | 8 +++---- arch/arm/lib/cache.c | 12 ++++++++++ doc/README.arm-caches | 51 +++++++++++++++++++++++++++++++++++++++++++ include/common.h | 1 + 4 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 doc/README.arm-caches diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index c899839852..a7fb251aa7 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -452,11 +452,9 @@ void board_init_r(gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ monitor_flash_len = _end_ofs; - /* - * Enable D$: - * I$, if needed, must be already enabled in start.S - */ - dcache_enable(); + + /* Enable caches */ + enable_caches(); debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2653..b545fb79bc 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,15 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + + +/* + * Default implementation of enable_caches() + * Real implementation should be in platform code + */ +void __enable_caches(void) +{ + puts("WARNING: Caches not enabled\n"); +} +void enable_caches(void) + __attribute__((weak, alias("__enable_caches"))); diff --git a/doc/README.arm-caches b/doc/README.arm-caches new file mode 100644 index 0000000000..cd2b4587c2 --- /dev/null +++ b/doc/README.arm-caches @@ -0,0 +1,51 @@ +Disabling I-cache: +- Set CONFIG_SYS_ICACHE_OFF + +Disabling D-cache: +- Set CONFIG_SYS_DCACHE_OFF + +Enabling I-cache: +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). + +Enabling D-cache: +- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable(). + +Enabling Caches at System Startup: +- Implement enable_caches() for your platform and enable the I-cache and + D-cache from this function. This function is called immediately + after relocation. + +Guidelines for Working with D-cache: + +Memory to Peripheral DMA: +- Flush the buffer after the MPU writes the data and before the DMA is + initiated. + +Peripheral to Memory DMA: +- Invalidate the buffer before starting the DMA. In case there are any dirty + lines from the DMA buffer in the cache, subsequent cache-line replacements + may corrupt the buffer in memory while the DMA is still going on. Cache-line + replacement can happen if the CPU tries to bring some other memory locations + into the cache while the DMA is going on. +- Invalidate the buffer after the DMA is complete and before the MPU reads + it. This may be needed in addition to the invalidation before the DMA + mentioned above, because in some processors memory contents can spontaneously + come to the cache due to speculative memory access by the CPU. If this + happens with the DMA buffer while DMA is going on we have a coherency problem. + +Buffer Requirements: +- Any buffer that is invalidated(that is, typically the peripheral to + memory DMA buffer) should be aligned to cache-line boundary both at + at the beginning and at the end of the buffer. +- If the buffer is not cache-line aligned invalidation will be restricted + to the aligned part. That is, one cache-line at the respective boundary + may be left out while doing invalidation. + +Cleanup Before Linux: +- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and + disable MMU and caches. +- The following sequence is advisable while disabling d-cache: + 1. disable_dcache() - flushes and disables d-cache + 2. invalidate_dcache_all() - invalid any entry that came to the cache + in the short period after the cache was flushed but before the + cache got disabled. diff --git a/include/common.h b/include/common.h index 12a10741bd..bd10f31f84 100644 --- a/include/common.h +++ b/include/common.h @@ -616,6 +616,7 @@ ulong lcd_setmem (ulong); ulong video_setmem (ulong); /* arch/$(ARCH)/lib/cache.c */ +void enable_caches(void); void flush_cache (unsigned long, unsigned long); void flush_dcache_all(void); void flush_dcache_range(unsigned long start, unsigned long stop); From 13d4f9bd7477b3b409f3e267b3b3d6fed5bd3e30 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 11 Aug 2011 04:35:43 +0000 Subject: [PATCH 085/145] omap: enable caches at system start-up Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/omap3/board.c | 8 ++++++++ arch/arm/cpu/armv7/omap4/board.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index bce3ee695f..0448bc93ff 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -402,3 +402,11 @@ void v7_outer_cache_disable(void) omap3_update_aux_cr(0, 0x2); } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 8e9054594d..69a0ce5513 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -299,3 +299,11 @@ void v7_outer_cache_disable(void) set_pl310_ctrl_reg(0); } #endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif From 882f80b993f3719cce5bfa7f1bca9b1b23062b5f Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 11 Aug 2011 04:35:44 +0000 Subject: [PATCH 086/145] armv7: stronger barrier for cache-maintenance operations set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/cache_v7.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf877..665f025b6f 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -227,8 +227,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) break; } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } /* Invalidate TLB */ From cabe2878a8201441a8aa4c482acb568f9ca137f0 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 11 Aug 2011 04:35:45 +0000 Subject: [PATCH 087/145] armv7: cache: remove flush on un-aligned invalidate Remove the flush of boundary cache-lines done as part of invalidate on a non cache-line boundary aligned buffer Also, print a warning when this situation is recognized. Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/cache_v7.c | 14 ++++++++------ arch/arm/lib/cache-pl310.c | 15 +++++++++------ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 665f025b6f..1b4e808a79 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) u32 mva; /* - * If start address is not aligned to cache-line flush the first - * line to prevent affecting somebody else's buffer + * If start address is not aligned to cache-line do not + * invalidate the first cache-line */ if (start & (line_len - 1)) { - v7_dcache_clean_inval_range(start, start + 1, line_len); + printf("ERROR: %s - start address is not aligned - 0x%08x\n", + __func__, start); /* move to next cache line */ start = (start + line_len - 1) & ~(line_len - 1); } /* - * If stop address is not aligned to cache-line flush the last - * line to prevent affecting somebody else's buffer + * If stop address is not aligned to cache-line do not + * invalidate the last cache-line */ if (stop & (line_len - 1)) { - v7_dcache_clean_inval_range(stop, stop + 1, line_len); + printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_len - 1); } diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 36c629ce51..21d13f787a 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -26,6 +26,7 @@ #include #include #include +#include struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop) u32 pa, line_size = 32; /* - * If start address is not aligned to cache-line flush the first - * line to prevent affecting somebody else's buffer + * If start address is not aligned to cache-line do not + * invalidate the first cache-line */ if (start & (line_size - 1)) { - v7_outer_cache_flush_range(start, start + 1); + printf("ERROR: %s - start address is not aligned - 0x%08x\n", + __func__, start); /* move to next cache line */ start = (start + line_size - 1) & ~(line_size - 1); } /* - * If stop address is not aligned to cache-line flush the last - * line to prevent affecting somebody else's buffer + * If stop address is not aligned to cache-line do not + * invalidate the last cache-line */ if (stop & (line_size - 1)) { - v7_outer_cache_flush_range(stop, stop + 1); + printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_size - 1); } From c4f4c760c9bdbad6c4f286edfff79e34d96ec5f6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 20 Aug 2011 14:24:49 +0200 Subject: [PATCH 088/145] PXA: Fix Lubbock, remove redundant parenthesis Signed-off-by: Marek Vasut --- board/lubbock/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index 1ea2893fd0..e1e7807bc1 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -408,7 +408,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } From dd0fb51d49051d3a6140a10ee8c48c3acd3732c7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 20 Aug 2011 14:26:11 +0200 Subject: [PATCH 089/145] PXA: Fix CSB226, fix monitor length This is what was probably intended by the original author. Signed-off-by: Marek Vasut --- include/configs/csb226.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/csb226.h b/include/configs/csb226.h index dcfbc6e686..934dfcdef2 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -141,7 +141,7 @@ /* ^^ Run Mode Speed = 2x Mem Speed */ /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ +#define CONFIG_SYS_MONITOR_LEN 0x1c000 /* 112 KiB */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } From 904a20bcea56b7409747a3af6ecca740a0f97fe4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Aug 2011 03:37:48 +0200 Subject: [PATCH 090/145] PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE Signed-off-by: Marek Vasut --- include/configs/vpac270.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 35afcd356c..ea779716f2 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -51,7 +51,6 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* From f62b1257f206ba5c54d696a09fe0c79eca007636 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sat, 3 Sep 2011 21:24:19 -0400 Subject: [PATCH 091/145] OMAP3/4: Increase console I/O buffer size Increase the console I/O buffer size (SYS_CBSIZE) to 512 (from 256) required especially for bootargs string, as multiple options (e.g Video settings) are passed to the kernel through bootargs. Signed-off-by: Vaibhav Hiremath Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- include/configs/omap4_panda.h | 2 +- include/configs/omap4_sdp4430.h | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index d7cbc2fe6d..ec48abcf46 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -261,7 +261,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index afa18aab39..6c46badf8b 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -237,7 +237,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP3_EVM # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index d6e0a0614d..821a8a3275 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -213,7 +213,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "Overo # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index bd55abc05d..097608632a 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -196,7 +196,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "Pandora # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index e1d8c7870e..a47cb6bbc4 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -269,7 +269,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP34XX SDP # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index aeac7c70c1..f106b3840b 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -220,7 +220,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 2a56182b94..71330370dd 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -200,7 +200,7 @@ #define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 814f15c5c4..6faf0e2f99 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -184,7 +184,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "Panda # " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 1a5d7a66c5..ba6f49d030 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -190,7 +190,7 @@ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "OMAP4430 SDP # " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) From f4dac3e16c1a08eb087e711a7e0ada3cf390d7ea Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sat, 3 Sep 2011 21:29:59 -0400 Subject: [PATCH 092/145] omap3:clock: configure GFX clock to 200MHz for AM/DM37x AM/DM37x is another OMAP3 variant, where the GFX clock has been boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change. HW Errata: Due to dependency of TV out clock of 54MHz, it is not possible to configure GFX to 192MHz. So as per HW errats, the recommended GFX clock is 200MHz (=CORE_CLK/2). Signed-off-by: Vaibhav Hiremath Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/omap3/clock.c | 2 +- arch/arm/include/asm/arch-omap3/clocks_omap3.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3d38d08ccb..29ff7131de 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) /* L3 */ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); /* GFX */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X); /* RESET MGR */ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index ef600dd9db..db29b7c6df 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -39,6 +39,7 @@ #define CORE_L4_DIV 2 /* 83MHz : L4 */ #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ /* PER DPLL */ From 7dd5a5be2fe8a23eb1bed2d3be8d3c6eade78c58 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sat, 3 Sep 2011 21:35:31 -0400 Subject: [PATCH 093/145] omap3:clock: check cpu_family before enabling clks for IVA & CAM In case of AM3517 and AM3505 (which is OMAP3 varients), IVA2 and ISP-CAMERA modules have been removed. So add check for cpu_family before enabling clocks for these modules, else this impacts subsequent power consumption and system suspend/resume functionality. Signed-off-by: Vaibhav Hiremath Signed-off-by: Ranjith Lohithakshan Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/omap3/clock.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 29ff7131de..4b66affbee 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -607,7 +607,9 @@ void prcm_init(void) dpll3_init_34xx(sil_index, clk_index); dpll4_init_34xx(sil_index, clk_index); dpll5_init_34xx(sil_index, clk_index); - iva_init_34xx(sil_index, clk_index); + if (get_cpu_family() != CPU_AM35XX) + iva_init_34xx(sil_index, clk_index); + mpu_init_34xx(sil_index, clk_index); /* Lock MPU DPLL to set frequency */ @@ -674,7 +676,9 @@ void per_clocks_enable(void) /* Enable the ICLK for 32K Sync Timer as its used in udelay */ sr32(&prcm_base->iclken_wkup, 2, 1, 0x1); - sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON); + if (get_cpu_family() != CPU_AM35XX) + sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON); + sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON); sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON); sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON); @@ -682,8 +686,10 @@ void per_clocks_enable(void) sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON); sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON); sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON); - sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); - sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); + if (get_cpu_family() != CPU_AM35XX) { + sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); + sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); + } sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); From dcc4f38b4384fc6e63e3674100737ea6e250a19f Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sat, 3 Sep 2011 21:42:35 -0400 Subject: [PATCH 094/145] omap3evm: Use generic MMC driver Switch from the legacy mmc driver to the new generic mmc driver. This patch is based on similar patch for beagle[1]. [1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240 Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- board/ti/evm/evm.c | 9 +++++++++ include/configs/omap3_evm.h | 10 ++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 30c1c570f1..e8360df960 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -221,3 +222,11 @@ int board_eth_init(bd_t *bis) return rc; } #endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 6c46badf8b..fdc861d9d4 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -97,7 +97,8 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ @@ -198,6 +199,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ + "mmcdev=0\0" \ "console=ttyS2,115200n8\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rw " \ @@ -205,10 +207,10 @@ "nandargs=setenv bootargs console=${console} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -218,7 +220,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ From 122e6e0a97f08b146b066eb384c8335c80214fd1 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sat, 3 Sep 2011 21:47:44 -0400 Subject: [PATCH 095/145] am3517evm: Use generic MMC driver Switch from the legacy mmc driver to the new generic mmc driver. This patch is based on similar patch for beagle[1]. [1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240 Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- board/logicpd/am3517evm/am3517evm.c | 9 +++++++++ include/configs/am3517_evm.h | 10 ++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index bbb6e834ec..c0a006a7b3 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include "am3517evm.h" @@ -74,3 +75,11 @@ void set_muxconf_regs(void) { MUX_AM3517EVM(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6c5728db59..72dd6f02ce 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -93,7 +93,8 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* @@ -190,16 +191,17 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "mmcdev=0\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ "nandargs=setenv bootargs console=${console} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -209,7 +211,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ From 28fed362356eed6962c011e94440ccfe662f8524 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:49:24 -0400 Subject: [PATCH 096/145] OMAP3: CM-T35: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/cm_t35/cm_t35.c | 8 ++++++++ include/configs/cm_t35.h | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index f82111bac2..420cd70dee 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -313,6 +313,14 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + /* * Routine: setup_net_chip_gmpc * Description: Setting up the configuration GPMC registers specific to the diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 16a5f5b1ed..496a904f2b 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -108,8 +108,9 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ From eaff60d7386bfd247cb1f9054d02da0990cf5abd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:50:05 -0400 Subject: [PATCH 097/145] OMAP3: DIG297: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/comelit/dig297/dig297.c | 9 +++++++++ include/configs/dig297.h | 5 +++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 0062f120d7..a7071cd554 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -145,6 +146,14 @@ void set_muxconf_regs(void) MUX_DIG297(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET /* * Routine: setup_net_chip diff --git a/include/configs/dig297.h b/include/configs/dig297.h index b68f07383a..0e05df3b5e 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -97,8 +97,9 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_MMC -#define CONFIG_OMAP3_MMC +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION /* DDR - I use Micron DDR */ From d6906cb812fe3264339a62874d4463b2e1d3f902 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:50:35 -0400 Subject: [PATCH 098/145] OMAP3: Zoom1: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/logicpd/zoom1/zoom1.c | 9 +++++++++ include/configs/omap3_zoom1.h | 10 ++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 7ef13cc623..dec0b2611f 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,14 @@ void set_muxconf_regs(void) MUX_ZOOM1_MDK(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index f106b3840b..fbac22235c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -95,8 +95,9 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ @@ -178,6 +179,7 @@ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ + "mmcdev=0\0" \ "videomode=1024x768@60,vxres=1024,vyres=768\0" \ "videospec=omapfb:vram:2M,vram:4M\0" \ "mmcargs=setenv bootargs console=${console} " \ @@ -188,10 +190,10 @@ "video=${videospec},mode:${videomode} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -201,7 +203,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ From cfc4384c840ae76ee4a2f9080daa8bd3b9013155 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:51:00 -0400 Subject: [PATCH 099/145] OMAP3: Zoom2: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/logicpd/zoom2/zoom2.c | 9 +++++++++ include/configs/omap3_zoom2.h | 3 ++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index 76793e42e7..800113a976 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -35,6 +35,7 @@ #endif #include #include +#include #include #include #include @@ -180,6 +181,14 @@ void set_muxconf_regs (void) MUX_ZOOM2 (); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 71330370dd..8de3d317f0 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -95,8 +95,9 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ From 86c5c54409cfcf20ae7ae75f567fa9a4c4a2e87e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:51:25 -0400 Subject: [PATCH 100/145] OMAP3: pandora: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/pandora/pandora.c | 9 +++++++++ include/configs/omap3_pandora.h | 5 +++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 0df45702c7..58a676d455 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -103,3 +104,11 @@ void set_muxconf_regs(void) { MUX_PANDORA(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 097608632a..3c2793ea42 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -100,8 +100,9 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* DDR - I use Micron DDR */ @@ -182,7 +183,7 @@ "mtdparts=" MTDPARTS_DEFAULT "\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc1 0 ${loadaddr} autoboot.scr || " \ + "if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \ "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \ "source ${loadaddr}; " \ "fi; " \ From a5a8821c47fa767d8946b3ace461c6f0cd285522 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:51:50 -0400 Subject: [PATCH 101/145] AM3517 CraneBoard: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/ti/am3517crane/am3517crane.c | 9 +++++++++ include/configs/am3517_crane.h | 10 ++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index d007044b2d..cd5683d9be 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -73,3 +74,11 @@ void set_muxconf_regs(void) { MUX_AM3517CRANE(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 743768e0f5..e23ca45dd5 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -93,8 +93,9 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* @@ -191,16 +192,17 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ + "mmcdev=0\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ "nandargs=setenv bootargs console=${console} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -210,7 +212,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ From 7cc862be8562667bde6159b6fb84858e3ddddc5a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:52:21 -0400 Subject: [PATCH 102/145] TI OMAP3 SDP3430: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/ti/sdp3430/sdp.c | 9 +++++++++ include/configs/omap3_sdp3430.h | 3 ++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 72f0984d67..d73f501819 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -204,3 +205,11 @@ void set_muxconf_regs(void) /* platform specific muxes */ MUX_SDP3430(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index a47cb6bbc4..6a826ba69b 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -189,8 +189,9 @@ */ #if defined(CONFIG_CMD_MMC) +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 #endif From f408501d2d18a75b1ade9e7451cc5e28c9e026c1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:52:45 -0400 Subject: [PATCH 103/145] devkit8000: Use generic MMC driver Switch from the legacy omap3 mmc driver to the new generic omap hsmmc driver. This patch is based on the work done for Beagle, etc. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- board/timll/devkit8000/devkit8000.c | 9 +++++++++ include/configs/devkit8000.h | 10 ++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 95afaaaaa4..533af5a60a 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,14 @@ void set_muxconf_regs(void) MUX_DEVKIT8000(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_DRIVER_DM9000 /* * Routine: board_eth_init diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cf77606fe0..710092de36 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -98,8 +98,9 @@ 115200} /* MMC */ +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 /* I2C */ @@ -181,6 +182,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ + "mmcdev=0\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -213,10 +215,10 @@ "${kernelopts} " \ "dnsip1=${dnsip} " \ "dnsip2=${dnsip2}\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ @@ -229,7 +231,7 @@ "dhcp ${loadaddr}; " \ "run netargs; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc init 0; then " \ + "autoboot=if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ From c318dbf07913c3b00d1eb28ade87cc67662bd99d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 3 Sep 2011 21:53:20 -0400 Subject: [PATCH 104/145] OMAP3: Remove legacy mmc driver Now that all platforms have been migrated to the new MMC driver, remove the old one. Signed-off-by: Tom Rini Signed-off-by: Sandeep Paulraj --- drivers/mmc/Makefile | 1 - drivers/mmc/omap3_mmc.c | 570 ---------------------------------------- drivers/mmc/omap3_mmc.h | 233 ---------------- 3 files changed, 804 deletions(-) delete mode 100644 drivers/mmc/omap3_mmc.c delete mode 100644 drivers/mmc/omap3_mmc.h diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3968c14bb0..e5ca121ed7 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -35,7 +35,6 @@ COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o -COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c deleted file mode 100644 index 15d41e55bd..0000000000 --- a/drivers/mmc/omap3_mmc.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "omap3_mmc.h" - -static const unsigned short mmc_transspeed_val[15][4] = { - {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, - {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, - {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, - {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, - {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, - {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, - {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, - {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, - {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, - {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, - {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, - {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, - {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, - {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, - {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} -}; - -static mmc_card_data cur_card_data; -static block_dev_desc_t mmc_blk_dev; -static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE; - -int mmc_set_dev(int dev_num) -{ - switch (dev_num) { - case 1: - mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE; - break; - case 2: - mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE; - break; - case 3: - mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE; - break; - default: - mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE; - return 1; - } - - return 0; -} - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return (block_dev_desc_t *) &mmc_blk_dev; -} - -static unsigned char mmc_board_init(void) -{ -#if defined(CONFIG_TWL4030_POWER) - twl4030_power_mmc_init(); -#endif - -#if defined(CONFIG_OMAP34XX) - t2_t *t2_base = (t2_t *)T2_BASE; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - - writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | - PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, - &t2_base->pbias_lite); - - writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, - &t2_base->devconf0); - - writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, - &t2_base->devconf1); - - writel(readl(&prcm_base->fclken1_core) | - EN_MMC1 | EN_MMC2 | EN_MMC3, - &prcm_base->fclken1_core); - - writel(readl(&prcm_base->iclken1_core) | - EN_MMC1 | EN_MMC2 | EN_MMC3, - &prcm_base->iclken1_core); -#endif - -/* TODO add appropriate OMAP4 init */ - - return 1; -} - -static void mmc_init_stream(void) -{ - writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); - - writel(MMC_CMD0, &mmc_base->cmd); - while (!(readl(&mmc_base->stat) & CC_MASK)); - - writel(CC_MASK, &mmc_base->stat); - - writel(MMC_CMD0, &mmc_base->cmd); - while (!(readl(&mmc_base->stat) & CC_MASK)); - - writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); -} - -static unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) -{ - unsigned int val; - - mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); - - switch (iclk) { - case CLK_INITSEQ: - val = MMC_INIT_SEQ_CLK / 2; - break; - case CLK_400KHZ: - val = MMC_400kHz_CLK; - break; - case CLK_MISC: - val = clk_div; - break; - default: - return 0; - } - mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, - (val << CLKD_OFFSET) | ICE_OSCILLATE); - - while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY); - - writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); - return 1; -} - -static unsigned char mmc_init_setup(void) -{ - unsigned int reg_val; - - mmc_board_init(); - - writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, - &mmc_base->sysconfig); - while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0); - - writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); - while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0); - - writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); - writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, - &mmc_base->capa); - - reg_val = readl(&mmc_base->con) & RESERVED_MASK; - - writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | - MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | - HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); - - mmc_clock_config(CLK_INITSEQ, 0); - writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); - - writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, - &mmc_base->ie); - - mmc_init_stream(); - return 1; -} - -static unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, - unsigned int *response) -{ - unsigned int mmc_stat; - - while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS); - - writel(BLEN_512BYTESLEN | NBLK_STPCNT, &mmc_base->blk); - writel(0xFFFFFFFF, &mmc_base->stat); - writel(arg, &mmc_base->arg); - writel(cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | - MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE, - &mmc_base->cmd); - - while (1) { - do { - mmc_stat = readl(&mmc_base->stat); - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & CC_MASK) { - writel(CC_MASK, &mmc_base->stat); - response[0] = readl(&mmc_base->rsp10); - if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { - response[1] = readl(&mmc_base->rsp32); - response[2] = readl(&mmc_base->rsp54); - response[3] = readl(&mmc_base->rsp76); - } - break; - } - } - return 1; -} - -static unsigned char mmc_read_data(unsigned int *output_buf) -{ - unsigned int mmc_stat; - unsigned int read_count = 0; - - /* - * Start Polled Read - */ - while (1) { - do { - mmc_stat = readl(&mmc_base->stat); - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & BRR_MASK) { - unsigned int k; - - writel(readl(&mmc_base->stat) | BRR_MASK, - &mmc_base->stat); - for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { - *output_buf = readl(&mmc_base->data); - output_buf++; - read_count += 4; - } - } - - if (mmc_stat & BWR_MASK) - writel(readl(&mmc_base->stat) | BWR_MASK, - &mmc_base->stat); - - if (mmc_stat & TC_MASK) { - writel(readl(&mmc_base->stat) | TC_MASK, - &mmc_base->stat); - break; - } - } - return 1; -} - -static unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) -{ - unsigned char err; - unsigned int argument = 0; - unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; - unsigned short retry_cnt = 2000; - mmc_resp_t mmc_resp; - - /* Set to Initialization Clock */ - err = mmc_clock_config(CLK_400KHZ, 0); - if (err != 1) - return err; - - mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; - argument = 0x00000000; - - ocr_value = (0x1FF << 15); - err = mmc_send_cmd(MMC_CMD0, argument, mmc_resp.resp); - if (err != 1) - return err; - - argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; - err = mmc_send_cmd(MMC_SDCMD8, argument, mmc_resp.resp); - hcs_val = (err == 1) ? - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; - - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp); - if (err == 1) { - mmc_card_cur->card_type = SD_CARD; - ocr_value |= hcs_val; - ret_cmd41 = MMC_ACMD41; - } else { - mmc_card_cur->card_type = MMC_CARD; - ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; - ret_cmd41 = MMC_CMD1; - writel(readl(&mmc_base->con) & ~OD, &mmc_base->con); - writel(readl(&mmc_base->con) | OPENDRAIN, &mmc_base->con); - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp); - if (err != 1) - return err; - - ocr_recvd = mmc_resp.r3.ocr; - - while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { - retry_cnt--; - if (mmc_card_cur->card_type == SD_CARD) { - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp); - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp); - if (err != 1) - return err; - ocr_recvd = mmc_resp.r3.ocr; - } - - if (!(ocr_recvd & (0x1 << 31))) - return 0; - - if (mmc_card_cur->card_type == MMC_CARD) { - if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == - MMC_OCR_REG_ACCESS_MODE_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - - ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; - } else { - if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) - == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; - } - - ocr_recvd &= ~(0x1 << 31); - if (!(ocr_recvd & ocr_value)) - return 0; - - err = mmc_send_cmd(MMC_CMD2, argument, mmc_resp.resp); - if (err != 1) - return err; - - if (mmc_card_cur->card_type == MMC_CARD) { - argument = mmc_card_cur->RCA << 16; - err = mmc_send_cmd(MMC_CMD3, argument, mmc_resp.resp); - if (err != 1) - return err; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_SDCMD3, argument, mmc_resp.resp); - if (err != 1) - return err; - - mmc_card_cur->RCA = mmc_resp.r6.newpublishedrca; - } - - writel(readl(&mmc_base->con) & ~OD, &mmc_base->con); - writel(readl(&mmc_base->con) | NOOPENDRAIN, &mmc_base->con); - return 1; -} - -static unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, - mmc_csd_reg_t *cur_csd) -{ - mmc_extended_csd_reg_t ext_csd; - unsigned int size, count, blk_len, blk_no, card_size, argument; - unsigned char err; - unsigned int resp[4]; - - if (mmc_dev_data->mode == SECTOR_MODE) { - if (mmc_dev_data->card_type == SD_CARD) { - card_size = - (((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | - ((((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) - << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); - mmc_dev_data->size = card_size * 1024; - if (mmc_dev_data->size == 0) - return 0; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_CMD8, argument, resp); - if (err != 1) - return err; - err = mmc_read_data((unsigned int *) &ext_csd); - if (err != 1) - return err; - mmc_dev_data->size = ext_csd.sectorcount; - - if (mmc_dev_data->size == 0) - mmc_dev_data->size = 8388608; - } - } else { - if (cur_csd->c_size_mult >= 8) - return 0; - - if (cur_csd->read_bl_len >= 12) - return 0; - - /* Compute size */ - count = 1 << (cur_csd->c_size_mult + 2); - card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | - ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) - << MMC_CSD_C_SIZE_MSB_OFFSET); - blk_no = (card_size + 1) * count; - blk_len = 1 << cur_csd->read_bl_len; - size = blk_no * blk_len; - mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; - if (mmc_dev_data->size == 0) - return 0; - } - return 1; -} - -static unsigned long mmc_bread(int dev_num, unsigned long blknr, - lbaint_t blkcnt, void *dst) -{ - unsigned char err; - unsigned int argument; - unsigned int resp[4]; - unsigned int *output_buf = dst; - unsigned int sec_inc_val; - lbaint_t i; - - if (blkcnt == 0) - return 0; - - if (cur_card_data.mode == SECTOR_MODE) { - argument = blknr; - sec_inc_val = 1; - } else { - argument = blknr * MMCSD_SECTOR_SIZE; - sec_inc_val = MMCSD_SECTOR_SIZE; - } - - for (i = 0; i < blkcnt; i++) { - err = mmc_send_cmd(MMC_CMD17, argument, resp); - if (err != 1) { - printf("mmc: CMD17 failed, status = %08x\n", err); - break; - } - - err = mmc_read_data(output_buf); - if (err != 1) { - printf("mmc: read failed, status = %08x\n", err); - break; - } - - output_buf += (MMCSD_SECTOR_SIZE / 4); - argument += sec_inc_val; - } - - return i; -} - -static unsigned char configure_mmc(mmc_card_data *mmc_card_cur) -{ - unsigned char ret_val; - unsigned int argument; - unsigned int trans_clk, trans_fact, trans_unit, retries = 2; - unsigned char trans_speed; - mmc_resp_t mmc_resp; - - ret_val = mmc_init_setup(); - - if (ret_val != 1) - return ret_val; - - do { - ret_val = mmc_detect_card(mmc_card_cur); - retries--; - } while ((retries > 0) && (ret_val != 1)); - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD9, argument, mmc_resp.resp); - if (ret_val != 1) - return ret_val; - - if (mmc_card_cur->card_type == MMC_CARD) - mmc_card_cur->version = mmc_resp.Card_CSD.spec_vers; - - trans_speed = mmc_resp.Card_CSD.tran_speed; - - ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, mmc_resp.resp); - if (ret_val != 1) - return ret_val; - - trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; - trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; - - if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) - return 0; - - if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || - (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) - return 0; - - trans_unit >>= 0; - trans_fact >>= 3; - - trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2; - ret_val = mmc_clock_config(CLK_MISC, trans_clk); - - if (ret_val != 1) - return ret_val; - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, mmc_resp.resp); - if (ret_val != 1) - return ret_val; - - /* Configure the block length to 512 bytes */ - argument = MMCSD_SECTOR_SIZE; - ret_val = mmc_send_cmd(MMC_CMD16, argument, mmc_resp.resp); - if (ret_val != 1) - return ret_val; - - /* get the card size in sectors */ - ret_val = mmc_read_cardsize(mmc_card_cur, &mmc_resp.Card_CSD); - if (ret_val != 1) - return ret_val; - - return 1; -} - -int mmc_legacy_init(int dev) -{ - if (mmc_set_dev(dev) != 0) - return 1; - - if (configure_mmc(&cur_card_data) != 1) - return 1; - - mmc_blk_dev.if_type = IF_TYPE_MMC; - mmc_blk_dev.part_type = PART_TYPE_DOS; - mmc_blk_dev.dev = 0; - mmc_blk_dev.lun = 0; - mmc_blk_dev.type = 0; - - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE; - mmc_blk_dev.lba = 0x10000; - mmc_blk_dev.removable = 0; - mmc_blk_dev.block_read = mmc_bread; - - fat_register_device(&mmc_blk_dev, 1); - return 0; -} diff --git a/drivers/mmc/omap3_mmc.h b/drivers/mmc/omap3_mmc.h deleted file mode 100644 index e4d263c877..0000000000 --- a/drivers/mmc/omap3_mmc.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT 0x0404 -#define SD_CMD8_CHECK_PATTERN 0xAA -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE 96 -#define MMC_RELATIVE_CARD_ADDRESS 0x1234 -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF -#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16 -#define MMC_CSD_C_SIZE_LSB_MASK 0x0003 -#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF -#define MMC_CSD_C_SIZE_MSB_OFFSET 2 - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -typedef union { - unsigned int resp[4]; - mmc_resp_r3 r3; - mmc_resp_r6 r6; - mmc_csd_reg_t Card_CSD; -} mmc_resp_t; - -#endif /* MMC_H */ From 913a39e9aa4d935948d41cd727d53f5878414a77 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:12:56 -0400 Subject: [PATCH 105/145] dm6446: disable cache usage due to coherency issues there are cache coherency issues when using the DAVINCI Ethernet driver, hence caches cant be used for dm6446 u-boot. As per new cache management framework,if the caches are not used in u-boot, it needs to be explicitly indicated through macros in config file. CACHE disable is indicated by the following macro definitions in config file, 1. CONFIG_SYS_ICACHE_OFF 2. CONFIG_SYS_DCACHE_OFF 3. CONFIG_SYS_L2CACHE_OFF Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/davinci_dvevm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 45214fa42a..086a2d7d40 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -60,6 +60,9 @@ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM644X +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_L2CACHE_OFF /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ From 98c19aff9524e1d0dd6bf39bf7bde5644f121feb Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:13:02 -0400 Subject: [PATCH 106/145] dm365: disable cache usage due to coherency issues there are cache coherency issues when using the DAVINCI Ethernet driver, hence caches cant be used for d365 u-boot. As per new cache management framework,if the caches are not used in u-boot, it needs to be explicitly indicated through macros in config file. CACHE disable is indicated by the following macro definitions in config file, 1. CONFIG_SYS_ICACHE_OFF 2. CONFIG_SYS_DCACHE_OFF 3. CONFIG_SYS_L2CACHE_OFF Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/davinci_dm365evm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 28250506a9..172a85214c 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -33,6 +33,9 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM365 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_L2CACHE_OFF /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 From e7b209707cdcce7a9bb21e15a90112b22fc62e43 Mon Sep 17 00:00:00 2001 From: "Rajashekhara, Sudhakar" Date: Sat, 3 Sep 2011 22:13:04 -0400 Subject: [PATCH 107/145] dm365: modify boot prompt from dm365 to dm36x Newer version for DM365 silicon support higher speeds and is called DM368. Modify the bootprompt string DM365 to DM36x. Signed-off-by: Rajashekhara, Sudhakar Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/davinci_dm365evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 172a85214c..28b9db9a70 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -169,7 +169,7 @@ /* U-Boot general configuration */ #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "DM365 EVM # " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "DM36x EVM # " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE /* Print buffer size */ \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) From bd65d006a6088bcb857e079447d7549e2cd7054d Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:17:37 -0400 Subject: [PATCH 108/145] da850: indicate cache usage disable in config file there are cache coherency issues when using the DAVINCI Ethernet driver, hence caches cant be used for da850 u-boot. As per new cache management framework,if the caches are not used in u-boot, it needs to be explicitly indicated through macros in config file. CACHE disable is indicated by the following macro definitions in config file, 1. CONFIG_SYS_ICACHE_OFF 2. CONFIG_SYS_DCACHE_OFF 3. CONFIG_SYS_L2CACHE_OFF Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/da850evm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index bbb5a9b160..fdcc6e3458 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -42,6 +42,9 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_L2CACHE_OFF /* * Memory Info From b7e6843f970a87941d45d4c8a9c41fa9d406e891 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Sat, 3 Sep 2011 22:18:04 -0400 Subject: [PATCH 109/145] da8xx: add support for multiple PLL controllers Modify clk_get() function in cpu file to work for multiple PLL controllers. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 30 +++++++++++++------- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 8b57205ea8..b705dfd318 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -37,6 +37,7 @@ #define PLLC_PLLDIV4 0x160 #define PLLC_PLLDIV5 0x164 #define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV7 0x16c #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 @@ -61,11 +62,9 @@ #endif #ifdef CONFIG_SOC_DA8XX -const dv_reg * const sysdiv[7] = { - &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2, - &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4, - &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6, - &davinci_pllc_regs->plldiv7 +unsigned int sysdiv[9] = { + PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, + PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 }; int clk_get(enum davinci_clk_ids id) @@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id) int pllm; int post_div; int pll_out; + unsigned int pll_base; pll_out = CONFIG_SYS_OSCIN_FREQ; if (id == DAVINCI_AUXCLK_CLKID) goto out; + if ((id >> 16) == 1) + pll_base = (unsigned int)davinci_pllc1_regs; + else + pll_base = (unsigned int)davinci_pllc0_regs; + + id &= 0xFFFF; + /* * Lets keep this simple. Combining operations can result in * unexpected approximations */ - pre_div = (readl(&davinci_pllc_regs->prediv) & - DAVINCI_PLLC_DIV_MASK) + 1; - pllm = readl(&davinci_pllc_regs->pllm) + 1; + pre_div = (readl(pll_base + PLLC_PREDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; + pllm = readl(pll_base + PLLC_PLLM) + 1; pll_out /= pre_div; pll_out *= pllm; @@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id) if (id == DAVINCI_PLLM_CLKID) goto out; - post_div = (readl(&davinci_pllc_regs->postdiv) & - DAVINCI_PLLC_DIV_MASK) + 1; + post_div = (readl(pll_base + PLLC_POSTDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; pll_out /= post_div; if (id == DAVINCI_PLLC_CLKID) goto out; - pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1; + pll_out /= (readl(pll_base + sysdiv[id - 1]) & + DAVINCI_PLLC_DIV_MASK) + 1; out: return pll_out; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index f537c4b1a9..646e2ced82 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_TIMER1_BASE 0x01c21000 #define DAVINCI_WDOG_BASE 0x01c21000 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 +#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 #define DAVINCI_PSC0_BASE 0x01c10000 #define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_SPI0_BASE 0x01c41000 @@ -387,7 +388,8 @@ struct davinci_pllc_regs { dv_reg emucnt1; }; -#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f #define ASYNC3 get_async3_src() From 1506b0a83713f4d537d44bebd8616226fec55279 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:18:32 -0400 Subject: [PATCH 110/145] da850: add NOR boot mode support Add pin-mux support for NOR in board file and correspanding macros to use NOR boot mode in configuration file. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- board/davinci/da8xxevm/da850evm.c | 51 +++++++++++++++++++++++++++++++ include/configs/da850evm.h | 17 +++++++++++ 2 files changed, 68 insertions(+) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 73eaa48b0b..d3d965cdab 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -105,6 +105,55 @@ const struct pinmux_config nand_pins[] = { { pinmux(12), 1, 5 }, { pinmux(12), 1, 6 } }; +#elif defined(CONFIG_USE_NOR) +/* NOR pin muxer settings */ +const struct pinmux_config nor_pins[] = { + { pinmux(5), 1, 6 }, + { pinmux(6), 1, 6 }, + { pinmux(7), 1, 0 }, + { pinmux(7), 1, 4 }, + { pinmux(7), 1, 5 }, + { pinmux(8), 1, 0 }, + { pinmux(8), 1, 1 }, + { pinmux(8), 1, 2 }, + { pinmux(8), 1, 3 }, + { pinmux(8), 1, 4 }, + { pinmux(8), 1, 5 }, + { pinmux(8), 1, 6 }, + { pinmux(8), 1, 7 }, + { pinmux(9), 1, 0 }, + { pinmux(9), 1, 1 }, + { pinmux(9), 1, 2 }, + { pinmux(9), 1, 3 }, + { pinmux(9), 1, 4 }, + { pinmux(9), 1, 5 }, + { pinmux(9), 1, 6 }, + { pinmux(9), 1, 7 }, + { pinmux(10), 1, 0 }, + { pinmux(10), 1, 1 }, + { pinmux(10), 1, 2 }, + { pinmux(10), 1, 3 }, + { pinmux(10), 1, 4 }, + { pinmux(10), 1, 5 }, + { pinmux(10), 1, 6 }, + { pinmux(10), 1, 7 }, + { pinmux(11), 1, 0 }, + { pinmux(11), 1, 1 }, + { pinmux(11), 1, 2 }, + { pinmux(11), 1, 3 }, + { pinmux(11), 1, 4 }, + { pinmux(11), 1, 5 }, + { pinmux(11), 1, 6 }, + { pinmux(11), 1, 7 }, + { pinmux(12), 1, 0 }, + { pinmux(12), 1, 1 }, + { pinmux(12), 1, 2 }, + { pinmux(12), 1, 3 }, + { pinmux(12), 1, 4 }, + { pinmux(12), 1, 5 }, + { pinmux(12), 1, 6 }, + { pinmux(12), 1, 7 } +}; #endif #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII @@ -122,6 +171,8 @@ static const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(i2c_pins), #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(nand_pins), +#elif defined(CONFIG_USE_NOR) + PINMUX_ITEM(nor_pins), #endif }; diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index fdcc6e3458..b1bce11e29 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -29,6 +29,7 @@ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_USE_SPIFLASH + /* * SoC Configuration */ @@ -129,6 +130,22 @@ #define CONFIG_NET_MULTI #endif +#ifdef CONFIG_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) +#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ +#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ + + 3) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#endif + #ifdef CONFIG_USE_SPIFLASH #undef CONFIG_ENV_IS_IN_FLASH #undef CONFIG_ENV_IS_IN_NAND From ac935e567bee77b39fc37c1ad360bb0d1ac07c4e Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:18:59 -0400 Subject: [PATCH 111/145] da850: modify the U-Boot prompt string Modify U-Boot prompt string from "DA850-evm >" to "U-Boot >". Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/da850evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index b1bce11e29..cf0ceac4e3 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -160,7 +160,7 @@ * U-Boot general configuration */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "DA850-evm > " /* Command Prompt */ +#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ From cf2c24e3996e49a26b449ab7daf843856b35b5c8 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:19:28 -0400 Subject: [PATCH 112/145] da850: add support to wake up DSP during board init add support for DSP wake-up by default on DA850/OMAP-L138 during board initialization. Enable hwconfig environment and added extra env setting through CONFIG_EXTRA_ENV_SETTINGS. To prevent DSP from being woken up,set the environment variable as, set hwconfig "dsp:wake=no" Signed-off-by: Sekhar Nori Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++ board/davinci/da8xxevm/da850evm.c | 59 ++++++++++++++++++++ include/configs/da850evm.h | 3 + 3 files changed, 66 insertions(+) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 646e2ced82..4a3af7d3b6 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -153,7 +153,11 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 #define DAVINCI_INTC_BASE 0xfffee000 #define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define DAVINCI_L3CBARAM_BASE 0x80000000 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) +#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) +#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index d3d965cdab..8c3d64e787 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -30,6 +30,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -163,6 +164,64 @@ const struct pinmux_config nor_pins[] = { #endif #endif /* CONFIG_DRIVER_TI_EMAC */ +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) *10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + return 0; +} + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index cf0ceac4e3..9c924896b3 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -159,6 +159,7 @@ /* * U-Boot general configuration */ +#define CONFIG_MISC_INIT_R #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -179,12 +180,14 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS \ "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" #define CONFIG_BOOTDELAY 3 +#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" /* * U-Boot commands From 8cf47399659a0d5d8fb4aa323a4bea1c50e16a41 Mon Sep 17 00:00:00 2001 From: "Manjunathappa, Prakash" Date: Sat, 3 Sep 2011 22:19:56 -0400 Subject: [PATCH 113/145] da850: add support for Spectrum Digital AM18xx EVM The AM18xx EVM contains winbond SPI flash instead of ST SPI flash in comparison with logic PD da850/omap-l138 EVM. So enable configuration to look for winbond flash. Signed-off-by: Manjunathappa, Prakash Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- include/configs/da850evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 9c924896b3..f6068a2b34 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -79,6 +79,7 @@ #define CONFIG_SPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) From ba511f779a584f77b4b798fc40685bfe8d3d5163 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:20:33 -0400 Subject: [PATCH 114/145] da850: fix the channel number for EMAC teardown init TX and RX channel numbers programmed as '1' during EMAC teardown initialization is wrong. This patch fixes the same by setting channel number to '0' which is used by U-boot. Signed-off-by: Sugumar Natarajan Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- drivers/net/davinci_emac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 66c0d13c2b..c0b8929258 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -457,7 +457,7 @@ static void davinci_eth_ch_teardown(int ch) if (ch == EMAC_CH_TX) { /* Init TX channel teardown */ - writel(1, &adap_emac->TXTEARDOWN); + writel(0, &adap_emac->TXTEARDOWN); do { /* * Wait here for Tx teardown completion interrupt to @@ -476,7 +476,7 @@ static void davinci_eth_ch_teardown(int ch) writel(0, &adap_emac->TX0HDP); } else { /* Init RX channel teardown */ - writel(1, &adap_emac->RXTEARDOWN); + writel(0, &adap_emac->RXTEARDOWN); do { /* * Wait here for Rx teardown completion interrupt to From 0f3d6b06ea06e5b0295e4a8222a25bc95a70c026 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:21:04 -0400 Subject: [PATCH 115/145] da850: modifications for Logic PD Rev.3 AM18xx EVM AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++++ board/davinci/da8xxevm/da850evm.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 4a3af7d3b6..692d50755a 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -159,6 +159,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 8c3d64e787..2f950e7bdf 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -109,6 +109,8 @@ const struct pinmux_config nand_pins[] = { #elif defined(CONFIG_USE_NOR) /* NOR pin muxer settings */ const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ { pinmux(5), 1, 6 }, { pinmux(6), 1, 6 }, { pinmux(7), 1, 0 }, @@ -278,6 +280,7 @@ u32 get_board_rev(void) int board_init(void) { + u32 val; #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -325,6 +328,16 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; +#ifdef CONFIG_USE_NOR + /* Set the GPIO direction as output */ + clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as low */ + val = readl(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + writel(val, GPIO_BANK0_REG_CLR_ADDR); +#endif + #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1; From 52d82e40b0332119d14f206555863c77b4f5edb3 Mon Sep 17 00:00:00 2001 From: Bob Feretich Date: Thu, 24 Feb 2011 13:16:44 +0000 Subject: [PATCH 116/145] OMAP3 Beagle Pin Mux initialization glitch fix The below patch reverses the order of two segments in the board file. Output pins need to have their values initialized, before they are exposed to the logic outside the chip. Signed-off-by: Bob Feretich Cc: Wolfgang Denk Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ab50514f25..15d061a008 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -301,17 +301,17 @@ int misc_init_r(void) twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - /* Configure GPIOs to output */ - writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); - writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); - - /* Set GPIOs */ + /* Set GPIO states before they are made outputs */ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + /* Configure GPIOs to output */ + writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + dieid_num_r(); return 0; From 2490e591b4b5450d2b011deac7b07345a1f1daf4 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Thu, 30 Dec 2010 07:19:44 +0000 Subject: [PATCH 117/145] OMAP: Remove omapfb.debug=y from Beagle and Overo env settings The kernel DSS2 code is mature now, and keeping this setting hurts performance Signed-off-by: Steve Sakoman Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 2 -- include/configs/omap3_overo.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ec48abcf46..5e73a62849 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -213,7 +213,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ @@ -221,7 +220,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 821a8a3275..3f3726350e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -169,7 +169,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ @@ -177,7 +176,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ From b16603146ae2f02ecfa3a08a2aca7eaabbf58bb2 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 11 Aug 2011 00:39:28 -0500 Subject: [PATCH 118/145] beagle: pass expansionboard name in bootargs Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 5e73a62849..c67dae2308 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -201,6 +201,7 @@ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ "mpurate=auto\0" \ + "buddy=none "\ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -211,6 +212,7 @@ "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ "mpurate=${mpurate} " \ + "buddy=${buddy} "\ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapdss.def_disp=${defaultdisplay} " \ @@ -218,6 +220,7 @@ "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ "mpurate=${mpurate} " \ + "buddy=${buddy} "\ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapdss.def_disp=${defaultdisplay} " \ From 1ffcb346926ac43b480b0829e7f7196c765d7d98 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 09:37:37 +0200 Subject: [PATCH 119/145] beagleboard: add support for xM revision C Signed-off-by: Koen Kooi Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 10 ++++++++++ board/ti/beagle/beagle.h | 1 + 2 files changed, 11 insertions(+) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 15d061a008..776890104f 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -216,6 +216,16 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; + case REVISION_XM_C: + printf("Beagle xM Rev C\n"); + setenv("beaglerev", "xMC"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; default: printf("Beagle unknown 0x%02x\n", get_board_revision()); MUX_BEAGLE_XM(); diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index a7401b1e7c..04247cdd1c 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -39,6 +39,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_C4 0x5 #define REVISION_XM_A 0x0 #define REVISION_XM_B 0x1 +#define REVISION_XM_C 0x2 /* * IEN - Input Enable From 69716c1900274a89bd5cbd1b0bb276ceaaa04f61 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Wed, 20 Apr 2011 08:54:16 -0500 Subject: [PATCH 120/145] USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor Remove __attribute__ ((packed)) to prevent byte access to soc registers in some gcc versions. Having patches to enable ehci for the BeagleBoard lying around for several months, this one was the show-stopper. Switched to align(4), rather than remove the attribute, per suggestion from Alexander. Credits have to go to Laine Walker-Avina for finding the problem. Signed-off-by: Jason Kridner Signed-off-by: Joel A Fernandes Cc: Alexander Holler Cc: Sandeep Paulraj Signed-off-by: Sandeep Paulraj --- drivers/usb/host/ehci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 945ab64f95..3d0ad0c852 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -55,7 +55,7 @@ struct ehci_hccr { #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) uint32_t cr_hccparams; uint8_t cr_hcsp_portrt[8]; -} __attribute__ ((packed)); +} __attribute__ ((packed, aligned(4))); struct ehci_hcor { uint32_t or_usbcmd; @@ -85,7 +85,7 @@ struct ehci_hcor { #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; uint32_t or_systune; -} __attribute__ ((packed)); +} __attribute__ ((packed, aligned(4))); #define USBMODE 0x68 /* USB Device mode */ #define USBMODE_SDIS (1 << 3) /* Stream disable */ From f44047df3b365e0fdd9be367971ade81b9afdf15 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 09:26:17 +0200 Subject: [PATCH 121/145] BeagleBoard: turn off clocks in ehci_stop This fixes display problems in linux Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 776890104f..a958545776 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -356,6 +356,12 @@ int ehci_hcd_stop(void) pr_debug("Resetting OMAP3 EHCI\n"); omap_set_gpio_dataout(GPIO_PHY_RESET, 0); writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + /* disable USB clocks */ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + sr32(&prcm_base->iclken_usbhost, 0, 1, 0); + sr32(&prcm_base->fclken_usbhost, 0, 2, 0); + sr32(&prcm_base->iclken3_core, 2, 1, 0); + sr32(&prcm_base->fclken3_core, 2, 1, 0); return 0; } From f835ea7158025818d69384a7ebd8c3de0f10a9f7 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Wed, 21 Jul 2010 07:41:25 -0500 Subject: [PATCH 122/145] BeagleBoard: Added userbutton command Based on commit f1099c7c43caf5bac3bf6a65aa266fade4747072 Author: Greg Turner Date: Tue May 25 09:19:06 2010 -0500 New u-boot command for status of USER button on BeagleBoard-xM Modified bootcmd to check the staus at boot time and set filename of the boot script. * Moved to a BeagleBoard specific file. * Removed changes to default boot command from adding userbutton command. * Made to handle pre-xM boards. * Flipped polarity of the return value to avoid confusion. Success (0) is when the button is pressed. Failure (1) is when the button is NOT pressed. * Used latest revision getting function. * Used latest macros for board revision. * Added xM-C revision definition (optional, since it was default) * updated default configuration with UserButton functionality * Added a separate bootenv variable to load a user defined .txt file * Added an example, showing how a different environment file can be loaded with the user button pressed Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Cc: Greg Turner Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 56 ++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 7 ++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index a958545776..8dc8dfa020 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -50,6 +50,7 @@ extern struct ehci_hccr *hccr; extern volatile struct ehci_hcor *hcor; #endif #include "beagle.h" +#include #define pr_debug(fmt, args...) debug(fmt, ##args) @@ -446,3 +447,58 @@ int ehci_hcd_init(void) } #endif /* CONFIG_USB_EHCI */ + +/* + * This command returns the status of the user button on beagle xM + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +int do_userbutton (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int button = 0; + int gpio; + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + switch (get_board_revision()) { + case REVISION_AXBX: + case REVISION_CX: + case REVISION_C4: + gpio = 7; + break; + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + default: + gpio = 4; + break; + } + omap_request_gpio(gpio); + omap_set_gpio_direction(gpio, 1); + printf("The user button is currently "); + if(omap_get_gpio_datain(gpio)) + { + button = 1; + printf("PRESSED.\n"); + } + else + { + button = 0; + printf("NOT pressed.\n"); + } + + omap_free_gpio(gpio); + + return !button; +} + +/* -------------------------------------------------------------------- */ + +U_BOOT_CMD( + userbutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the BeagleBoard USER button", + "" +); diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c67dae2308..c87936498e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -226,7 +226,8 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ @@ -240,8 +241,12 @@ #define CONFIG_BOOTCOMMAND \ "if mmc rescan ${mmcdev}; then " \ + "if userbutton; then " \ + "setenv bootenv user.txt;" \ + "fi;" \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ "run importbootenv;" \ "fi;" \ "if test -n $uenvcmd; then " \ From 3f16ab9102b45e80258821e503ea24d3598ada14 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Tue, 19 Apr 2011 14:01:13 -0500 Subject: [PATCH 123/145] BeagleBoard: Configure DVI/S-video Based on patches from Syed Mohammed Khasim (khasim@ti.com). Configures the output of the BeagleBoard DVI to be orange. Configures the output of the BeagleBoard S-Video to be a colorbar. Changed display_init to beagle_display_init as suggested by Igor Grinberg: http://www.mail-archive.com/u-boot@lists.denx.de/msg51446.html Signed-off-by: Jason Kridner Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 24 +++++++++++ board/ti/beagle/beagle.h | 86 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 8dc8dfa020..13fe39bd00 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -164,6 +164,28 @@ unsigned int get_expansion_id(void) return expansion_config.device_vendor; } +/* + * Configure DSS to display background color on DVID + * Configure VENC to display color bar on S-Video + */ +void beagle_display_init(void) +{ + omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); + switch (get_board_revision()) { + case REVISION_AXBX: + case REVISION_CX: + case REVISION_C4: + omap3_dss_panel_config(&dvid_cfg); + break; + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + default: + omap3_dss_panel_config(&dvid_cfg_xm); + break; + } +} + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -324,6 +346,8 @@ int misc_init_r(void) GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); dieid_num_r(); + beagle_display_init(); + omap3_dss_enable(); return 0; } diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index 04247cdd1c..18bfaa8dec 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -23,6 +23,8 @@ #ifndef _BEAGLE_H_ #define _BEAGLE_H_ +#include + const omap3_sysinfo sysinfo = { DDR_STACKED, "OMAP3 Beagle board", @@ -472,4 +474,88 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/ +/* + * Display Configuration + */ + +#define DVI_BEAGLE_ORANGE_COL 0x00FF8000 +#define VENC_HEIGHT 0x00ef +#define VENC_WIDTH 0x027f + +/* + * Configure VENC in DSS for Beagle to generate Color Bar + * + * Kindly refer to OMAP TRM for definition of these values. + */ +static const struct venc_regs venc_config_std_tv = { + .status = 0x0000001B, + .f_control = 0x00000040, + .vidout_ctrl = 0x00000000, + .sync_ctrl = 0x00008000, + .llen = 0x00008359, + .flens = 0x0000020C, + .hfltr_ctrl = 0x00000000, + .cc_carr_wss_carr = 0x043F2631, + .c_phase = 0x00000024, + .gain_u = 0x00000130, + .gain_v = 0x00000198, + .gain_y = 0x000001C0, + .black_level = 0x0000006A, + .blank_level = 0x0000005C, + .x_color = 0x00000000, + .m_control = 0x00000001, + .bstamp_wss_data = 0x0000003F, + .s_carr = 0x21F07C1F, + .line21 = 0x00000000, + .ln_sel = 0x00000015, + .l21__wc_ctl = 0x00001400, + .htrigger_vtrigger = 0x00000000, + .savid__eavid = 0x069300F4, + .flen__fal = 0x0016020C, + .lal__phase_reset = 0x00060107, + .hs_int_start_stop_x = 0x008D034E, + .hs_ext_start_stop_x = 0x000F0359, + .vs_int_start_x = 0x01A00000, + .vs_int_stop_x__vs_int_start_y = 0x020501A0, + .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, + .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, + .vs_ext_stop_y = 0x00000006, + .avid_start_stop_x = 0x03480079, + .avid_start_stop_y = 0x02040024, + .fid_int_start_x__fid_int_start_y = 0x0001008A, + .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, + .fid_ext_start_y__fid_ext_offset_y = 0x01060006, + .tvdetgp_int_start_stop_x = 0x00140001, + .tvdetgp_int_start_stop_y = 0x00010001, + .gen_ctrl = 0x00FF0000, + .output_control = 0x0000000D, + .dac_b__dac_c = 0x00000000 +}; + +/* + * Configure Timings for DVI D + */ +static const struct panel_config dvid_cfg = { + .timing_h = 0x0ff03f31, /* Horizantal timing */ + .timing_v = 0x01400504, /* Vertical timing */ + .pol_freq = 0x00007028, /* Pol Freq */ + .divisor = 0x00010006, /* 72Mhz Pixel Clock */ + .lcd_size = 0x02ff03ff, /* 1024x768 */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ +}; + +static const struct panel_config dvid_cfg_xm = { + .timing_h = 0x1a4024c9, /* Horizantal timing */ + .timing_v = 0x02c00509, /* Vertical timing */ + .pol_freq = 0x00007028, /* Pol Freq */ + .divisor = 0x00010001, /* 96MHz Pixel Clock */ + .lcd_size = 0x02ff03ff, /* 1024x768 */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ +}; #endif From e5549f0f8b34925e288445e2cb5dcc131a6b304f Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 09:33:03 +0200 Subject: [PATCH 124/145] BeagleBoard: config: load kernel from MMC ext, not FAT Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c87936498e..e46f7fbcb3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -230,7 +230,8 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ From ec556ffccd5ba0902123a0c412b9d17576d4333d Mon Sep 17 00:00:00 2001 From: Joel A Fernandes Date: Sat, 3 Sep 2011 23:22:58 -0400 Subject: [PATCH 125/145] BeagleBoard: config: hardcode MAC for onboard SMSC Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index e46f7fbcb3..03a3084e16 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -199,6 +199,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ + "usbethaddr=de:ad:be:ef\0" \ "console=ttyS2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none "\ From e682930867f7dfc4a01784fe452fad9e962d65a9 Mon Sep 17 00:00:00 2001 From: Joel A Fernandes Date: Sat, 3 Sep 2011 23:24:41 -0400 Subject: [PATCH 126/145] BeagleBoard: config: use uImage.beagle for tftp Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 03a3084e16..223621d956 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -200,6 +200,7 @@ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ "usbethaddr=de:ad:be:ef\0" \ + "bootfile=uImage.beagle\0" \ "console=ttyS2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none "\ From 4c37e8de00ab04d342b57a5515674174c99b880b Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 10:03:06 +0200 Subject: [PATCH 127/145] BeagleBoard: config: decrease bootdelay to 2 seconds Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 223621d956..536d2cd5dc 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -194,7 +194,7 @@ /* partition */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 2 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ From 2162439a26ddc863a800d782f1a697c56fbc7cf9 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 09:31:09 +0200 Subject: [PATCH 128/145] BeagleBoard: config: enable networking Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 536d2cd5dc..9845fc6848 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -128,6 +128,10 @@ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_NET_MULTI /* commands to include */ #include @@ -148,13 +152,15 @@ #define CONFIG_USB_STORAGE /* USB storage support */ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_LED /* LED support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING + #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH #define CONFIG_HARD_I2C 1 From 54b62d590c0a050c3ee87c75a8f58a2a1786ebe1 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Fri, 17 Jun 2011 09:47:08 +0200 Subject: [PATCH 129/145] BeagleBoard: config: enable asix driver and dhcp Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 9845fc6848..253865da59 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -130,6 +130,7 @@ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX #define CONFIG_NET_MULTI @@ -155,7 +156,7 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_PING - +#define CONFIG_CMD_DHCP #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ From 25a4d0175cdde2d8e537f8a27e1612bc80938f03 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Tue, 21 Jun 2011 22:18:01 +0200 Subject: [PATCH 130/145] BeagleBoard: config: enable DSS Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 253865da59..9e6e2fa5ee 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -171,6 +171,7 @@ #define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_I2C_MULTI_BUS 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_VIDEO_OMAP3 /* DSS Support */ /* * TWL4030 From 780a97f8c8a8a0b61c687fbef4a1c8a08d131cda Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Tue, 19 Apr 2011 11:58:54 -0500 Subject: [PATCH 131/145] BeagleBoard: config: make mtest run Utilize the alternate mtest and define a valid region. Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 9e6e2fa5ee..11283ab42e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -286,10 +286,11 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ + /* defaults */ +#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ +#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ From 933d370121e5e303b0e3335655b2e2bec6b1c16e Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Sat, 3 Sep 2011 23:30:34 -0400 Subject: [PATCH 132/145] BeagleBoard: config: increase command-line functionality Enable the expression evaluator. Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 11283ab42e..6c5fa3b7a3 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -157,6 +157,7 @@ #define CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR /* Evaluate expressions */ #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ @@ -282,7 +283,7 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) From c522eac41f198ebf0cdc964bce8c6d7d265dbb9e Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Sat, 3 Sep 2011 23:37:24 -0400 Subject: [PATCH 133/145] BeagleBoard: config: add optargs/buddy/camera buddy and camera are used to configure peripherals in the kernel at boot time that cannot easily be detected by the kernel. Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 6c5fa3b7a3..ec4a16d884 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -213,6 +213,8 @@ "console=ttyS2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none "\ + "optargs=\0" \ + "camera=none\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ "defaultdisplay=dvi\0" \ @@ -222,16 +224,20 @@ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ "mpurate=${mpurate} " \ "buddy=${buddy} "\ + "camera=${camera} "\ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ "mpurate=${mpurate} " \ "buddy=${buddy} "\ + "camera=${camera} "\ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ "omapdss.def_disp=${defaultdisplay} " \ From f74fc4ae6d6257ecdbc0049f6aa2e96212207f05 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Fri, 22 Jul 2011 23:42:44 -0500 Subject: [PATCH 134/145] BeagleBoard: config: Enabled multibus support for I2C in configuration Signed-off-by: Jason Kridner Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ec4a16d884..83c577a8cd 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -114,6 +114,12 @@ /* DDR - I use Micron DDR */ #define CONFIG_OMAP3_MICRON_DDR 1 +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS 1 + +/* Probe all devices */ +#define CONFIG_SYS_I2C_NOPROBES {0x0, 0x0} + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 From f4b36ea92710242e213f8eefff470423a0166eaa Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Sat, 23 Jul 2011 00:01:14 -0500 Subject: [PATCH 135/145] BeagleBoard: config: updated default configuration * Improved boot env var setting * Made room for a 64MB ramdisk by moving from 0x81600000 to 0x81000000 * Added ramarg, ramroot and ramboot env variables Signed-off-by: Jason Kridner Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- include/configs/omap3_beagle.h | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 83c577a8cd..18c6debc01 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -212,7 +212,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + "loadaddr=0x80200000\0" \ + "rdaddr=0x81000000\0" \ "usbtty=cdc_acm\0" \ "usbethaddr=de:ad:be:ef\0" \ "bootfile=uImage.beagle\0" \ @@ -222,13 +223,15 @@ "optargs=\0" \ "camera=none\0" \ "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ + "dvimode=640x480MR-16@60\0" \ "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=/dev/mtdblock4 rw\0" \ "nandrootfstype=jffs2\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ + "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "mpurate=${mpurate} " \ @@ -253,6 +256,16 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "mpurate=${mpurate} " \ + "buddy=${buddy} "\ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ @@ -262,6 +275,9 @@ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "if mmc rescan ${mmcdev}; then " \ From 95492d784b6167a5de47f7aae691646e99f5b623 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Tue, 8 Mar 2011 20:42:01 -0600 Subject: [PATCH 136/145] Corrected LED name match finding avoiding extraneous Usage printouts Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- common/cmd_led.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/cmd_led.c b/common/cmd_led.c index c53195f1a3..8b468486e0 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -83,7 +83,7 @@ int str_onoff (char *var) int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int state, i; + int state, i, match = 0; /* Validate arguments */ if ((argc != 3)) { @@ -98,6 +98,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (i = 0; led_commands[i].string; i++) { if ((strcmp("all", argv[1]) == 0) || (strcmp(led_commands[i].string, argv[1]) == 0)) { + match = 1; if (led_commands[i].on) { if (state) { led_commands[i].on(); @@ -112,7 +113,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } /* If we ran out of matches, print Usage */ - if (!led_commands[i].string && !(strcmp("all", argv[1]) == 0)) { + if (!match) { return cmd_usage(cmdtp); } From f87824efddf3d09d6bb2f01663170f5d7107fd62 Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Tue, 19 Apr 2011 10:55:26 -0500 Subject: [PATCH 137/145] BeagleBoard: fix LED 0/1 in driver Fixed USR0/USR1 to be LED 0/1 respectively Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- board/ti/beagle/led.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c index 08f95a0a16..d3de51f2f5 100644 --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -27,8 +27,8 @@ static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; /* GPIO pins for the LEDs */ -#define BEAGLE_LED_USR0 149 -#define BEAGLE_LED_USR1 150 +#define BEAGLE_LED_USR0 150 +#define BEAGLE_LED_USR1 149 #ifdef STATUS_LED_GREEN void green_LED_off (void) From 4421acf8cdc2afed48f430e4a88eff39df86c0dc Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Wed, 20 Apr 2011 18:11:38 -0500 Subject: [PATCH 138/145] led: added cmd_led to Makefile Addition of cmd_led into the Makefile wasn't included in the patch applied to u-boot-ti. Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- common/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/common/Makefile b/common/Makefile index d66246823c..2edbd71474 100644 --- a/common/Makefile +++ b/common/Makefile @@ -106,6 +106,7 @@ COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o +COBJS-$(CONFIG_CMD_LED) += cmd_led.o COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o COBJS-y += cmd_load.o COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o From 4086b51cb7eac451f96130affbc17094a9e7b75a Mon Sep 17 00:00:00 2001 From: Jason Kridner Date: Wed, 20 Apr 2011 18:13:49 -0500 Subject: [PATCH 139/145] led: correct off/on locations in structure Although the initialization should probably be done with names, the existing implementation has these structures filled in the opposite order. Signed-off-by: Jason Kridner Signed-off-by: Koen Kooi Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- common/cmd_led.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_led.c b/common/cmd_led.c index 8b468486e0..d14dd5adab 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -34,8 +34,8 @@ struct led_tbl_s { char *string; /* String for use in the command */ led_id_t mask; /* Mask used for calling __led_set() */ - void (*on)(void); /* Optional fucntion for turning LED on */ - void (*off)(void); /* Optional fucntion for turning LED on */ + void (*off)(void); /* Optional function for turning LED off */ + void (*on)(void); /* Optional function for turning LED on */ }; typedef struct led_tbl_s led_tbl_t; From d604cda34ab2190fb07a1134bb488105e1a2f9c3 Mon Sep 17 00:00:00 2001 From: Joel A Fernandes Date: Thu, 11 Aug 2011 19:10:19 -0500 Subject: [PATCH 140/145] led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all' Fix for only one led getting set or reset when the led_name is 'all' Previous discussion: http://lists.denx.de/pipermail/u-boot/2011-May/093068.html Changes since v1: Fixed checkpatch if statement error noticed by Sergei. Signed-off-by: Joel A Fernandes Signed-off-by: Jason Kridner Cc: Sergei Shtylyov Signed-off-by: Sandeep Paulraj --- common/cmd_led.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/common/cmd_led.c b/common/cmd_led.c index d14dd5adab..183dc0b42f 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -108,7 +108,9 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } else { __led_set(led_commands[i].mask, state); } - break; + /* Need to set only 1 led if led_name wasn't 'all' */ + if (strcmp("all", argv[1]) != 0) + break; } } From b8bc8973a1830bb92e7a9bf3356dc209afb2f4e8 Mon Sep 17 00:00:00 2001 From: Joel A Fernandes Date: Thu, 11 Aug 2011 23:16:53 -0500 Subject: [PATCH 141/145] led: Remove state-saving of led for toggle functionality and add toggle option to led command * Read the led output state from GPIO instead saving state in memory when it is [re]set * Added a toggle option to the led command Previous discussion: http://lists.denx.de/pipermail/u-boot/2011-May/093068.html Changes since v1: Fixed checkpatch errors Signed-off-by: Joel A Fernandes Signed-off-by: Jason Kridner Signed-off-by: Sandeep Paulraj --- board/ti/beagle/led.c | 28 ++++++++----------- common/cmd_led.c | 64 +++++++++++++++++++++++++++---------------- 2 files changed, 52 insertions(+), 40 deletions(-) diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c index d3de51f2f5..f08c08ad88 100644 --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -24,8 +24,6 @@ #include #include -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - /* GPIO pins for the LEDs */ #define BEAGLE_LED_USR0 150 #define BEAGLE_LED_USR1 149 @@ -49,22 +47,22 @@ void __led_init (led_id_t mask, int state) void __led_toggle (led_id_t mask) { + int state, toggle_gpio = 0; #ifdef STATUS_LED_BIT - if (STATUS_LED_BIT & mask) { - if (STATUS_LED_ON == saved_state[0]) - __led_set(STATUS_LED_BIT, 0); - else - __led_set(STATUS_LED_BIT, 1); - } + if (!toggle_gpio && STATUS_LED_BIT & mask) + toggle_gpio = BEAGLE_LED_USR0; #endif #ifdef STATUS_LED_BIT1 - if (STATUS_LED_BIT1 & mask) { - if (STATUS_LED_ON == saved_state[1]) - __led_set(STATUS_LED_BIT1, 0); - else - __led_set(STATUS_LED_BIT1, 1); - } + if (!toggle_gpio && STATUS_LED_BIT1 & mask) + toggle_gpio = BEAGLE_LED_USR1; #endif + if (toggle_gpio) { + if (!omap_request_gpio(toggle_gpio)) { + omap_set_gpio_direction(toggle_gpio, 0); + state = omap_get_gpio_dataout(toggle_gpio); + omap_set_gpio_dataout(toggle_gpio, !state); + } + } } void __led_set (led_id_t mask, int state) @@ -75,7 +73,6 @@ void __led_set (led_id_t mask, int state) omap_set_gpio_direction(BEAGLE_LED_USR0, 0); omap_set_gpio_dataout(BEAGLE_LED_USR0, state); } - saved_state[0] = state; } #endif #ifdef STATUS_LED_BIT1 @@ -84,7 +81,6 @@ void __led_set (led_id_t mask, int state) omap_set_gpio_direction(BEAGLE_LED_USR1, 0); omap_set_gpio_dataout(BEAGLE_LED_USR1, state); } - saved_state[1] = state; } #endif } diff --git a/common/cmd_led.c b/common/cmd_led.c index 183dc0b42f..0e4ebc59c0 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -36,6 +36,7 @@ struct led_tbl_s { led_id_t mask; /* Mask used for calling __led_set() */ void (*off)(void); /* Optional function for turning LED off */ void (*on)(void); /* Optional function for turning LED on */ + void (*toggle)(void);/* Optional function for toggling LED */ }; typedef struct led_tbl_s led_tbl_t; @@ -43,70 +44,85 @@ typedef struct led_tbl_s led_tbl_t; static const led_tbl_t led_commands[] = { #ifdef CONFIG_BOARD_SPECIFIC_LED #ifdef STATUS_LED_BIT - { "0", STATUS_LED_BIT, NULL, NULL }, + { "0", STATUS_LED_BIT, NULL, NULL, NULL }, #endif #ifdef STATUS_LED_BIT1 - { "1", STATUS_LED_BIT1, NULL, NULL }, + { "1", STATUS_LED_BIT1, NULL, NULL, NULL }, #endif #ifdef STATUS_LED_BIT2 - { "2", STATUS_LED_BIT2, NULL, NULL }, + { "2", STATUS_LED_BIT2, NULL, NULL, NULL }, #endif #ifdef STATUS_LED_BIT3 - { "3", STATUS_LED_BIT3, NULL, NULL }, + { "3", STATUS_LED_BIT3, NULL, NULL, NULL }, #endif #endif #ifdef STATUS_LED_GREEN - { "green", STATUS_LED_GREEN, green_LED_off, green_LED_on }, + { "green", STATUS_LED_GREEN, green_LED_off, green_LED_on, NULL }, #endif #ifdef STATUS_LED_YELLOW - { "yellow", STATUS_LED_YELLOW, yellow_LED_off, yellow_LED_on }, + { "yellow", STATUS_LED_YELLOW, yellow_LED_off, yellow_LED_on, NULL }, #endif #ifdef STATUS_LED_RED - { "red", STATUS_LED_RED, red_LED_off, red_LED_on }, + { "red", STATUS_LED_RED, red_LED_off, red_LED_on, NULL }, #endif #ifdef STATUS_LED_BLUE - { "blue", STATUS_LED_BLUE, blue_LED_off, blue_LED_on }, + { "blue", STATUS_LED_BLUE, blue_LED_off, blue_LED_on, NULL }, #endif - { NULL, 0, NULL, NULL } + { NULL, 0, NULL, NULL, NULL } }; -int str_onoff (char *var) +enum led_cmd { LED_ON, LED_OFF, LED_TOGGLE }; + +enum led_cmd get_led_cmd(char *var) { if (strcmp(var, "off") == 0) { - return 0; + return LED_OFF; } if (strcmp(var, "on") == 0) { - return 1; + return LED_ON; } + if (strcmp(var, "toggle") == 0) + return LED_TOGGLE; return -1; } int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int state, i, match = 0; + int i, match = 0; + enum led_cmd cmd; /* Validate arguments */ if ((argc != 3)) { return cmd_usage(cmdtp); } - state = str_onoff(argv[2]); - if (state < 0) { + cmd = get_led_cmd(argv[2]); + if (cmd < 0) { return cmd_usage(cmdtp); } for (i = 0; led_commands[i].string; i++) { if ((strcmp("all", argv[1]) == 0) || (strcmp(led_commands[i].string, argv[1]) == 0)) { - match = 1; - if (led_commands[i].on) { - if (state) { + match = 1; + switch (cmd) { + case LED_ON: + if (led_commands[i].on) led_commands[i].on(); - } else { + else + __led_set(led_commands[i].mask, 1); + break; + case LED_OFF: + if (led_commands[i].off) led_commands[i].off(); - } - } else { - __led_set(led_commands[i].mask, state); + else + __led_set(led_commands[i].mask, 0); + break; + case LED_TOGGLE: + if (led_commands[i].toggle) + led_commands[i].toggle(); + else + __led_toggle(led_commands[i].mask); } /* Need to set only 1 led if led_name wasn't 'all' */ if (strcmp("all", argv[1]) != 0) @@ -151,6 +167,6 @@ U_BOOT_CMD( #ifdef STATUS_LED_BLUE "blue|" #endif - "all] [on|off]\n", - "led [led_name] [on|off] sets or clears led(s)\n" + "all] [on|off|toggle]\n", + "led [led_name] [on|off|toggle] sets or clears led(s)\n" ); From de701d118380de12a48c8a4fb345e9f909329432 Mon Sep 17 00:00:00 2001 From: Syed Mohammed Khasim Date: Tue, 19 Apr 2011 14:00:34 -0500 Subject: [PATCH 142/145] OMAP3: Add DSS driver for OMAP3 * Supports dynamic panel configuration * Supports dynamic tv standard selection * Adds support for DSS register access through generic APIs * Incorporated DSS register access using structures. * DSS makefile update Previous discussions are here: http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/arch-omap3/dss.h | 174 ++++++++++++++++++++++++++ drivers/video/Makefile | 2 + drivers/video/omap3_dss.c | 131 +++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 arch/arm/include/asm/arch-omap3/dss.h create mode 100644 drivers/video/omap3_dss.c diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h new file mode 100644 index 0000000000..4c56e5e9e6 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Syed Mohammed Khasim + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef DSS_H +#define DSS_H + +/* + * DSS Base Registers + */ +#define OMAP3_DSS_BASE 0x48050040 +#define OMAP3_DISPC_BASE 0x48050440 +#define OMAP3_VENC_BASE 0x48050C00 + +/* DSS Registers */ +struct dss_regs { + u32 control; /* 0x40 */ + u32 sdi_control; /* 0x44 */ + u32 pll_control; /* 0x48 */ +}; + +/* DISPC Registers */ +struct dispc_regs { + u32 control; /* 0x40 */ + u32 config; /* 0x44 */ + u32 reserve_2; /* 0x48 */ + u32 default_color0; /* 0x4C */ + u32 default_color1; /* 0x50 */ + u32 trans_color0; /* 0x54 */ + u32 trans_color1; /* 0x58 */ + u32 line_status; /* 0x5C */ + u32 line_number; /* 0x60 */ + u32 timing_h; /* 0x64 */ + u32 timing_v; /* 0x68 */ + u32 pol_freq; /* 0x6C */ + u32 divisor; /* 0x70 */ + u32 global_alpha; /* 0x74 */ + u32 size_dig; /* 0x78 */ + u32 size_lcd; /* 0x7C */ +}; + +/* VENC Registers */ +struct venc_regs { + u32 rev_id; /* 0x00 */ + u32 status; /* 0x04 */ + u32 f_control; /* 0x08 */ + u32 reserve_1; /* 0x0C */ + u32 vidout_ctrl; /* 0x10 */ + u32 sync_ctrl; /* 0x14 */ + u32 reserve_2; /* 0x18 */ + u32 llen; /* 0x1C */ + u32 flens; /* 0x20 */ + u32 hfltr_ctrl; /* 0x24 */ + u32 cc_carr_wss_carr; /* 0x28 */ + u32 c_phase; /* 0x2C */ + u32 gain_u; /* 0x30 */ + u32 gain_v; /* 0x34 */ + u32 gain_y; /* 0x38 */ + u32 black_level; /* 0x3C */ + u32 blank_level; /* 0x40 */ + u32 x_color; /* 0x44 */ + u32 m_control; /* 0x48 */ + u32 bstamp_wss_data; /* 0x4C */ + u32 s_carr; /* 0x50 */ + u32 line21; /* 0x54 */ + u32 ln_sel; /* 0x58 */ + u32 l21__wc_ctl; /* 0x5C */ + u32 htrigger_vtrigger; /* 0x60 */ + u32 savid__eavid; /* 0x64 */ + u32 flen__fal; /* 0x68 */ + u32 lal__phase_reset; /* 0x6C */ + u32 hs_int_start_stop_x; /* 0x70 */ + u32 hs_ext_start_stop_x; /* 0x74 */ + u32 vs_int_start_x; /* 0x78 */ + u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ + u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ + u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ + u32 vs_ext_stop_y; /* 0x88 */ + u32 reserve_3; /* 0x8C */ + u32 avid_start_stop_x; /* 0x90 */ + u32 avid_start_stop_y; /* 0x94 */ + u32 reserve_4; /* 0x98 */ + u32 reserve_5; /* 0x9C */ + u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ + u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ + u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ + u32 reserve_6; /* 0xAC */ + u32 tvdetgp_int_start_stop_x; /* 0xB0 */ + u32 tvdetgp_int_start_stop_y; /* 0xB4 */ + u32 gen_ctrl; /* 0xB8 */ + u32 reserve_7; /* 0xBC */ + u32 reserve_8; /* 0xC0 */ + u32 output_control; /* 0xC4 */ + u32 dac_b__dac_c; /* 0xC8 */ + u32 height_width; /* 0xCC */ +}; + +/* Few Register Offsets */ +#define FRAME_MODE_SHIFT 1 +#define TFTSTN_SHIFT 3 +#define DATALINES_SHIFT 8 + +/* Enabling Display controller */ +#define LCD_ENABLE 1 +#define DIG_ENABLE (1 << 1) +#define GO_LCD (1 << 5) +#define GO_DIG (1 << 6) +#define GP_OUT0 (1 << 15) +#define GP_OUT1 (1 << 16) + +#define DISPC_ENABLE (LCD_ENABLE | \ + DIG_ENABLE | \ + GO_LCD | \ + GO_DIG | \ + GP_OUT0| \ + GP_OUT1) + +/* Configure VENC DSS Params */ +#define VENC_CLK_ENABLE (1 << 3) +#define DAC_DEMEN (1 << 4) +#define DAC_POWERDN (1 << 5) +#define VENC_OUT_SEL (1 << 6) +#define DIG_LPP_SHIFT 16 +#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \ + DAC_DEMEN | \ + DAC_POWERDN | \ + VENC_OUT_SEL) +/* + * Panel Configuration + */ +struct panel_config { + u32 timing_h; + u32 timing_v; + u32 pol_freq; + u32 divisor; + u32 lcd_size; + u32 panel_type; + u32 data_lines; + u32 load_mode; + u32 panel_color; +}; + +/* + * Generic DSS Functions + */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width); +void omap3_dss_panel_config(const struct panel_config *panel_cfg); +void omap3_dss_enable(void); + +#endif /* DSS_H */ diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 086dc05383..226684ad5d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -41,6 +41,8 @@ COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +COBJS-y += videomodes.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c new file mode 100644 index 0000000000..b322cc3579 --- /dev/null +++ b/drivers/video/omap3_dss.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * Syed Mohammed Khasim + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Configure VENC for a given Mode (NTSC / PAL) + */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width) +{ + struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE; + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + writel(venc_cfg->status, &venc->status); + writel(venc_cfg->f_control, &venc->f_control); + writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl); + writel(venc_cfg->sync_ctrl, &venc->sync_ctrl); + writel(venc_cfg->llen, &venc->llen); + writel(venc_cfg->flens, &venc->flens); + writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl); + writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr); + writel(venc_cfg->c_phase, &venc->c_phase); + writel(venc_cfg->gain_u, &venc->gain_u); + writel(venc_cfg->gain_v, &venc->gain_v); + writel(venc_cfg->gain_y, &venc->gain_y); + writel(venc_cfg->black_level, &venc->black_level); + writel(venc_cfg->blank_level, &venc->blank_level); + writel(venc_cfg->x_color, &venc->x_color); + writel(venc_cfg->m_control, &venc->m_control); + writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data); + writel(venc_cfg->s_carr, &venc->s_carr); + writel(venc_cfg->line21, &venc->line21); + writel(venc_cfg->ln_sel, &venc->ln_sel); + writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl); + writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger); + writel(venc_cfg->savid__eavid, &venc->savid__eavid); + writel(venc_cfg->flen__fal, &venc->flen__fal); + writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset); + writel(venc_cfg->hs_int_start_stop_x, + &venc->hs_int_start_stop_x); + writel(venc_cfg->hs_ext_start_stop_x, + &venc->hs_ext_start_stop_x); + writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x); + writel(venc_cfg->vs_int_stop_x__vs_int_start_y, + &venc->vs_int_stop_x__vs_int_start_y); + writel(venc_cfg->vs_int_stop_y__vs_ext_start_x, + &venc->vs_int_stop_y__vs_ext_start_x); + writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y, + &venc->vs_ext_stop_x__vs_ext_start_y); + writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y); + writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x); + writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y); + writel(venc_cfg->fid_int_start_x__fid_int_start_y, + &venc->fid_int_start_x__fid_int_start_y); + writel(venc_cfg->fid_int_offset_y__fid_ext_start_x, + &venc->fid_int_offset_y__fid_ext_start_x); + writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y, + &venc->fid_ext_start_y__fid_ext_offset_y); + writel(venc_cfg->tvdetgp_int_start_stop_x, + &venc->tvdetgp_int_start_stop_x); + writel(venc_cfg->tvdetgp_int_start_stop_y, + &venc->tvdetgp_int_start_stop_y); + writel(venc_cfg->gen_ctrl, &venc->gen_ctrl); + writel(venc_cfg->output_control, &venc->output_control); + writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c); + + /* Configure DSS for VENC Settings */ + writel(VENC_DSS_CONFIG, &dss->control); + + /* Configure height and width for Digital out */ + writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig); +} + +/* + * Configure Panel Specific Parameters + */ +void omap3_dss_panel_config(const struct panel_config *panel_cfg) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + writel(panel_cfg->timing_h, &dispc->timing_h); + writel(panel_cfg->timing_v, &dispc->timing_v); + writel(panel_cfg->pol_freq, &dispc->pol_freq); + writel(panel_cfg->divisor, &dispc->divisor); + writel(panel_cfg->lcd_size, &dispc->size_lcd); + writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config); + writel(((panel_cfg->panel_type << TFTSTN_SHIFT) | + (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control); + writel(panel_cfg->panel_color, &dispc->default_color0); +} + +/* + * Enable LCD and DIGITAL OUT in DSS + */ +void omap3_dss_enable(void) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + u32 l = 0; + + l = readl(&dispc->control); + l |= DISPC_ENABLE; + writel(l, &dispc->control); +} From 3ecfa9525c2d78a9a8d257a7fd664f61dd10fe21 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Sat, 25 Jun 2011 13:42:47 -0500 Subject: [PATCH 143/145] ehci-hcd: Allow cleanups to happen gracefully on a timeout. With this, the EHCI seems to "recover" from a timeout. This is particularly observable if you were to ping the wrong IP Address and then ping the correct one or if there was a temporary failure during tftp sessions. All it takes is one timeout to disable it. If you have a noisy network (lot of traffic), even if the traffic is not for the board, the timeouts don't occur. Signed-off-by: Joel A Fernandes Signed-off-by: Sandeep Paulraj --- drivers/usb/host/ehci-hcd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 70c02c9deb..2197119cf7 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -461,7 +461,6 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, /* Check that the TD processing happened */ if (token & 0x80) { printf("EHCI timed out on TD - token=%#x\n", token); - goto fail; } /* Disable async schedule. */ From 31c8598425091a859782b804740e43e2a3c915ed Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Fri, 10 Jun 2011 12:21:52 +0000 Subject: [PATCH 144/145] dm3730: enable dpll5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit which is used to provide 120MHz to USB EHCI This allows EHCI to work on BeagleBoard XM Signed-off-by: Eric Bénard Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/omap3/clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 4b66affbee..e0d65c7a4a 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -579,6 +579,7 @@ void prcm_init(void) dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); + dpll5_init_34xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); From 38a77c3adb3ee559b135217769f5c49f3c8b62c9 Mon Sep 17 00:00:00 2001 From: Christian Spielberger Date: Wed, 24 Aug 2011 17:17:31 -0500 Subject: [PATCH 145/145] beagleboard: enable HUB power on all variants of the BeagleBoard Changes made by Jason Kridner with inputs from Eric Benard to special case xM Rev A and xM Rev B Relevant discussions: http://www.mail-archive.com/u-boot@lists.denx.de/msg59361.html http://www.mail-archive.com/u-boot@lists.denx.de/msg59589.html Signed-off-by: Joel A Fernandes Cc: Eric Benard Cc: Christian Spielberger Cc: Jason Kridner Signed-off-by: Sandeep Paulraj --- board/ti/beagle/beagle.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 13fe39bd00..e07f1b8f82 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -332,7 +332,15 @@ int misc_init_r(void) setenv(expansion_config.env_var, expansion_config.env_setting); twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + switch (get_board_revision()) { + case REVISION_XM_A: + case REVISION_XM_B: + twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); + break; + default: + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + break; + } /* Set GPIO states before they are made outputs */ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,