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rockchip: clk: rk3036: correct setting for pll integer mode

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According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang 2017-06-13 10:03:11 +08:00 • committed by Philipp Tomsich
parent 915e09814a
commit 6a464d9cab
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk_rk3036.c
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@ -40,7 +40,7 @@ enum {
#hz "Hz cannot be hit with PLL "\
"divisors on line " __stringify(__LINE__));
/* use interge mode*/
/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
/* use interger mode */
rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
/* use integer mode */
rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,