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Merge "ipq807x: usb: Added SSPHY support"

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Linux Build Service Account 2017-09-15 10:27:29 -07:00 • committed by Gerrit - the friendly Code Review server
commit 678e436e6f
2 changed files with 174 additions and 25 deletions
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118
board/qca/arm/ipq807x/ipq807x.c
View file

@ -565,6 +565,7 @@ static void usb_clock_init(int id)
writel(1, GCC_USB0_MOCK_UTMI_CBCR);
writel(0x8001, GCC_USB0_PHY_CFG_AHB_CBCR);
writel(1, GCC_USB0_AUX_CBCR);
writel(1, GCC_USB0_PIPE_CBCR);
}
else if (id == 1) {
writel(0x222000, GCC_USB1_GDSCR);
@ -584,19 +585,106 @@ static void usb_clock_init(int id)
writel(1, GCC_USB1_MOCK_UTMI_CBCR);
writel(0x8001, GCC_USB1_PHY_CFG_AHB_CBCR);
writel(1, GCC_USB1_AUX_CBCR);
writel(1, GCC_USB1_PIPE_CBCR);
}
}
static void usb_init_ssphy(int index)
{
void __iomem *phybase;
if (index == 0) {
phybase = USB0_SSPHY_BASE;
}
else if (index == 1) {
phybase = USB1_SSPHY_BASE;
}
out_8( phybase + USB3_PHY_POWER_DOWN_CONTROL,0x1);
out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x1a);
out_8(phybase + QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08);
out_8(phybase + QSERDES_COM_CLK_SELECT,0x30);
out_8(phybase + QSERDES_COM_BG_TRIM,0x0f);
out_8(phybase + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b);
out_8(phybase + QSERDES_COM_SVS_MODE_CLK_SEL,0x01);
out_8(phybase + QSERDES_COM_HSCLK_SEL,0x00);
out_8(phybase + QSERDES_COM_CMN_CONFIG,0x06);
out_8(phybase + QSERDES_COM_PLL_IVCO,0x0f);
out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x06);
out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x82);
out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0x55);
out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0x55);
out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x03);
out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x0b);
out_8(phybase + QSERDES_COM_PLL_RCTRL_MODE0,0x16);
out_8(phybase + QSERDES_COM_PLL_CCTRL_MODE0,0x28);
out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0x80);
out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0x15);
out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x34);
out_8(phybase + QSERDES_COM_LOCK_CMP3_MODE0,0x00);
out_8(phybase + QSERDES_COM_CORE_CLK_EN,0x00);
out_8(phybase + QSERDES_COM_LOCK_CMP_CFG,0x00);
out_8(phybase + QSERDES_COM_VCO_TUNE_MAP,0x00);
out_8(phybase + QSERDES_COM_BG_TIMER,0x0a);
out_8(phybase + QSERDES_COM_SSC_EN_CENTER,0x01);
out_8(phybase + QSERDES_COM_SSC_PER1,0x31);
out_8(phybase + QSERDES_COM_SSC_PER2,0x01);
out_8(phybase + QSERDES_COM_SSC_ADJ_PER1,0x00);
out_8(phybase + QSERDES_COM_SSC_ADJ_PER2,0x00);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0xde);
out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x07);
out_8(phybase + QSERDES_RX_UCDR_SO_GAIN,0x06);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c);
out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8);
out_8(phybase + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL,0x77);
out_8(phybase + QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2,0x80);
out_8(phybase + QSERDES_RX_SIGDET_CNTRL,0x03);
out_8(phybase + QSERDES_RX_SIGDET_DEGLITCH_CNTRL,0x16);
out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0c);
out_8(phybase + QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D,0x45);
out_8(phybase + QSERDES_TX_RCV_DETECT_LVL_2,0x12);
out_8(phybase + QSERDES_TX_LANE_MODE,0x06);
out_8(phybase + PCS_TXDEEMPH_M6DB_V0,0x15);
out_8(phybase + PCS_TXDEEMPH_M3P5DB_V0,0x0e);
out_8(phybase + PCS_FLL_CNTRL2,0x83);
out_8(phybase + PCS_FLL_CNTRL1,0x02);
out_8(phybase + PCS_FLL_CNT_VAL_L,0x09);
out_8(phybase + PCS_FLL_CNT_VAL_H_TOL,0xa2);
out_8(phybase + PCS_FLL_MAN_CODE,0x85);
out_8(phybase + PCS_LOCK_DETECT_CONFIG1,0xd1);
out_8(phybase + PCS_LOCK_DETECT_CONFIG2,0x1f);
out_8(phybase + PCS_LOCK_DETECT_CONFIG3,0x47);
out_8(phybase + PCS_POWER_STATE_CONFIG2,0x1b);
out_8(phybase + PCS_RXEQTRAINING_WAIT_TIME,0x75);
out_8(phybase + PCS_RXEQTRAINING_RUN_TIME,0x13);
out_8(phybase + PCS_LFPS_TX_ECSTART_EQTLOCK,0x86);
out_8(phybase + PCS_PWRUP_RESET_DLY_TIME_AUXCLK,0x04);
out_8(phybase + PCS_TSYNC_RSYNC_TIME,0x44);
out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_L,0xe7);
out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_H,0x03);
out_8(phybase + PCS_RCVR_DTCT_DLY_U3_L,0x40);
out_8(phybase + PCS_RCVR_DTCT_DLY_U3_H,0x00);
out_8(phybase + PCS_RX_SIGDET_LVL,0x88);
out_8(phybase + USB3_PCS_TXDEEMPH_M6DB_V0,0x17);
out_8(phybase + USB3_PCS_TXDEEMPH_M3P5DB_V0,0x0f);
out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0);
out_8(phybase + USB3_PHY_START_CONTROL,0x03);
out_8(phybase + USB3_PHY_SW_RESET,0x00);
}
static void usb_init_phy(int index)
{
void __iomem *boot_clk_ctl, *usb_bcr, *qusb2_phy_bcr;
void __iomem *usb_phy_bcr, *usb_gen_cfg, *usb_guctl, *phy_base;
void __iomem *usb_phy_bcr, *usb3_phy_bcr, *usb_gen_cfg, *usb_guctl, *phy_base;
if (index == 0) {
boot_clk_ctl = GCC_USB_0_BOOT_CLOCK_CTL;
usb_bcr = GCC_USB0_BCR;
qusb2_phy_bcr = GCC_QUSB2_0_PHY_BCR;
usb_phy_bcr = GCC_USB0_PHY_BCR;
usb3_phy_bcr = GCC_USB3PHY_0_PHY_BCR;
usb_gen_cfg = USB30_1_GENERAL_CFG;
usb_guctl = USB30_1_GUCTL;
phy_base = USB30_PHY_1_QUSB2PHY_BASE;
@ -606,6 +694,7 @@ static void usb_init_phy(int index)
usb_bcr = GCC_USB1_BCR;
qusb2_phy_bcr = GCC_QUSB2_1_PHY_BCR;
usb_phy_bcr = GCC_USB1_PHY_BCR;
usb3_phy_bcr = GCC_USB3PHY_1_PHY_BCR;
usb_gen_cfg = USB30_2_GENERAL_CFG;
usb_guctl = USB30_2_GUCTL;
phy_base = USB30_PHY_2_QUSB2PHY_BASE;
@ -613,7 +702,6 @@ static void usb_init_phy(int index)
else {
return;
}
//2. Enable SS Ref Clock
setbits_le32(GCC_USB_SS_REF_CLK_EN, 0x1);
@ -628,17 +716,18 @@ static void usb_init_phy(int index)
//6. GCC Reset USB0 BCR
clrbits_le32(usb_bcr, 0x1);
//7. GCC_QUSB2_0_PHY_BCR
setbits_le32(qusb2_phy_bcr, 0x1);
//8. GCC_USB0_PHY_BCR
setbits_le32(usb_phy_bcr, 0x1);
setbits_le32(usb3_phy_bcr, 0x1);
//9. Delay 100us
mdelay(10);
//10. GCC_USB0_PHY_BCR
clrbits_le32(usb3_phy_bcr, 0x1);
clrbits_le32(usb_phy_bcr, 0x1);
//11. GCC_QUSB2_0_PHY_BCR
@ -647,27 +736,6 @@ static void usb_init_phy(int index)
//12. Delay 100us
mdelay(10);
//13. Enable PIPE_UTMI_CLK_DIS
setbits_le32(usb_gen_cfg, 0x100);
//14. Delay 100us
mdelay(10);
//15. Enable PIPE_UTMI_CLK_SEL
setbits_le32(usb_gen_cfg, 0x1);
//16. Delay 100us
mdelay(10);
//17. Enable PIPE3_PHYSTATUS_SW
setbits_le32(usb_gen_cfg, 0x8);
//18. Delay 100us
mdelay(10);
//19. Disable PIPE_UTMI_CLK_DIS
clrbits_le32(usb_gen_cfg, 0x100);
//20. Config user control register
writel(0x0c80c010, usb_guctl);
@ -690,6 +758,8 @@ static void usb_init_phy(int index)
//23. Disable USB2 PHY Power down
clrbits_le32(phy_base+0xB4, 0x1);
usb_init_ssphy(index);
}
int ipq_board_usb_init(void)

81
board/qca/arm/ipq807x/ipq807x.h
View file

@ -100,9 +100,11 @@
#define GCC_USB0_BCR 0x183E070
#define GCC_QUSB2_0_PHY_BCR 0x184103C
#define GCC_USB0_PHY_BCR 0x183E034
#define GCC_USB3PHY_0_PHY_BCR 0x183E03C
#define USB30_1_GENERAL_CFG 0x8AF8808
#define USB30_1_GUCTL 0x8A0C12C
#define USB30_PHY_1_QUSB2PHY_BASE 0x79000
#define GCC_USB0_PIPE_CBCR 0x183E040
#define GCC_USB1_GDSCR 0x183F078
#define GCC_SYS_NOC_USB1_AXI_CBCR 0x1826044
@ -123,12 +125,89 @@
#define GCC_USB1_BCR 0x183F070
#define GCC_QUSB2_1_PHY_BCR 0x1841040
#define GCC_USB1_PHY_BCR 0x183F034
#define GCC_USB3PHY_1_PHY_BCR 0x183F03C
#define USB30_2_GENERAL_CFG 0x8CF8808
#define USB30_2_GUCTL 0x8C0C12C
#define USB30_PHY_2_QUSB2PHY_BASE 0x59000
#define GCC_USB1_PIPE_CBCR 0x183F040
#define KERNEL_AUTH_CMD 0x13
#define KERNEL_AUTH_CMD 0x13
#define USB0_SSPHY_BASE 0x78000
#define USB1_SSPHY_BASE 0x58000
#define USB3_PHY_POWER_DOWN_CONTROL 0x804
#define QSERDES_COM_SYSCLK_EN_SEL 0xac
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x34
#define QSERDES_COM_CLK_SELECT 0x174
#define QSERDES_COM_BG_TRIM 0x70
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
#define QSERDES_COM_HSCLK_SEL 0x178
#define QSERDES_COM_CMN_CONFIG 0x194
#define QSERDES_COM_PLL_IVCO 0x048
#define QSERDES_COM_SYS_CLK_CTRL 0x3c
#define QSERDES_COM_DEC_START_MODE0 0xd0
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0xdc
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0xe0
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0xe4
#define QSERDES_COM_CP_CTRL_MODE0 0x78
#define QSERDES_COM_PLL_RCTRL_MODE0 0x84
#define QSERDES_COM_PLL_CCTRL_MODE0 0x90
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
#define QSERDES_COM_LOCK_CMP1_MODE0 0x4c
#define QSERDES_COM_LOCK_CMP2_MODE0 0x50
#define QSERDES_COM_LOCK_CMP3_MODE0 0x54
#define QSERDES_COM_CORE_CLK_EN 0x18c
#define QSERDES_COM_LOCK_CMP_CFG 0xcc
#define QSERDES_COM_VCO_TUNE_MAP 0x128
#define QSERDES_COM_BG_TIMER 0x0c
#define QSERDES_COM_SSC_EN_CENTER 0x10
#define QSERDES_COM_SSC_PER1 0x1c
#define QSERDES_COM_SSC_PER2 0x20
#define QSERDES_COM_SSC_ADJ_PER1 0x14
#define QSERDES_COM_SSC_ADJ_PER2 0x18
#define QSERDES_COM_SSC_STEP_SIZE1 0x24
#define QSERDES_COM_SSC_STEP_SIZE2 0x28
#define QSERDES_RX_UCDR_SO_GAIN 0x410
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4d8
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4dc
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x4e0
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL 0x508
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x50c
#define QSERDES_RX_SIGDET_CNTRL 0x514
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x51c
#define QSERDES_RX_SIGDET_ENABLES 0x510
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D 0x268
#define QSERDES_TX_RCV_DETECT_LVL_2 0x2ac
#define QSERDES_TX_LANE_MODE 0x294
#define PCS_TXDEEMPH_M6DB_V0 0x824
#define PCS_TXDEEMPH_M3P5DB_V0 0x828
#define PCS_FLL_CNTRL2 0x8c8
#define PCS_FLL_CNTRL1 0x8c4
#define PCS_FLL_CNT_VAL_L 0x8cc
#define PCS_FLL_CNT_VAL_H_TOL 0x8d0
#define PCS_FLL_MAN_CODE 0x8d4
#define PCS_LOCK_DETECT_CONFIG1 0x880
#define PCS_LOCK_DETECT_CONFIG2 0x884
#define PCS_LOCK_DETECT_CONFIG3 0x888
#define PCS_POWER_STATE_CONFIG2 0x864
#define PCS_RXEQTRAINING_WAIT_TIME 0x8b8
#define PCS_RXEQTRAINING_RUN_TIME 0x8bc
#define PCS_LFPS_TX_ECSTART_EQTLOCK 0x8b0
#define PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x8a0
#define PCS_TSYNC_RSYNC_TIME 0x88c
#define PCS_RCVR_DTCT_DLY_P1U2_L 0x870
#define PCS_RCVR_DTCT_DLY_P1U2_H 0x874
#define PCS_RCVR_DTCT_DLY_U3_L 0x878
#define PCS_RCVR_DTCT_DLY_U3_H 0x87c
#define PCS_RX_SIGDET_LVL 0x9d8
#define USB3_PHY_START_CONTROL 0x808
#define USB3_PHY_SW_RESET 0x800
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x440
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4dc
#define QSERDES_RX_SIGDET_ENABLES 0x510
#define USB3_PCS_TXDEEMPH_M6DB_V0 0x824
#define USB3_PCS_TXDEEMPH_M3P5DB_V0 0x828
typedef enum {
SMEM_SPINLOCK_ARRAY = 7,
SMEM_AARM_PARTITION_TABLE = 9,